1 /*
2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this list of
9 * conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
12 * of conditions and the following disclaimer in the documentation and/or other materials
13 * provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
16 * to endorse or promote products derived from this software without specific prior written
17 * permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include "los_config.h"
33 #include "gic_common.h"
34 #include "los_printf.h"
35 #include "los_smp.h"
36 #include "los_vm_map.h"
37 #include "los_vm_zone.h"
38 #include "los_vm_boot.h"
39 #include "los_mmu_descriptor_v6.h"
40 #include "los_init.h"
41
42 #ifdef LOSCFG_KERNEL_SMP
43 #define BOOTROM_PHYS_BASE 0
44 #define BOOTROM_VIRT_BASE (PERIPH_UNCACHED_BASE + PERIPH_UNCACHED_SIZE)
45 #define BOOTROM_MEM_SIZE 0x100000
46
47 /* The startEntry is physical addr. */
bootaddr_setup(UINTPTR startEntry)48 STATIC VOID bootaddr_setup(UINTPTR startEntry)
49 {
50 UINTPTR *startAddrBae = (UINTPTR *)BOOTROM_VIRT_BASE;
51
52 /*
53 * 0xe51ff004 = "ldr pc, [pc, #-4]"
54 * next addr value will be the real booting addr
55 */
56 *startAddrBae = 0xe51ff004;
57 startAddrBae++;
58 *startAddrBae = startEntry;
59
60 DCacheInvRange(BOOTROM_VIRT_BASE, BOOTROM_VIRT_BASE + 8);
61 }
62
63 #ifdef LOSCFG_TEE_ENABLE
64 #define TSP_CPU_ON 0xb2000011UL
raw_smc_send(UINT32 cmd)65 STATIC INT32 raw_smc_send(UINT32 cmd)
66 {
67 register UINT32 smc_id asm("r0") = cmd;
68 do {
69 asm volatile (
70 "mov r0, %[a0]\n"
71 "smc #0\n"
72 : [a0] "+r"(smc_id)
73 );
74 } while (0);
75
76 return (INT32)smc_id;
77 }
78
trigger_secondary_cpu(VOID)79 STATIC VOID trigger_secondary_cpu(VOID)
80 {
81 (VOID)raw_smc_send(TSP_CPU_ON);
82 }
83
release_secondary_cores(UINT32 cpuNum,UINTPTR startEntry)84 LITE_OS_SEC_TEXT_INIT INT32 release_secondary_cores(UINT32 cpuNum, UINTPTR startEntry)
85 {
86 PRINT_RELEASE("releasing %u secondary cores\n", cpuNum);
87
88 bootaddr_setup(startEntry);
89
90 trigger_secondary_cpu();
91
92 return 0;
93 }
94 #else
95 #define CLEAR_RESET_REG_STATUS(regval) (regval) &= ~(1U << 2)
release_secondary_cores(UINT32 cpuNum,UINTPTR startEntry)96 LITE_OS_SEC_TEXT_INIT INT32 release_secondary_cores(UINT32 cpuNum, UINTPTR startEntry)
97 {
98 UINT32 regval;
99
100 PRINT_RELEASE("releasing %u secondary cores\n", cpuNum);
101
102 bootaddr_setup(startEntry);
103
104 /* clear the second cpu reset status */
105 READ_UINT32(regval, PERI_CRG30_BASE);
106 CLEAR_RESET_REG_STATUS(regval);
107 WRITE_UINT32(regval, PERI_CRG30_BASE);
108
109 return 0;
110 }
111 #endif /* LOSCFG_TEE_ENABLE */
112
113 STATIC struct SmpOps g_hisiSmpOps = {
114 .SmpCpuOn = release_secondary_cores,
115 };
116
HisiSmpInit(VOID)117 STATIC VOID HisiSmpInit(VOID)
118 {
119 LOS_SmpOpsSet(&g_hisiSmpOps);
120 }
121
122 LOS_MODULE_INIT(HisiSmpInit, LOS_INIT_LEVEL_EARLIEST);
123 #endif /* LOSCFG_KERNEL_SMP */
124
125 #ifdef LOSCFG_KERNEL_MMU
126 LosArchMmuInitMapping g_archMmuInitMapping[] = {
127 {
128 .phys = SYS_MEM_BASE,
129 .virt = KERNEL_VMM_BASE,
130 .size = KERNEL_VMM_SIZE,
131 .flags = MMU_DESCRIPTOR_KERNEL_L1_PTE_FLAGS,
132 .name = "KernelCached",
133 },
134 {
135 .phys = SYS_MEM_BASE,
136 .virt = UNCACHED_VMM_BASE,
137 .size = UNCACHED_VMM_SIZE,
138 .flags = MMU_INITIAL_MAP_NORMAL_NOCACHE,
139 .name = "KernelUncached",
140 },
141 {
142 .phys = PERIPH_PMM_BASE,
143 .virt = PERIPH_DEVICE_BASE,
144 .size = PERIPH_DEVICE_SIZE,
145 .flags = MMU_INITIAL_MAP_DEVICE,
146 .name = "PeriphDevice",
147 },
148 {
149 .phys = PERIPH_PMM_BASE,
150 .virt = PERIPH_CACHED_BASE,
151 .size = PERIPH_CACHED_SIZE,
152 .flags = MMU_DESCRIPTOR_KERNEL_L1_PTE_FLAGS,
153 .name = "PeriphCached",
154 },
155 {
156 .phys = PERIPH_PMM_BASE,
157 .virt = PERIPH_UNCACHED_BASE,
158 .size = PERIPH_UNCACHED_SIZE,
159 .flags = MMU_INITIAL_MAP_STRONGLY_ORDERED,
160 .name = "PeriphStronglyOrdered",
161 },
162 #ifdef LOSCFG_KERNEL_SMP
163 {
164 .phys = BOOTROM_PHYS_BASE,
165 .virt = BOOTROM_VIRT_BASE,
166 .size = BOOTROM_MEM_SIZE,
167 .flags = MMU_DESCRIPTOR_KERNEL_L1_PTE_FLAGS,
168 .name = "BootRom",
169 },
170 #endif
171 {0}
172 };
173 #endif
174
175