1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef __ASM_PLATFORM_H__ 17 #define __ASM_PLATFORM_H__ 18 19 #include "los_bitmap.h" 20 #include "asm/hal_platform_ints.h" 21 #include "hisoc/timer.h" 22 #include "hisoc/uart.h" 23 24 #ifdef __cplusplus 25 #if __cplusplus 26 extern "C" { 27 #endif /* __cplusplus */ 28 #endif /* __cplusplus */ 29 30 /*------------------------------------------------ 31 * GIC reg base address 32 *------------------------------------------------*/ 33 #define GIC_BASE_ADDR IO_DEVICE_ADDR(0x10300000) 34 #define GICD_OFFSET 0x1000 /* interrupt distributor offset */ 35 #define GICC_OFFSET 0x2000 /* CPU interface register offset */ 36 37 #define DDR_MEM_BASE 0x80000000 38 39 #define FMC_MEM_PBASE 0x14000000 40 #define FMC_MEM_OFFSIZE 0x8 41 42 #define IO_CTL_REG_BASE IO_DEVICE_ADDR(0x10FF0000) 43 44 #define GPIO_REG_ADDR 0x120d0000 45 #define GPIO11_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0xb000) 46 #define GPIO10_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0xa000) 47 #define GPIO9_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x9000) 48 #define GPIO8_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x8000) 49 #define GPIO7_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x7000) 50 #define GPIO6_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x6000) 51 #define GPIO5_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x5000) 52 #define GPIO4_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x4000) 53 #define GPIO3_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x3000) 54 #define GPIO2_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x2000) 55 #define GPIO1_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x1000) 56 #define GPIO0_REG_BASE IO_DEVICE_ADDR(GPIO_REG_ADDR + 0x0000) 57 58 #define SPI_REG_ADDR IO_DEVICE_ADDR(0x120c0000) 59 #define SPI2_REG_BASE (SPI_REG_ADDR + 0x2000) 60 #define SPI1_REG_BASE (SPI_REG_ADDR + 0x1000) 61 #define SPI0_REG_BASE (SPI_REG_ADDR + 0x0000) 62 63 #define I2C_REG_ADDR 0x120b0000 64 #define I2C7_REG_PBASE (I2C_REG_ADDR + 0x7000) 65 #define I2C6_REG_PBASE (I2C_REG_ADDR + 0x6000) 66 #define I2C5_REG_PBASE (I2C_REG_ADDR + 0x5000) 67 #define I2C4_REG_PBASE (I2C_REG_ADDR + 0x4000) 68 #define I2C3_REG_PBASE (I2C_REG_ADDR + 0x3000) 69 #define I2C2_REG_PBASE (I2C_REG_ADDR + 0x2000) 70 #define I2C1_REG_PBASE (I2C_REG_ADDR + 0x1000) 71 #define I2C0_REG_PBASE (I2C_REG_ADDR + 0x0000) 72 73 #define I2C7_REG_BASE IO_DEVICE_ADDR(I2C7_REG_PBASE) 74 #define I2C6_REG_BASE IO_DEVICE_ADDR(I2C6_REG_PBASE) 75 #define I2C5_REG_BASE IO_DEVICE_ADDR(I2C5_REG_PBASE) 76 #define I2C4_REG_BASE IO_DEVICE_ADDR(I2C4_REG_PBASE) 77 #define I2C3_REG_BASE IO_DEVICE_ADDR(I2C3_REG_PBASE) 78 #define I2C2_REG_BASE IO_DEVICE_ADDR(I2C2_REG_PBASE) 79 #define I2C1_REG_BASE IO_DEVICE_ADDR(I2C1_REG_PBASE) 80 #define I2C0_REG_BASE IO_DEVICE_ADDR(I2C0_REG_PBASE) 81 82 #define UART_REG_ADDR 0x120a0000 83 #define UART4_REG_PBASE (UART_REG_ADDR + 0x4000) 84 #define UART3_REG_PBASE (UART_REG_ADDR + 0x3000) 85 #define UART2_REG_PBASE (UART_REG_ADDR + 0x2000) 86 #define UART1_REG_PBASE (UART_REG_ADDR + 0x1000) 87 #define UART0_REG_PBASE (UART_REG_ADDR + 0x0000) 88 #define UART4_REG_BASE IO_DEVICE_ADDR(UART4_REG_PBASE) 89 #define UART3_REG_BASE IO_DEVICE_ADDR(UART3_REG_PBASE) 90 #define UART2_REG_BASE IO_DEVICE_ADDR(UART2_REG_PBASE) 91 #define UART1_REG_BASE IO_DEVICE_ADDR(UART1_REG_PBASE) 92 #define UART0_REG_BASE IO_DEVICE_ADDR(UART0_REG_PBASE) 93 94 #define MISC_REG_BASE IO_DEVICE_ADDR(0x12030000) 95 #define SYS_CTRL_REG_BASE IO_DEVICE_ADDR(0x12020000) 96 97 #define CRG_REG_ADDR 0x12010000 98 #define CRG_REG_BASE IO_DEVICE_ADDR(CRG_REG_ADDR) 99 #define PERI_CRG30_BASE IO_DEVICE_ADDR(CRG_REG_ADDR + 0x0078) /* cpu freq-mode & reset CRG */ 100 101 #define GSF_REG_BASE IO_DEVICE_ADDR(0x12050000) 102 #define SDIO0_REG_PBASE 0x100f0000 103 #define SDIO1_REG_PBASE 0x10020000 104 #define EMMC_REG_PBASE 0x10100000 105 #define MMC_REG_OFFSIZE 0x118 106 107 #define ETH_REG_BASE IO_DEVICE_ADDR(0x10010000) 108 #define ETH_REG_OFFSIZE 0x2000 109 110 #define VIC_REG_BASE IO_DEVICE_ADDR(0x10040000) 111 #define IRQ_REG_BASE VIC_REG_BASE 112 113 #define DMAC_REG_BASE IO_DEVICE_ADDR(0x10060000) 114 #define IO_MUX_REG_BASE IO_DEVICE_ADDR(0x12040000) 115 #define FMC_REG_PBASE 0x10000000 116 #define FMC_REG_OFFSIZE 0xdc 117 118 #define TIMER0_ENABLE BIT(16) 119 #define TIMER1_ENABLE BIT(17) 120 #define TIMER2_ENABLE BIT(18) 121 #define TIMER3_ENABLE BIT(19) 122 #define TIMER4_ENABLE BIT(20) 123 #define TIMER5_ENABLE BIT(21) 124 #define TIMER6_ENABLE BIT(22) 125 #define TIMER7_ENABLE BIT(23) 126 127 #define TIMER7_REG_BASE IO_DEVICE_ADDR(0x12003020) 128 #define TIMER6_REG_BASE IO_DEVICE_ADDR(0x12003000) 129 #define TIMER5_REG_BASE IO_DEVICE_ADDR(0x12002020) 130 #define TIMER4_REG_BASE IO_DEVICE_ADDR(0x12002000) 131 #define TIMER3_REG_BASE IO_DEVICE_ADDR(0x12001020) 132 #define TIMER2_REG_BASE IO_DEVICE_ADDR(0x12001000) 133 #define TIMER1_REG_BASE IO_DEVICE_ADDR(0x12000020) 134 #define TIMER0_REG_BASE IO_DEVICE_ADDR(0x12000000) 135 136 #define TIMER_TICK_REG_BASE TIMER4_REG_BASE /* timer for tick */ 137 #define TIMER_TICK_ENABLE TIMER4_ENABLE 138 #define TIMER_TIME_REG_BASE TIMER5_REG_BASE /* timer for time */ 139 #define TIMER_TIME_ENABLE TIMER5_ENABLE 140 #define HRTIMER_TIMER_REG_BASE TIMER7_REG_BASE /* timer for hrtimer */ 141 #define HRTIMER_TIMER_ENABLE TIMER7_ENABLE 142 143 #define CACHE_ALIGNED_SIZE 64 144 145 #define ARM_REG_BASE IO_DEVICE_ADDR(0x10300000) 146 147 extern void OsReboot(void); 148 extern void InitRebootHook(void); 149 150 #ifdef __cplusplus 151 #if __cplusplus 152 } 153 #endif /* __cplusplus */ 154 #endif /* __cplusplus */ 155 156 #endif 157