1 /*
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16 #ifndef __HISOC_DMAC_H__
17 #define __HISOC_DMAC_H__
18 #include "asm/io.h"
19 #include "asm/platform.h"
20 #ifdef __cplusplus
21 #if __cplusplus
22 extern "C"{
23 #endif
24 #endif /* __cplusplus */
25
26 #define DDRAM_ADRS DDR_MEM_BASE /* fixed */
27 #define DDRAM_SIZE 0x3FFFFFFF /* 1GB DDR. */
28
29
30 #define DMAC_INTSTATUS (DMAC_REG_BASE + 0X00)
31 #define DMAC_INTTCSTATUS (DMAC_REG_BASE + 0X04)
32 #define DMAC_INTTCCLEAR (DMAC_REG_BASE + 0X08)
33 #define DMAC_INTERRORSTATUS (DMAC_REG_BASE + 0X0C)
34 #define DMAC_INTERRCLR (DMAC_REG_BASE + 0X10)
35
36 #define DMAC_RAWINTTCSTATUS (DMAC_REG_BASE + 0X14)
37 #define DMAC_RAWINTERRORSTATUS (DMAC_REG_BASE + 0X18)
38
39 #define DMAC_ENBLDCHNS (DMAC_REG_BASE + 0X1C)
40 #define DMAC_SOFT_BREQ (DMAC_REG_BASE + 0X20)
41 #define DMAC_SOFT_SREQ (DMAC_REG_BASE + 0X24)
42 #define DMAC_SOFT_LBREQ (DMAC_REG_BASE + 0X28)
43 #define DMAC_SOFT_LSREQ (DMAC_REG_BASE + 0X2C)
44
45 #define DMAC_CONFIG (DMAC_REG_BASE + 0X30)
46 #define DMAC_SYNC (DMAC_REG_BASE + 0X34)
47
48 /* the definition for DMAC channel register */
49 #define DMAC_CxBASE(i) (DMAC_REG_BASE + 0x100+i*0x20)
50
51 #define DMAC_CxSRCADDR(i) (DMAC_CxBASE(i) + 0x00)
52 #define DMAC_CxDESTADDR(i) (DMAC_CxBASE(i) + 0x04)
53 #define DMAC_CxLLI(i) (DMAC_CxBASE(i) + 0x08)
54 #define DMAC_CxCONTROL(i) (DMAC_CxBASE(i) + 0x0C)
55 #define DMAC_CxCONFIG(i) (DMAC_CxBASE(i) + 0x10)
56
57 #define DMAC_MAXTRANSFERSIZE 0x0fff /* the max length is denoted by 0-11bit */
58 #define DMAC_CxDISABLE 0x00
59 #define DMAC_CxENABLE 0x01
60
61 /* the means the bit in the channel control register */
62 #define DMAC_CxCONTROL_M2M 0x8d489000 /* Dwidth=32,burst size=4 */
63 #define DMAC_CxCONTROL_LLIM2M 0x0d489000 /* Dwidth=32,burst size=4 */
64 #define DMAC_CxCONTROL_LLIP2M 0x0a000000 // 0x09409000
65 #define DMAC_CxCONTROL_LLIM2P 0x86089000
66
67 #define DMAC_CxCONTROL_INT_EN (0x01 << 31) /* bit:31,enable interrupt */
68
69 #define DMAC_CxLLI_LM 0x01
70 #define DMAC_TRANS_SIZE 0xff0
71
72 #define DMAC_CHANNEL_ENABLE 1
73 #define DMAC_CHANNEL_DISABLE 0xfffffffe
74
75 #define DMAC_CxCONFIG_M2M 0xc000
76 #define DMAC_CxCONFIG_LLIM2M 0xc000
77
78 #define DMAC_CxCONFIG_P2M 0xd000
79 #define DMAC_CxCONFIG_M2P 0xc800
80
81 #define DMAC_CxCONFIG_SIO_P2M 0x0000d000
82 #define DMAC_CxCONFIG_SIO_M2P 0x0000c800
83
84 /* default the config and sync regsiter for DMAC controller */
85 /* M1,M2 little endian, enable DMAC */
86 #define DMAC_CONFIG_VAL 0x01
87 /* enable the sync logic for the 16 peripheral */
88 #define DMAC_SYNC_VAL 0x0
89
90 #define DMAC_MAX_PERIPHERALS 16 // 12
91 #define MEM_MAX_NUM 1
92 #define CHANNEL_NUM 4
93 #define DMAC_MAX_CHANNELS CHANNEL_NUM
94
95 #define PERI_CRG91 (CRG_REG_BASE + 0x16c)
96 #define DMAC_CLK_EN (1 << 5)
97 #define DMAC_SRST_REQ (1 << 4)
98
99
hidmac_clk_en(void)100 static void hidmac_clk_en(void)
101 {
102 unsigned int tmp;
103
104 tmp = readl(PERI_CRG91);
105 tmp |= DMAC_CLK_EN;
106 writel(tmp, PERI_CRG91);
107 }
108
hidmac_unreset(void)109 static void hidmac_unreset(void)
110 {
111 unsigned int tmp;
112
113 tmp = readl(PERI_CRG91);
114 tmp &= ~DMAC_SRST_REQ;
115 writel(tmp, PERI_CRG91);
116 }
117
118 #define PERI_8BIT_MODE 0
119 #define PERI_16BIT_MODE 1
120 #define PERI_32BIT_MODE 2
121
122
123 // hidmac data structure
124
125 /* DMAC peripheral structure */
126 typedef struct dmac_peripheral {
127 /* peripherial ID */
128 unsigned int peri_id;
129 /* peripheral data register address */
130 unsigned int peri_addr;
131 /* default channel control word */
132 unsigned int transfer_ctrl;
133 /* default channel configuration word */
134 unsigned int transfer_cfg;
135 /* default channel configuration word */
136 unsigned int transfer_width;
137 } dmac_peripheral;
138
139 /*
140 * DMA config array!
141 * DREQ, FIFO, CONTROL, CONFIG, BITWIDTH
142 */
143 static dmac_peripheral g_peripheral[DMAC_MAX_PERIPHERALS] = {
144 /* DREQ, FIFO, CONTROL, CONFIG, WIDTH */
145 /* periphal 0: I2C0/I2C1 RX */
146 { 0, I2C1_REG_BASE + 0x10, 0, DMAC_CxCONTROL_LLIP2M | (0 << 1), PERI_8BIT_MODE},
147
148 /* periphal 1: I2C0/I2C1 TX */
149 { 1, I2C1_REG_BASE + 0x10, 0, DMAC_CxCONTROL_LLIP2M | (1 << 1), PERI_8BIT_MODE},
150
151 /* periphal 2: I2C1/I2C2 RX */
152 { 2, I2C1_REG_BASE + 0x10, 0x99000000, DMAC_CxCONTROL_LLIP2M | (2 << 1), PERI_8BIT_MODE}, /* 8bit width */
153
154 /* periphal 3: I2C1/I2C2 TX */
155 { 3, I2C1_REG_BASE + 0x10, 0x96000000, DMAC_CxCONTROL_LLIP2M | (3 << 1), PERI_8BIT_MODE}, /* 8bit width */
156
157 /* periphal 4: UART0 RX */
158 { 4, UART0_REG_BASE + 0x00, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (4 << 1), PERI_8BIT_MODE},
159
160 /* periphal 5: UART0 TX */
161 { 5, UART0_REG_BASE + 0x00, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (5 << 1), PERI_8BIT_MODE},
162
163 /* periphal 6: UART1 RX */
164 { 6, UART1_REG_BASE + 0x00, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (6 << 1), PERI_8BIT_MODE},
165
166 /* periphal 7: UART1 TX */
167 { 7, UART1_REG_BASE + 0x00, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (7 << 1), PERI_8BIT_MODE},
168
169 /* periphal 8: UART2 RX */
170 { 8, UART2_REG_BASE + 0x00, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (8 << 1), PERI_8BIT_MODE},
171
172 /* periphal 9: UART2 TX */
173 { 9, UART2_REG_BASE + 0x00, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (9 << 1), PERI_8BIT_MODE},
174
175 /* periphal 10: UART3 RX */
176 { 10, UART3_REG_BASE + 0x00, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (10 << 1), PERI_8BIT_MODE},
177
178 /* periphal 11: UART0 TX */
179 { 11, UART3_REG_BASE + 0x00, DMAC_CxCONTROL_LLIP2M, DMAC_CxCONFIG_P2M | (11 << 1), PERI_8BIT_MODE},
180
181 /* periphal 12: SSP1 RX */
182 { 12, 0, 0, 0, 0},
183
184 /* periphal 13: SSP1 TX */
185 { 13, 0, 0, 0, 0},
186
187 /* periphal 14: SSP0 RX */
188 { 14, 0, 0, 0, 0},
189
190 /* periphal 15: SSP0 TX */
191 { 15, 0, 0, 0, 0},
192
193 };
194
195 #ifdef __cplusplus
196 #if __cplusplus
197 }
198 #endif
199 #endif /* __cplusplus */
200
201
202 #endif
203