1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef __HISOC_MMC_H_ 17 #define __HISOC_MMC_H_ 18 19 /************************************************************************/ 20 21 #include "asm/platform.h" 22 #include "asm/io.h" 23 #include "himci_v200/himci_reg.h" 24 #include "mmc/mmc_caps.h" 25 #include "hal_timer.h" 26 #include "los_printf.h" 27 28 #ifdef __cplusplus 29 #if __cplusplus 30 extern "C" { 31 #endif /* __cplusplus */ 32 #endif /* __cplusplus */ 33 34 /************************************************************************/ 35 #define EMMC_DDR50 36 #define EMMC_HS200 37 38 #define MMC0 0 39 #define MMC1 1 40 #define MMC2 2 41 42 #define MAX_MMC_NUM 3 43 44 45 /** 46 * MMC HOST usable 47 * Set to 1: usable 48 * Set to 0: not usable 49 * sdio0=1, sdio1=2, EMMC=0 50 **/ 51 #ifdef LOSCFG_DRIVERS_EMMC 52 #define USE_MMC0 1 53 #else 54 #define USE_MMC0 0 55 #endif 56 #define USE_MMC1 1 57 #define USE_MMC2 1 58 59 60 #define MMC_FREQ_150M (150000000) 61 #define MMC_FREQ_100M (100000000) 62 #define MMC_FREQ_50M (50000000) 63 #define MMC_FREQ_25M (25000000) 64 65 #define CONFIG_MMC0_CCLK_MIN 50000 66 #define CONFIG_MMC0_CCLK_MAX MMC_FREQ_100M 67 #define CONFIG_MMC1_CCLK_MIN 50000 68 #define CONFIG_MMC1_CCLK_MAX MMC_FREQ_100M 69 #define CONFIG_MMC2_CCLK_MIN 50000 70 #define CONFIG_MMC2_CCLK_MAX MMC_FREQ_100M 71 72 73 #define CONFIG_MMC0_CLK MMC_FREQ_50M 74 #define CONFIG_MMC1_CLK MMC_FREQ_50M 75 #define CONFIG_MMC2_CLK MMC_FREQ_100M 76 77 78 #define CONFIG_MAX_BLK_COUNT 2048 79 #define CONFIG_MAX_BLK_SIZE 512 80 81 #define HIMMC_PAGE_SIZE 4096 82 83 /* register mapping */ 84 #define PERI_CRG49 (CRG_REG_BASE + 0xC4) 85 #define PERI_CRG50 (CRG_REG_BASE + 0xC8) 86 87 #define PERI_CRG82 (CRG_REG_BASE + 0x0148) 88 #define PERI_CRG83 (CRG_REG_BASE + 0x014C) 89 #define PERI_CRG84 (CRG_REG_BASE + 0x0150) 90 #define PERI_CRG85 (CRG_REG_BASE + 0x0154) 91 92 #define PERI_CRG86 (CRG_REG_BASE + 0x0158) 93 #define PERI_CRG87 (CRG_REG_BASE + 0x015C) 94 #define PERI_CRG88 (CRG_REG_BASE + 0x0160) 95 #define PERI_CRG89 (CRG_REG_BASE + 0x0164) 96 #define PERI_CRG90 (CRG_REG_BASE + 0x0168) 97 98 /* sdio2:eMMC pad ctrl reg */ 99 #define REG_CTRL_EMMC_CCLK (IO_CTL_REG_BASE + 0) 100 #define REG_CTRL_EMMC_CCMD (IO_CTL_REG_BASE + 4) 101 #define REG_CTRL_EMMC_CDATA0 (IO_CTL_REG_BASE + 8) 102 #define REG_CTRL_EMMC_CDATA1 (IO_CTL_REG_BASE + 0xc) 103 #define REG_CTRL_EMMC_CDATA2 (IO_CTL_REG_BASE + 0x10) 104 #define REG_CTRL_EMMC_CDATA3 (IO_CTL_REG_BASE + 0x14) 105 106 #define EMMC_CLK_DS_1V8 0xc0 107 #define EMMC_CMD_DS_1V8 0x150 108 #define EMMC_DATA0_DS_1V8 0x1d0 109 #define EMMC_DATA1_DS_1V8 0x1d0 110 #define EMMC_DATA2_DS_1V8 0x1d0 111 #define EMMC_DATA3_DS_1V8 0x1d0 112 113 #define SDIO_CLK_SEL_MASK (3U << 2) 114 #define SDIO_CLK_SEL_100M (1U << 2) 115 #define SDIO_CLK_SEL_50M (2U << 2) 116 #define SDIO_CLK_SEL_25M (3U << 2) 117 #define SDIO_CKEN (1U << 1) 118 #define SDIO_RESET (1U << 0) 119 120 #define SDIO1_CLK_OFFSET (2) 121 #define SDIO0_CLK_OFFSET (10) 122 123 #define PHASE_SHIFT 0x2030000 124 #define READ_THRESHOLD_SIZE 0x2000005 125 #define DRV_PHASE_SHIFT (0x4) 126 #define SMPL_PHASE_SHIFT (0x1) 127 128 #define DDR50_DRV_PHASE_CFG (0x2) 129 #define SDR104_DRV_PHASE_CFG (0x3) 130 131 #define HIMCI_EDGE_TUNING 132 #define HIMCI_PHASE_SCALE 8 133 #define TUNING_START_PHASE 0 134 #define TUNING_END_PHASE 7 135 136 #define PHASE_NOT_FOUND -1 137 138 #define hi_mci_detect_polarity_cfg(mmc_num) do { } while (0) 139 140 /* EMMC=PERI_CRG82, sdio0=PERI_CRG88, sdio1=PERI_CRG85 */ 141 #define hi_mci_soft_reset(mmc_num) do { \ 142 unsigned int regs[] = {PERI_CRG82, PERI_CRG88, PERI_CRG85}; \ 143 unsigned int val = 0; \ 144 if ((int)mmc_num >= 0 && mmc_num <= 2) { \ 145 val = readl((uintptr_t)regs[mmc_num]); \ 146 PRINT_DEBUG("0x%x:0x%x\n", regs[mmc_num], val); \ 147 HalDelayUs(1000); \ 148 writel(val | 1, (uintptr_t)regs[mmc_num]); \ 149 val &= ~1; \ 150 writel(val, (uintptr_t)regs[mmc_num]); \ 151 PRINT_DEBUG("0x%x:0x%x\n", regs[mmc_num], val); \ 152 } \ 153 } while (0) 154 155 156 /* MCI_FIFOTH(0x4c) details */ 157 #define BURST_SIZE (0x6 << 28) 158 #define RX_WMARK (0x7f << 16) 159 #define TX_WMARK 0x80 160 #define MCI_BMOD_VALUE (BURST_INCR | BURST_16) 161 162 void himci_cfg_phase(unsigned int devid, void *base, enum mmc_bus_timing timing); 163 164 #ifdef __cplusplus 165 #if __cplusplus 166 } 167 #endif /* __cplusplus */ 168 #endif /* __cplusplus */ 169 #endif 170 171