1 /*
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16 #ifndef __HISOC_SPINAND_H__
17 #define __HISOC_SPINAND_H__
18
19 #include "asm/platform.h"
20
21 #ifdef __cplusplus
22 #if __cplusplus
23 extern "C" {
24 #endif /* __cplusplus */
25 #endif /* __cplusplus */
26 /*****************************************************************************/
27 #define CRG48 0xc0
28 #define CRG48_SPI_NAND_CLK_SEL(_clk) (((_clk) & 0x3) << 6)
29 #define CRG48_SPI_NAND_CLK_EN (1 << 5)
30 #define CRG48_SPI_NAND_SOFT_RST_REQ (1 << 4)
31
32 #define SPI_NAND_CLK_SEL_MASK (0x3 << 6)
33 #define DEVICE_TYPE_SHIFT 1
34 #define DEVICE_TYPE_MASK (0x1 << 1)
35
36 #define CLK_24M 0
37 #define CLK_75M 1
38 #define CLK_125M 2
39
40 #define SPI_NAND_CLK_SEL_24M CRG48_SPI_NAND_CLK_SEL(CLK_24M)
41 #define SPI_NAND_CLK_SEL_75M CRG48_SPI_NAND_CLK_SEL(CLK_75M)
42 #define SPI_NAND_CLK_SEL_125M CRG48_SPI_NAND_CLK_SEL(CLK_125M)
43
44 #define GET_CLK_TYPE(_reg) (((_reg) >> 2) & 0x3)
45
46 /*****************************************************************************/
hisnfc100_set_system_clock(int clock,int clk_en)47 static void hisnfc100_set_system_clock(int clock, int clk_en)
48 {
49 unsigned base = CRG_REG_BASE;
50 unsigned regval = readl(base + CRG48);
51
52 if (!clock)
53 clock = SPI_NAND_CLK_SEL_75M;
54 regval = (regval & SPI_NAND_CLK_SEL_MASK) | clock;
55
56 if (clk_en)
57 regval |= CRG48_SPI_NAND_CLK_EN;
58 else
59 regval &= ~CRG48_SPI_NAND_CLK_EN;
60
61 if (readl(base + CRG48) != regval)
62 writel(regval, (base + CRG48));
63 }
64
65 /*****************************************************************************/
hisnfc100_get_best_clock(unsigned int * clock)66 static void hisnfc100_get_best_clock(unsigned int *clock)
67 {
68 int ix;
69 int clk_reg;
70 #define CLK_2X(_clk) (((_clk) + 1) >> 1)
71 unsigned int sysclk[] = {
72 CLK_2X(24), SPI_NAND_CLK_SEL_24M,
73 CLK_2X(75), SPI_NAND_CLK_SEL_75M,
74 CLK_2X(125), SPI_NAND_CLK_SEL_125M,
75 0, 0,
76 };
77 #undef CLK_2X
78
79 clk_reg = SPI_NAND_CLK_SEL_24M;
80 for (ix = 0; sysclk[ix]; ix += 2) {
81 if (*clock < sysclk[ix])
82 break;
83 clk_reg = sysclk[ix + 1];
84 }
85 *clock = clk_reg;
86 }
87
88 #ifdef __cplusplus
89 #if __cplusplus
90 }
91 #endif /* __cplusplus */
92 #endif /* __cplusplus */
93
94 #endif
95
96