1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef _TARGET_CONFIG_H 17 #define _TARGET_CONFIG_H 18 19 20 #ifdef __cplusplus 21 #if __cplusplus 22 extern "C" { 23 #endif /* __cplusplus */ 24 #endif /* __cplusplus */ 25 26 #define OS_SYS_CLOCK (50000000) 27 #define SYS_CTRL_REG_BASE IO_DEVICE_ADDR(0x12020000) 28 #define REG_SC_CTRL 0 29 30 /* smp */ 31 #define CRG_REG_ADDR 0x12010000 32 #define CRG_REG_BASE IO_DEVICE_ADDR(CRG_REG_ADDR) 33 #define PERI_CRG30_BASE IO_DEVICE_ADDR(CRG_REG_ADDR + 0x0078) /* cpu freq-mode & reset CRG */ 34 35 /* memory config */ 36 #define CACHE_ALIGNED_SIZE 64 37 #ifdef LOSCFG_TEE_ENABLE 38 #define DDR_MEM_ADDR 0x81000000 39 #define DDR_MEM_SIZE 0x1f000000 40 #else 41 #define DDR_MEM_ADDR 0x80000000 42 #define DDR_MEM_SIZE 0x20000000 43 #endif 44 /* Peripheral register address base and size */ 45 #define PERIPH_PMM_BASE 0x10000000 46 #define PERIPH_PMM_SIZE 0x10000000 47 #define SYS_MEM_SIZE_DEFAULT 0x07f00000 48 /* hwi */ 49 /** 50 * Maximum number of supported hardware devices that generate hardware interrupts. 51 * The maximum number of hardware devices that generate hardware interrupts is 128. 52 */ 53 #define OS_HWI_MAX_NUM 128 54 /** 55 * Maximum interrupt number. 56 */ 57 #define OS_HWI_MAX ((OS_HWI_MAX_NUM) - 1) 58 /** 59 * Minimum interrupt number. 60 */ 61 #define OS_HWI_MIN 0 62 /** 63 * Maximum usable interrupt number. 64 */ 65 #define OS_USER_HWI_MAX OS_HWI_MAX 66 /** 67 * Minimum usable interrupt number. 68 */ 69 #define OS_USER_HWI_MIN OS_HWI_MIN 70 71 #define NUM_HAL_INTERRUPT_CNTPSIRQ 29 72 #define NUM_HAL_INTERRUPT_CNTPNSIRQ 30 73 #ifdef LOSCFG_TEE_ENABLE 74 #define OS_TICK_INT_NUM NUM_HAL_INTERRUPT_CNTPNSIRQ // use non-secure physical timer for now 75 #else 76 #define OS_TICK_INT_NUM NUM_HAL_INTERRUPT_CNTPSIRQ // use secure physical timer for now 77 #endif 78 79 #define NUM_HAL_INTERRUPT_TIMER7 36 80 #define NUM_HAL_INTERRUPT_UART0 38 81 #define NUM_HAL_INTERRUPT_TEE_SPI_NOTIFY 105 82 83 /* gic */ 84 #define GIC_BASE_ADDR IO_DEVICE_ADDR(0x10300000) 85 #define GICD_OFFSET 0x1000 /* interrupt distributor offset */ 86 #define GICC_OFFSET 0x2000 /* CPU interface register offset */ 87 88 /* timer */ 89 #define TIMER7_REG_BASE IO_DEVICE_ADDR(0x12003020) 90 #define TIMER6_REG_BASE IO_DEVICE_ADDR(0x12003000) 91 #define TIMER5_REG_BASE IO_DEVICE_ADDR(0x12002020) 92 #define TIMER4_REG_BASE IO_DEVICE_ADDR(0x12002000) 93 #define TIMER3_REG_BASE IO_DEVICE_ADDR(0x12001020) 94 #define TIMER2_REG_BASE IO_DEVICE_ADDR(0x12001000) 95 #define TIMER1_REG_BASE IO_DEVICE_ADDR(0x12000020) 96 #define TIMER0_REG_BASE IO_DEVICE_ADDR(0x12000000) 97 98 #define BIT(n) (1U << (n)) 99 #define TIMER4_ENABLE BIT(20) 100 #define TIMER5_ENABLE BIT(21) 101 #define TIMER7_ENABLE BIT(23) 102 103 #define TIMER_TICK_REG_BASE TIMER4_REG_BASE /* timer for tick */ 104 #define TIMER_TICK_ENABLE TIMER4_ENABLE 105 #define TIMER_TIME_REG_BASE TIMER5_REG_BASE /* timer for time */ 106 #define TIMER_TIME_ENABLE TIMER5_ENABLE 107 #define HRTIMER_TIMER_REG_BASE TIMER7_REG_BASE /* timer for hrtimer */ 108 #define HRTIMER_TIMER_ENABLE TIMER7_ENABLE 109 110 #define NUM_HAL_INTERRUPT_HRTIMER NUM_HAL_INTERRUPT_TIMER7 111 112 #define TIMER_LOAD 0x0 113 #define TIMER_VALUE 0x4 114 #define TIMER_CONTROL 0x8 115 #define TIMER_INT_CLR 0xc 116 117 /* uart */ 118 #define UART_REG_ADDR 0x120a0000 119 #define UART0_REG_PBASE (UART_REG_ADDR + 0x0000) 120 #define UART0_REG_BASE IO_DEVICE_ADDR(UART0_REG_PBASE) 121 #define TTY_DEVICE "/dev/uartdev-0" 122 #define UART_REG_BASE UART0_REG_BASE 123 #define NUM_HAL_INTERRUPT_UART NUM_HAL_INTERRUPT_UART0 124 125 #ifdef LOSCFG_DEBUG_VERSION 126 #define LOSCFG_BASE_CORE_TSK_LIMIT 256 127 #endif 128 129 #ifdef __cplusplus 130 #if __cplusplus 131 } 132 #endif /* __cplusplus */ 133 #endif /* __cplusplus */ 134 135 #endif 136