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1# Development Guidelines<a name="EN-US_TOPIC_0000001079036458"></a>
2
3-   [Available APIs](#section158501652121514)
4-   [How to Develop](#section11841123033618)
5-   [Development Example](#section460018317164)
6    -   [Verification](#section1048572415182)
7
8
9When an interrupt request is generated by a peripheral, the CPU suspends the current task and responds to the interrupt request. You need to register the interrupt handler and specify the operation to be performed by the CPU.
10
11## Available APIs<a name="section158501652121514"></a>
12
13The following table describes APIs available for the OpenHarmony LiteOS-M interrupt module. For more details about the APIs, see the API reference.
14
15**Table  1**  APIs of the interrupt module
16
17<a name="table1415203765610"></a>
18<table><thead align="left"><tr id="row134151837125611"><th class="cellrowborder" valign="top" width="12.85128512851285%" id="mcps1.2.4.1.1"><p id="p16415637105612"><a name="p16415637105612"></a><a name="p16415637105612"></a>Category</p>
19</th>
20<th class="cellrowborder" valign="top" width="29.8029802980298%" id="mcps1.2.4.1.2"><p id="p11415163718562"><a name="p11415163718562"></a><a name="p11415163718562"></a>API</p>
21</th>
22<th class="cellrowborder" valign="top" width="57.34573457345735%" id="mcps1.2.4.1.3"><p id="p1641533755612"><a name="p1641533755612"></a><a name="p1641533755612"></a>Description</p>
23</th>
24</tr>
25</thead>
26<tbody><tr id="row0415737175610"><td class="cellrowborder" rowspan="2" valign="top" width="12.85128512851285%" headers="mcps1.2.4.1.1 "><p id="p4917132105710"><a name="p4917132105710"></a><a name="p4917132105710"></a>Creating or deleting interrupts</p>
27</td>
28<td class="cellrowborder" valign="top" width="29.8029802980298%" headers="mcps1.2.4.1.2 "><p id="p341513372561"><a name="p341513372561"></a><a name="p341513372561"></a>HalHwiCreate</p>
29</td>
30<td class="cellrowborder" valign="top" width="57.34573457345735%" headers="mcps1.2.4.1.3 "><p id="p74151037185617"><a name="p74151037185617"></a><a name="p74151037185617"></a>Creates an interrupt and registers the interrupt ID, interrupt triggering mode, interrupt priority, and interrupt handler. When an interrupt is triggered, the interrupt handler will be called.</p>
31</td>
32</tr>
33<tr id="row1841519376561"><td class="cellrowborder" valign="top" headers="mcps1.2.4.1.1 "><p id="p64151837155618"><a name="p64151837155618"></a><a name="p64151837155618"></a>HalHwiDelete</p>
34</td>
35<td class="cellrowborder" valign="top" headers="mcps1.2.4.1.2 "><p id="p441516379562"><a name="p441516379562"></a><a name="p441516379562"></a>Deletes an interrupt based on the specified interrupt ID.</p>
36</td>
37</tr>
38<tr id="row1141513373562"><td class="cellrowborder" rowspan="3" valign="top" width="12.85128512851285%" headers="mcps1.2.4.1.1 "><p id="p956643365710"><a name="p956643365710"></a><a name="p956643365710"></a>Enabling or disabling interrupts</p>
39</td>
40<td class="cellrowborder" valign="top" width="29.8029802980298%" headers="mcps1.2.4.1.2 "><p id="p17765212416"><a name="p17765212416"></a><a name="p17765212416"></a>LOS_IntUnLock</p>
41</td>
42<td class="cellrowborder" valign="top" width="57.34573457345735%" headers="mcps1.2.4.1.3 "><p id="p1972971913115"><a name="p1972971913115"></a><a name="p1972971913115"></a>Enables the CPU to respond to all interrupt requests.</p>
43</td>
44</tr>
45<tr id="row1541513745611"><td class="cellrowborder" valign="top" headers="mcps1.2.4.1.1 "><p id="p1332013246116"><a name="p1332013246116"></a><a name="p1332013246116"></a>LOS_IntLock</p>
46</td>
47<td class="cellrowborder" valign="top" headers="mcps1.2.4.1.2 "><p id="p1692710331219"><a name="p1692710331219"></a><a name="p1692710331219"></a>Disables the CPU from responding to interrupt requests.</p>
48</td>
49</tr>
50<tr id="row14167379561"><td class="cellrowborder" valign="top" headers="mcps1.2.4.1.1 "><p id="p1438619410117"><a name="p1438619410117"></a><a name="p1438619410117"></a>LOS_IntRestore</p>
51</td>
52<td class="cellrowborder" valign="top" headers="mcps1.2.4.1.2 "><p id="p254691522"><a name="p254691522"></a><a name="p254691522"></a>Restores the interrupt status before the <strong id="b12851162254619"><a name="b12851162254619"></a><a name="b12851162254619"></a>LOS_IntLock</strong> and <strong id="b19635152734617"><a name="b19635152734617"></a><a name="b19635152734617"></a>LOS_IntUnLock</strong> operations are performed.</p>
53</td>
54</tr>
55</tbody>
56</table>
57
58## How to Develop<a name="section11841123033618"></a>
59
601.  Create an interrupt by calling  **HalHwiCreate**.
612.  Call  **TestHwiTrigger**  to trigger the specified interrupt. \(This API is defined in the test suite. It simulates an external interrupt by writing the related register of the interrupt controller. Skip this step for common peripheral devices.\)
623.  Call  **HalHwiDelete**  to delete the specified interrupt. Use this API based on actual requirements.
63
64>![](../public_sys-resources/icon-note.gif) **NOTE:**
65>-   Configure the maximum number of interrupts supported and the number of configurable interrupt priorities based on the specific hardware.
66>-   If the interrupt handler takes long time, the CPU cannot respond to interrupt requests in a timely manner.
67>-   Functions that trigger  **LOS\_Schedule**  cannot be directly or indirectly executed during interrupt response process.
68>-   The input parameter of  **LOS\_IntRestore\(\)**  must be the return value of  **LOS\_IntLock\(\)**, that is, the current program status register \(CPSR\) value before the interrupt is disabled. Interrupts 0 to 15 in the Cortex-M series processors are for internal use. You are advised not to apply for or create interrupts 0 to 15.
69
70## Development Example<a name="section460018317164"></a>
71
72This example implements the following:
73
741.  Create an interrupt.
752.  Trigger an interrupt.
763.  Delete an interrupt.
77
78The following sample code shows how to create and delete an interrupt. When the interrupt  **HWI\_NUM\_TEST**  is generated, the interrupt handler function will be called.
79
80```
81#include "los_interrupt.h"
82
83/* Create an interrupt.*/
84#define HWI_NUM_TEST 7
85
86STATIC VOID HwiUsrIrq(VOID)
87{
88    printf("in the func HwiUsrIrq \n");
89}
90
91static UINT32 Example_Interrupt(VOID)
92{
93    UINT32 ret;
94    HWI_PRIOR_T hwiPrio = 3;
95    HWI_MODE_T mode = 0;
96    HWI_ARG_T arg = 0;
97
98    /* Create an interrupt. */
99    ret = HalHwiCreate(HWI_NUM_TEST, hwiPrio, mode, (HWI_PROC_FUNC)HwiUsrIrq, arg);
100    if(ret == LOS_OK){
101        printf("Hwi create success!\n");
102    } else {
103        printf("Hwi create failed!\n");
104        return LOS_NOK;
105    }
106
107    /* Delay 50 ticks. When a hardware interrupt occurs, the HwiUsrIrq function will be called.*/
108    LOS_TaskDelay(50);
109
110    /* Delete an interrupt./
111    ret = HalHwiDelete(HWI_NUM_TEST);
112    if(ret == LOS_OK){
113        printf("Hwi delete success!\n");
114    } else {
115        printf("Hwi delete failed!\n");
116        return LOS_NOK;
117    }
118    return LOS_OK;
119}
120```
121
122### Verification<a name="section1048572415182"></a>
123
124The development is successful if the return result is as follows:
125
126```
127Hwi create success!
128Hwi delete success!.
129```
130
131