1 /* 2 * Copyright (c) 2021 Huawei Device Co., Ltd. 3 * 4 * HDF is dual licensed: you can use it either under the terms of 5 * the GPL, or the BSD license, at your option. 6 * See the LICENSE file in the root of this repository for complete details. 7 */ 8 9 #ifndef MTD_SPI_COMMON_H 10 #define MTD_SPI_COMMON_H 11 12 #include "mtd_core.h" 13 14 #ifdef __cplusplus 15 #if __cplusplus 16 extern "C" { 17 #endif 18 #endif /* __cplusplus */ 19 20 struct SpiFlash; 21 22 struct MtdSpiConfig { 23 uint8_t ifType; 24 uint8_t cmd; 25 uint8_t dummy; 26 uint32_t size; 27 uint32_t clock; 28 }; 29 30 struct MtdSpiOps { 31 int32_t (*waitReady)(struct SpiFlash *spi); 32 int32_t (*writeEnable)(struct SpiFlash *spi); 33 int32_t (*qeEnable)(struct SpiFlash *spi); 34 int32_t (*entry4Addr)(struct SpiFlash *spi, int enable); 35 }; 36 37 struct SpiOpsInfo { 38 uint8_t id[MTD_FLASH_ID_LEN_MAX]; 39 uint8_t idLen; 40 struct MtdSpiOps spiOps; 41 }; 42 43 enum SpiIfType { 44 MTD_SPI_IF_STD = 0, 45 MTD_SPI_IF_DUAL = 1, 46 MTD_SPI_IF_DIO = 2, 47 MTD_SPI_IF_QUAD = 3, 48 MTD_SPI_IF_QIO = 4, 49 }; 50 51 struct SpiFlash { 52 struct MtdDevice mtd; 53 uint8_t cs; 54 uint8_t qeEnable; 55 uint8_t qeSupport; 56 uint32_t addrCycle; 57 struct MtdSpiConfig eraseCfg; 58 struct MtdSpiConfig writeCfg; 59 struct MtdSpiConfig readCfg; 60 struct MtdSpiOps spiOps; 61 }; 62 63 int32_t SpiFlashWaitReady(struct SpiFlash *spi); 64 int32_t SpiFlashWriteEnable(struct SpiFlash *spi); 65 int32_t SpiFlashQeEnable(struct SpiFlash *spi); 66 int32_t SpiFlashEntry4Addr(struct SpiFlash *spi, int enable); 67 68 int32_t SpiFlashAdd(struct SpiFlash *spi); 69 void SpiFlashDel(struct SpiFlash *spi); 70 71 /****************************Spi Common Command Set **************************************/ 72 #define MTD_SPI_CMD_WRSR 0x01 /* Write Status Register */ 73 #define MTD_SPI_CMD_WRITE_STD 0x02 /* Standard page program */ 74 #define MTD_SPI_CMD_READ_STD 0x03 /* Standard page cache */ 75 #define MTD_SPI_CMD_WRDI 0x04 /* Write Disable */ 76 77 #define MTD_SPI_CMD_RDSR 0x05 /* Read Status Register */ 78 #define MTD_SPI_SR_WEL_MASK (1 << 1) 79 #define MTD_SPI_SR_WIP_MASK (1 << 0) 80 #define MTD_SPI_SR_QE_MASK (1 << 6) 81 82 #define MTD_SPI_CMD_WREN 0x06 /* Write Enable */ 83 84 #define MTD_SPI_CMD_GET_FEATURE 0x0F 85 #define MTD_SPI_CMD_SET_FEATURE 0x1F 86 87 #define MTD_SPI_CMD_RDSR3 0x15 /* Read Status Register 3 */ 88 #define MTD_SPI_SR3_4BYTE_SHIFT 5 89 #define MTD_SPI_SR3_4BYTE_MASK (1 << MTD_SPI_SR3_4BYTE_SHIFT) 90 #define MTD_SPI_SR3_IS_4BYTE(sr3) (((sr3) & MTD_SPI_SR3_4BYTE_MASK) >> MTD_SPI_SR3_4BYTE_SHIFT) 91 92 93 #define MTD_SPI_CMD_ERASE_4K 0x20 /* 4KB sector erase */ 94 #define MTD_SPI_CMD_ERASE_64K 0xD8 /* 64KB sector erase */ 95 96 #define MTD_SPI_CMD_WRSR2 0x31 /* Write Status Register 2 */ 97 98 #define MTD_SPI_CMD_RDSR2 0x35 /* Read Status Register 2 */ 99 #define MTD_SPI_CMD_RDCR 0x35 /* Read Config Register */ 100 #define MTD_SPI_CR_QE_MASK (1 << 1) 101 102 #define MTD_SPI_CMD_RDID 0x9F /* Read Identification */ 103 104 #define MTD_SPI_CMD_EN4B 0xB7 /* enter 4 bytes mode and set 4 byte bit */ 105 106 #define MTD_SPI_CMD_EX4B 0xE7 /* exit 4 bytes mode and clear 4 byte bit */ 107 108 109 #define MTD_SPI_CMD_RESET 0xFF 110 111 /**************************** Ohters **************************************/ 112 #define MTD_SPI_CS_MAX 2 113 #define MTD_SPI_STD_OP_ADDR_NUM 3 114 #define MTD_SPI_FEATURE_ECC_ENABLE (1 << 4) 115 #define MTD_SPI_FEATURE_QE_ENABLE (1 << 0) 116 117 118 #ifdef __cplusplus 119 #if __cplusplus 120 121 } 122 #endif 123 #endif /* __cplusplus */ 124 125 #endif /* MTD_SPI_COMMON_H */ 126