1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_DEVICE_H
34 #define MLX5_DEVICE_H
35
36 #include <linux/types.h>
37 #include <rdma/ib_verbs.h>
38 #include <linux/mlx5/mlx5_ifc.h>
39
40 #if defined(__LITTLE_ENDIAN)
41 #define MLX5_SET_HOST_ENDIANNESS 0
42 #elif defined(__BIG_ENDIAN)
43 #define MLX5_SET_HOST_ENDIANNESS 0x80
44 #else
45 #error Host endianness not defined
46 #endif
47
48 /* helper macros */
49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
52 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
53 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
58
59 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
60 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
61 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
62 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
63 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
64 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
65 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
66
67 /* insert a value to a struct */
68 #define MLX5_SET(typ, p, fld, v) do { \
69 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
70 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
71 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
72 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
73 << __mlx5_dw_bit_off(typ, fld))); \
74 } while (0)
75
76 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
77 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
78 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
79 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
80 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
81 << __mlx5_dw_bit_off(typ, fld))); \
82 } while (0)
83
84 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
85 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
86 __mlx5_mask(typ, fld))
87
88 #define MLX5_GET_PR(typ, p, fld) ({ \
89 u32 ___t = MLX5_GET(typ, p, fld); \
90 pr_debug(#fld " = 0x%x\n", ___t); \
91 ___t; \
92 })
93
94 #define MLX5_SET64(typ, p, fld, v) do { \
95 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
96 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
97 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
98 } while (0)
99
100 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
101
102 #define MLX5_GET64_PR(typ, p, fld) ({ \
103 u64 ___t = MLX5_GET64(typ, p, fld); \
104 pr_debug(#fld " = 0x%llx\n", ___t); \
105 ___t; \
106 })
107
108 enum {
109 MLX5_MAX_COMMANDS = 32,
110 MLX5_CMD_DATA_BLOCK_SIZE = 512,
111 MLX5_PCI_CMD_XPORT = 7,
112 MLX5_MKEY_BSF_OCTO_SIZE = 4,
113 MLX5_MAX_PSVS = 4,
114 };
115
116 enum {
117 MLX5_EXTENDED_UD_AV = 0x80000000,
118 };
119
120 enum {
121 MLX5_CQ_STATE_ARMED = 9,
122 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
123 MLX5_CQ_STATE_FIRED = 0xa,
124 };
125
126 enum {
127 MLX5_STAT_RATE_OFFSET = 5,
128 };
129
130 enum {
131 MLX5_INLINE_SEG = 0x80000000,
132 };
133
134 enum {
135 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
136 };
137
138 enum {
139 MLX5_MIN_PKEY_TABLE_SIZE = 128,
140 MLX5_MAX_LOG_PKEY_TABLE = 5,
141 };
142
143 enum {
144 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
145 };
146
147 enum {
148 MLX5_PFAULT_SUBTYPE_WQE = 0,
149 MLX5_PFAULT_SUBTYPE_RDMA = 1,
150 };
151
152 enum {
153 MLX5_PERM_LOCAL_READ = 1 << 2,
154 MLX5_PERM_LOCAL_WRITE = 1 << 3,
155 MLX5_PERM_REMOTE_READ = 1 << 4,
156 MLX5_PERM_REMOTE_WRITE = 1 << 5,
157 MLX5_PERM_ATOMIC = 1 << 6,
158 MLX5_PERM_UMR_EN = 1 << 7,
159 };
160
161 enum {
162 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
163 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
164 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
165 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
166 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
167 };
168
169 enum {
170 MLX5_ACCESS_MODE_PA = 0,
171 MLX5_ACCESS_MODE_MTT = 1,
172 MLX5_ACCESS_MODE_KLM = 2
173 };
174
175 enum {
176 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
177 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
178 MLX5_MKEY_BSF_EN = 1 << 30,
179 MLX5_MKEY_LEN64 = 1 << 31,
180 };
181
182 enum {
183 MLX5_EN_RD = (u64)1,
184 MLX5_EN_WR = (u64)2
185 };
186
187 enum {
188 MLX5_BF_REGS_PER_PAGE = 4,
189 MLX5_MAX_UAR_PAGES = 1 << 8,
190 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
191 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
192 };
193
194 enum {
195 MLX5_MKEY_MASK_LEN = 1ull << 0,
196 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
197 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
198 MLX5_MKEY_MASK_PD = 1ull << 7,
199 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
200 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
201 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
202 MLX5_MKEY_MASK_KEY = 1ull << 13,
203 MLX5_MKEY_MASK_QPN = 1ull << 14,
204 MLX5_MKEY_MASK_LR = 1ull << 17,
205 MLX5_MKEY_MASK_LW = 1ull << 18,
206 MLX5_MKEY_MASK_RR = 1ull << 19,
207 MLX5_MKEY_MASK_RW = 1ull << 20,
208 MLX5_MKEY_MASK_A = 1ull << 21,
209 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
210 MLX5_MKEY_MASK_FREE = 1ull << 29,
211 };
212
213 enum {
214 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
215
216 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
217 MLX5_UMR_CHECK_FREE = (2 << 5),
218
219 MLX5_UMR_INLINE = (1 << 7),
220 };
221
222 #define MLX5_UMR_MTT_ALIGNMENT 0x40
223 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
224 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
225
226 enum mlx5_event {
227 MLX5_EVENT_TYPE_COMP = 0x0,
228
229 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
230 MLX5_EVENT_TYPE_COMM_EST = 0x02,
231 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
232 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
233 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
234
235 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
236 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
237 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
238 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
239 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
240 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
241
242 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
243 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
244 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
245 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
246
247 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
248 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
249
250 MLX5_EVENT_TYPE_CMD = 0x0a,
251 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
252
253 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
254 };
255
256 enum {
257 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
258 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
259 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
260 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
261 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
262 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
263 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
264 };
265
266 enum {
267 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
268 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
269 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
270 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
271 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
272 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
273 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
274 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
275 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
276 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
277 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
278 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
279 };
280
281 enum {
282 MLX5_OPCODE_NOP = 0x00,
283 MLX5_OPCODE_SEND_INVAL = 0x01,
284 MLX5_OPCODE_RDMA_WRITE = 0x08,
285 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
286 MLX5_OPCODE_SEND = 0x0a,
287 MLX5_OPCODE_SEND_IMM = 0x0b,
288 MLX5_OPCODE_LSO = 0x0e,
289 MLX5_OPCODE_RDMA_READ = 0x10,
290 MLX5_OPCODE_ATOMIC_CS = 0x11,
291 MLX5_OPCODE_ATOMIC_FA = 0x12,
292 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
293 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
294 MLX5_OPCODE_BIND_MW = 0x18,
295 MLX5_OPCODE_CONFIG_CMD = 0x1f,
296
297 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
298 MLX5_RECV_OPCODE_SEND = 0x01,
299 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
300 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
301
302 MLX5_CQE_OPCODE_ERROR = 0x1e,
303 MLX5_CQE_OPCODE_RESIZE = 0x16,
304
305 MLX5_OPCODE_SET_PSV = 0x20,
306 MLX5_OPCODE_GET_PSV = 0x21,
307 MLX5_OPCODE_CHECK_PSV = 0x22,
308 MLX5_OPCODE_RGET_PSV = 0x26,
309 MLX5_OPCODE_RCHECK_PSV = 0x27,
310
311 MLX5_OPCODE_UMR = 0x25,
312
313 };
314
315 enum {
316 MLX5_SET_PORT_RESET_QKEY = 0,
317 MLX5_SET_PORT_GUID0 = 16,
318 MLX5_SET_PORT_NODE_GUID = 17,
319 MLX5_SET_PORT_SYS_GUID = 18,
320 MLX5_SET_PORT_GID_TABLE = 19,
321 MLX5_SET_PORT_PKEY_TABLE = 20,
322 };
323
324 enum {
325 MLX5_MAX_PAGE_SHIFT = 31
326 };
327
328 enum {
329 MLX5_ADAPTER_PAGE_SHIFT = 12,
330 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
331 };
332
333 enum {
334 MLX5_CAP_OFF_CMDIF_CSUM = 46,
335 };
336
337 struct mlx5_inbox_hdr {
338 __be16 opcode;
339 u8 rsvd[4];
340 __be16 opmod;
341 };
342
343 struct mlx5_outbox_hdr {
344 u8 status;
345 u8 rsvd[3];
346 __be32 syndrome;
347 };
348
349 struct mlx5_cmd_query_adapter_mbox_in {
350 struct mlx5_inbox_hdr hdr;
351 u8 rsvd[8];
352 };
353
354 struct mlx5_cmd_query_adapter_mbox_out {
355 struct mlx5_outbox_hdr hdr;
356 u8 rsvd0[24];
357 u8 intapin;
358 u8 rsvd1[13];
359 __be16 vsd_vendor_id;
360 u8 vsd[208];
361 u8 vsd_psid[16];
362 };
363
364 enum mlx5_odp_transport_cap_bits {
365 MLX5_ODP_SUPPORT_SEND = 1 << 31,
366 MLX5_ODP_SUPPORT_RECV = 1 << 30,
367 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
368 MLX5_ODP_SUPPORT_READ = 1 << 28,
369 };
370
371 struct mlx5_odp_caps {
372 char reserved[0x10];
373 struct {
374 __be32 rc_odp_caps;
375 __be32 uc_odp_caps;
376 __be32 ud_odp_caps;
377 } per_transport_caps;
378 char reserved2[0xe4];
379 };
380
381 struct mlx5_cmd_init_hca_mbox_in {
382 struct mlx5_inbox_hdr hdr;
383 u8 rsvd0[2];
384 __be16 profile;
385 u8 rsvd1[4];
386 };
387
388 struct mlx5_cmd_init_hca_mbox_out {
389 struct mlx5_outbox_hdr hdr;
390 u8 rsvd[8];
391 };
392
393 struct mlx5_cmd_teardown_hca_mbox_in {
394 struct mlx5_inbox_hdr hdr;
395 u8 rsvd0[2];
396 __be16 profile;
397 u8 rsvd1[4];
398 };
399
400 struct mlx5_cmd_teardown_hca_mbox_out {
401 struct mlx5_outbox_hdr hdr;
402 u8 rsvd[8];
403 };
404
405 struct mlx5_cmd_layout {
406 u8 type;
407 u8 rsvd0[3];
408 __be32 inlen;
409 __be64 in_ptr;
410 __be32 in[4];
411 __be32 out[4];
412 __be64 out_ptr;
413 __be32 outlen;
414 u8 token;
415 u8 sig;
416 u8 rsvd1;
417 u8 status_own;
418 };
419
420
421 struct health_buffer {
422 __be32 assert_var[5];
423 __be32 rsvd0[3];
424 __be32 assert_exit_ptr;
425 __be32 assert_callra;
426 __be32 rsvd1[2];
427 __be32 fw_ver;
428 __be32 hw_id;
429 __be32 rsvd2;
430 u8 irisc_index;
431 u8 synd;
432 __be16 ext_synd;
433 };
434
435 struct mlx5_init_seg {
436 __be32 fw_rev;
437 __be32 cmdif_rev_fw_sub;
438 __be32 rsvd0[2];
439 __be32 cmdq_addr_h;
440 __be32 cmdq_addr_l_sz;
441 __be32 cmd_dbell;
442 __be32 rsvd1[120];
443 __be32 initializing;
444 struct health_buffer health;
445 __be32 rsvd2[884];
446 __be32 health_counter;
447 __be32 rsvd3[1019];
448 __be64 ieee1588_clk;
449 __be32 ieee1588_clk_type;
450 __be32 clr_intx;
451 };
452
453 struct mlx5_eqe_comp {
454 __be32 reserved[6];
455 __be32 cqn;
456 };
457
458 struct mlx5_eqe_qp_srq {
459 __be32 reserved[6];
460 __be32 qp_srq_n;
461 };
462
463 struct mlx5_eqe_cq_err {
464 __be32 cqn;
465 u8 reserved1[7];
466 u8 syndrome;
467 };
468
469 struct mlx5_eqe_port_state {
470 u8 reserved0[8];
471 u8 port;
472 };
473
474 struct mlx5_eqe_gpio {
475 __be32 reserved0[2];
476 __be64 gpio_event;
477 };
478
479 struct mlx5_eqe_congestion {
480 u8 type;
481 u8 rsvd0;
482 u8 congestion_level;
483 };
484
485 struct mlx5_eqe_stall_vl {
486 u8 rsvd0[3];
487 u8 port_vl;
488 };
489
490 struct mlx5_eqe_cmd {
491 __be32 vector;
492 __be32 rsvd[6];
493 };
494
495 struct mlx5_eqe_page_req {
496 u8 rsvd0[2];
497 __be16 func_id;
498 __be32 num_pages;
499 __be32 rsvd1[5];
500 };
501
502 struct mlx5_eqe_page_fault {
503 __be32 bytes_committed;
504 union {
505 struct {
506 u16 reserved1;
507 __be16 wqe_index;
508 u16 reserved2;
509 __be16 packet_length;
510 u8 reserved3[12];
511 } __packed wqe;
512 struct {
513 __be32 r_key;
514 u16 reserved1;
515 __be16 packet_length;
516 __be32 rdma_op_len;
517 __be64 rdma_va;
518 } __packed rdma;
519 } __packed;
520 __be32 flags_qpn;
521 } __packed;
522
523 union ev_data {
524 __be32 raw[7];
525 struct mlx5_eqe_cmd cmd;
526 struct mlx5_eqe_comp comp;
527 struct mlx5_eqe_qp_srq qp_srq;
528 struct mlx5_eqe_cq_err cq_err;
529 struct mlx5_eqe_port_state port;
530 struct mlx5_eqe_gpio gpio;
531 struct mlx5_eqe_congestion cong;
532 struct mlx5_eqe_stall_vl stall_vl;
533 struct mlx5_eqe_page_req req_pages;
534 struct mlx5_eqe_page_fault page_fault;
535 } __packed;
536
537 struct mlx5_eqe {
538 u8 rsvd0;
539 u8 type;
540 u8 rsvd1;
541 u8 sub_type;
542 __be32 rsvd2[7];
543 union ev_data data;
544 __be16 rsvd3;
545 u8 signature;
546 u8 owner;
547 } __packed;
548
549 struct mlx5_cmd_prot_block {
550 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
551 u8 rsvd0[48];
552 __be64 next;
553 __be32 block_num;
554 u8 rsvd1;
555 u8 token;
556 u8 ctrl_sig;
557 u8 sig;
558 };
559
560 enum {
561 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
562 };
563
564 struct mlx5_err_cqe {
565 u8 rsvd0[32];
566 __be32 srqn;
567 u8 rsvd1[18];
568 u8 vendor_err_synd;
569 u8 syndrome;
570 __be32 s_wqe_opcode_qpn;
571 __be16 wqe_counter;
572 u8 signature;
573 u8 op_own;
574 };
575
576 struct mlx5_cqe64 {
577 u8 rsvd0[4];
578 u8 lro_tcppsh_abort_dupack;
579 u8 lro_min_ttl;
580 __be16 lro_tcp_win;
581 __be32 lro_ack_seq_num;
582 __be32 rss_hash_result;
583 u8 rss_hash_type;
584 u8 ml_path;
585 u8 rsvd20[2];
586 __be16 check_sum;
587 __be16 slid;
588 __be32 flags_rqpn;
589 u8 hds_ip_ext;
590 u8 l4_hdr_type_etc;
591 __be16 vlan_info;
592 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
593 __be32 imm_inval_pkey;
594 u8 rsvd40[4];
595 __be32 byte_cnt;
596 __be64 timestamp;
597 __be32 sop_drop_qpn;
598 __be16 wqe_counter;
599 u8 signature;
600 u8 op_own;
601 };
602
get_cqe_lro_tcppsh(struct mlx5_cqe64 * cqe)603 static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
604 {
605 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
606 }
607
get_cqe_l4_hdr_type(struct mlx5_cqe64 * cqe)608 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
609 {
610 return (cqe->l4_hdr_type_etc >> 4) & 0x7;
611 }
612
cqe_has_vlan(struct mlx5_cqe64 * cqe)613 static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
614 {
615 return !!(cqe->l4_hdr_type_etc & 0x1);
616 }
617
618 enum {
619 CQE_L4_HDR_TYPE_NONE = 0x0,
620 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
621 CQE_L4_HDR_TYPE_UDP = 0x2,
622 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
623 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
624 };
625
626 enum {
627 CQE_RSS_HTYPE_IP = 0x3 << 6,
628 CQE_RSS_HTYPE_L4 = 0x3 << 2,
629 };
630
631 enum {
632 CQE_L2_OK = 1 << 0,
633 CQE_L3_OK = 1 << 1,
634 CQE_L4_OK = 1 << 2,
635 };
636
637 struct mlx5_sig_err_cqe {
638 u8 rsvd0[16];
639 __be32 expected_trans_sig;
640 __be32 actual_trans_sig;
641 __be32 expected_reftag;
642 __be32 actual_reftag;
643 __be16 syndrome;
644 u8 rsvd22[2];
645 __be32 mkey;
646 __be64 err_offset;
647 u8 rsvd30[8];
648 __be32 qpn;
649 u8 rsvd38[2];
650 u8 signature;
651 u8 op_own;
652 };
653
654 struct mlx5_wqe_srq_next_seg {
655 u8 rsvd0[2];
656 __be16 next_wqe_index;
657 u8 signature;
658 u8 rsvd1[11];
659 };
660
661 union mlx5_ext_cqe {
662 struct ib_grh grh;
663 u8 inl[64];
664 };
665
666 struct mlx5_cqe128 {
667 union mlx5_ext_cqe inl_grh;
668 struct mlx5_cqe64 cqe64;
669 };
670
671 struct mlx5_srq_ctx {
672 u8 state_log_sz;
673 u8 rsvd0[3];
674 __be32 flags_xrcd;
675 __be32 pgoff_cqn;
676 u8 rsvd1[4];
677 u8 log_pg_sz;
678 u8 rsvd2[7];
679 __be32 pd;
680 __be16 lwm;
681 __be16 wqe_cnt;
682 u8 rsvd3[8];
683 __be64 db_record;
684 };
685
686 struct mlx5_create_srq_mbox_in {
687 struct mlx5_inbox_hdr hdr;
688 __be32 input_srqn;
689 u8 rsvd0[4];
690 struct mlx5_srq_ctx ctx;
691 u8 rsvd1[208];
692 __be64 pas[0];
693 };
694
695 struct mlx5_create_srq_mbox_out {
696 struct mlx5_outbox_hdr hdr;
697 __be32 srqn;
698 u8 rsvd[4];
699 };
700
701 struct mlx5_destroy_srq_mbox_in {
702 struct mlx5_inbox_hdr hdr;
703 __be32 srqn;
704 u8 rsvd[4];
705 };
706
707 struct mlx5_destroy_srq_mbox_out {
708 struct mlx5_outbox_hdr hdr;
709 u8 rsvd[8];
710 };
711
712 struct mlx5_query_srq_mbox_in {
713 struct mlx5_inbox_hdr hdr;
714 __be32 srqn;
715 u8 rsvd0[4];
716 };
717
718 struct mlx5_query_srq_mbox_out {
719 struct mlx5_outbox_hdr hdr;
720 u8 rsvd0[8];
721 struct mlx5_srq_ctx ctx;
722 u8 rsvd1[32];
723 __be64 pas[0];
724 };
725
726 struct mlx5_arm_srq_mbox_in {
727 struct mlx5_inbox_hdr hdr;
728 __be32 srqn;
729 __be16 rsvd;
730 __be16 lwm;
731 };
732
733 struct mlx5_arm_srq_mbox_out {
734 struct mlx5_outbox_hdr hdr;
735 u8 rsvd[8];
736 };
737
738 struct mlx5_cq_context {
739 u8 status;
740 u8 cqe_sz_flags;
741 u8 st;
742 u8 rsvd3;
743 u8 rsvd4[6];
744 __be16 page_offset;
745 __be32 log_sz_usr_page;
746 __be16 cq_period;
747 __be16 cq_max_count;
748 __be16 rsvd20;
749 __be16 c_eqn;
750 u8 log_pg_sz;
751 u8 rsvd25[7];
752 __be32 last_notified_index;
753 __be32 solicit_producer_index;
754 __be32 consumer_counter;
755 __be32 producer_counter;
756 u8 rsvd48[8];
757 __be64 db_record_addr;
758 };
759
760 struct mlx5_create_cq_mbox_in {
761 struct mlx5_inbox_hdr hdr;
762 __be32 input_cqn;
763 u8 rsvdx[4];
764 struct mlx5_cq_context ctx;
765 u8 rsvd6[192];
766 __be64 pas[0];
767 };
768
769 struct mlx5_create_cq_mbox_out {
770 struct mlx5_outbox_hdr hdr;
771 __be32 cqn;
772 u8 rsvd0[4];
773 };
774
775 struct mlx5_destroy_cq_mbox_in {
776 struct mlx5_inbox_hdr hdr;
777 __be32 cqn;
778 u8 rsvd0[4];
779 };
780
781 struct mlx5_destroy_cq_mbox_out {
782 struct mlx5_outbox_hdr hdr;
783 u8 rsvd0[8];
784 };
785
786 struct mlx5_query_cq_mbox_in {
787 struct mlx5_inbox_hdr hdr;
788 __be32 cqn;
789 u8 rsvd0[4];
790 };
791
792 struct mlx5_query_cq_mbox_out {
793 struct mlx5_outbox_hdr hdr;
794 u8 rsvd0[8];
795 struct mlx5_cq_context ctx;
796 u8 rsvd6[16];
797 __be64 pas[0];
798 };
799
800 struct mlx5_modify_cq_mbox_in {
801 struct mlx5_inbox_hdr hdr;
802 __be32 cqn;
803 __be32 field_select;
804 struct mlx5_cq_context ctx;
805 u8 rsvd[192];
806 __be64 pas[0];
807 };
808
809 struct mlx5_modify_cq_mbox_out {
810 struct mlx5_outbox_hdr hdr;
811 u8 rsvd[8];
812 };
813
814 struct mlx5_enable_hca_mbox_in {
815 struct mlx5_inbox_hdr hdr;
816 u8 rsvd[8];
817 };
818
819 struct mlx5_enable_hca_mbox_out {
820 struct mlx5_outbox_hdr hdr;
821 u8 rsvd[8];
822 };
823
824 struct mlx5_disable_hca_mbox_in {
825 struct mlx5_inbox_hdr hdr;
826 u8 rsvd[8];
827 };
828
829 struct mlx5_disable_hca_mbox_out {
830 struct mlx5_outbox_hdr hdr;
831 u8 rsvd[8];
832 };
833
834 struct mlx5_eq_context {
835 u8 status;
836 u8 ec_oi;
837 u8 st;
838 u8 rsvd2[7];
839 __be16 page_pffset;
840 __be32 log_sz_usr_page;
841 u8 rsvd3[7];
842 u8 intr;
843 u8 log_page_size;
844 u8 rsvd4[15];
845 __be32 consumer_counter;
846 __be32 produser_counter;
847 u8 rsvd5[16];
848 };
849
850 struct mlx5_create_eq_mbox_in {
851 struct mlx5_inbox_hdr hdr;
852 u8 rsvd0[3];
853 u8 input_eqn;
854 u8 rsvd1[4];
855 struct mlx5_eq_context ctx;
856 u8 rsvd2[8];
857 __be64 events_mask;
858 u8 rsvd3[176];
859 __be64 pas[0];
860 };
861
862 struct mlx5_create_eq_mbox_out {
863 struct mlx5_outbox_hdr hdr;
864 u8 rsvd0[3];
865 u8 eq_number;
866 u8 rsvd1[4];
867 };
868
869 struct mlx5_destroy_eq_mbox_in {
870 struct mlx5_inbox_hdr hdr;
871 u8 rsvd0[3];
872 u8 eqn;
873 u8 rsvd1[4];
874 };
875
876 struct mlx5_destroy_eq_mbox_out {
877 struct mlx5_outbox_hdr hdr;
878 u8 rsvd[8];
879 };
880
881 struct mlx5_map_eq_mbox_in {
882 struct mlx5_inbox_hdr hdr;
883 __be64 mask;
884 u8 mu;
885 u8 rsvd0[2];
886 u8 eqn;
887 u8 rsvd1[24];
888 };
889
890 struct mlx5_map_eq_mbox_out {
891 struct mlx5_outbox_hdr hdr;
892 u8 rsvd[8];
893 };
894
895 struct mlx5_query_eq_mbox_in {
896 struct mlx5_inbox_hdr hdr;
897 u8 rsvd0[3];
898 u8 eqn;
899 u8 rsvd1[4];
900 };
901
902 struct mlx5_query_eq_mbox_out {
903 struct mlx5_outbox_hdr hdr;
904 u8 rsvd[8];
905 struct mlx5_eq_context ctx;
906 };
907
908 enum {
909 MLX5_MKEY_STATUS_FREE = 1 << 6,
910 };
911
912 struct mlx5_mkey_seg {
913 /* This is a two bit field occupying bits 31-30.
914 * bit 31 is always 0,
915 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
916 */
917 u8 status;
918 u8 pcie_control;
919 u8 flags;
920 u8 version;
921 __be32 qpn_mkey7_0;
922 u8 rsvd1[4];
923 __be32 flags_pd;
924 __be64 start_addr;
925 __be64 len;
926 __be32 bsfs_octo_size;
927 u8 rsvd2[16];
928 __be32 xlt_oct_size;
929 u8 rsvd3[3];
930 u8 log2_page_size;
931 u8 rsvd4[4];
932 };
933
934 struct mlx5_query_special_ctxs_mbox_in {
935 struct mlx5_inbox_hdr hdr;
936 u8 rsvd[8];
937 };
938
939 struct mlx5_query_special_ctxs_mbox_out {
940 struct mlx5_outbox_hdr hdr;
941 __be32 dump_fill_mkey;
942 __be32 reserved_lkey;
943 };
944
945 struct mlx5_create_mkey_mbox_in {
946 struct mlx5_inbox_hdr hdr;
947 __be32 input_mkey_index;
948 __be32 flags;
949 struct mlx5_mkey_seg seg;
950 u8 rsvd1[16];
951 __be32 xlat_oct_act_size;
952 __be32 rsvd2;
953 u8 rsvd3[168];
954 __be64 pas[0];
955 };
956
957 struct mlx5_create_mkey_mbox_out {
958 struct mlx5_outbox_hdr hdr;
959 __be32 mkey;
960 u8 rsvd[4];
961 };
962
963 struct mlx5_destroy_mkey_mbox_in {
964 struct mlx5_inbox_hdr hdr;
965 __be32 mkey;
966 u8 rsvd[4];
967 };
968
969 struct mlx5_destroy_mkey_mbox_out {
970 struct mlx5_outbox_hdr hdr;
971 u8 rsvd[8];
972 };
973
974 struct mlx5_query_mkey_mbox_in {
975 struct mlx5_inbox_hdr hdr;
976 __be32 mkey;
977 };
978
979 struct mlx5_query_mkey_mbox_out {
980 struct mlx5_outbox_hdr hdr;
981 __be64 pas[0];
982 };
983
984 struct mlx5_modify_mkey_mbox_in {
985 struct mlx5_inbox_hdr hdr;
986 __be32 mkey;
987 __be64 pas[0];
988 };
989
990 struct mlx5_modify_mkey_mbox_out {
991 struct mlx5_outbox_hdr hdr;
992 u8 rsvd[8];
993 };
994
995 struct mlx5_dump_mkey_mbox_in {
996 struct mlx5_inbox_hdr hdr;
997 };
998
999 struct mlx5_dump_mkey_mbox_out {
1000 struct mlx5_outbox_hdr hdr;
1001 __be32 mkey;
1002 };
1003
1004 struct mlx5_mad_ifc_mbox_in {
1005 struct mlx5_inbox_hdr hdr;
1006 __be16 remote_lid;
1007 u8 rsvd0;
1008 u8 port;
1009 u8 rsvd1[4];
1010 u8 data[256];
1011 };
1012
1013 struct mlx5_mad_ifc_mbox_out {
1014 struct mlx5_outbox_hdr hdr;
1015 u8 rsvd[8];
1016 u8 data[256];
1017 };
1018
1019 struct mlx5_access_reg_mbox_in {
1020 struct mlx5_inbox_hdr hdr;
1021 u8 rsvd0[2];
1022 __be16 register_id;
1023 __be32 arg;
1024 __be32 data[0];
1025 };
1026
1027 struct mlx5_access_reg_mbox_out {
1028 struct mlx5_outbox_hdr hdr;
1029 u8 rsvd[8];
1030 __be32 data[0];
1031 };
1032
1033 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
1034
1035 enum {
1036 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
1037 };
1038
1039 struct mlx5_allocate_psv_in {
1040 struct mlx5_inbox_hdr hdr;
1041 __be32 npsv_pd;
1042 __be32 rsvd_psv0;
1043 };
1044
1045 struct mlx5_allocate_psv_out {
1046 struct mlx5_outbox_hdr hdr;
1047 u8 rsvd[8];
1048 __be32 psv_idx[4];
1049 };
1050
1051 struct mlx5_destroy_psv_in {
1052 struct mlx5_inbox_hdr hdr;
1053 __be32 psv_number;
1054 u8 rsvd[4];
1055 };
1056
1057 struct mlx5_destroy_psv_out {
1058 struct mlx5_outbox_hdr hdr;
1059 u8 rsvd[8];
1060 };
1061
1062 #define MLX5_CMD_OP_MAX 0x920
1063
1064 enum {
1065 VPORT_STATE_DOWN = 0x0,
1066 VPORT_STATE_UP = 0x1,
1067 };
1068
1069 enum {
1070 MLX5_L3_PROT_TYPE_IPV4 = 0,
1071 MLX5_L3_PROT_TYPE_IPV6 = 1,
1072 };
1073
1074 enum {
1075 MLX5_L4_PROT_TYPE_TCP = 0,
1076 MLX5_L4_PROT_TYPE_UDP = 1,
1077 };
1078
1079 enum {
1080 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
1081 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
1082 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
1083 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
1084 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
1085 };
1086
1087 enum {
1088 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
1089 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
1090 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1091
1092 };
1093
1094 enum {
1095 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
1096 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
1097 };
1098
1099 enum {
1100 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
1101 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
1102 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
1103 };
1104
1105 enum {
1106 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1107 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
1108 };
1109
1110 /* MLX5 DEV CAPs */
1111
1112 /* TODO: EAT.ME */
1113 enum mlx5_cap_mode {
1114 HCA_CAP_OPMOD_GET_MAX = 0,
1115 HCA_CAP_OPMOD_GET_CUR = 1,
1116 };
1117
1118 enum mlx5_cap_type {
1119 MLX5_CAP_GENERAL = 0,
1120 MLX5_CAP_ETHERNET_OFFLOADS,
1121 MLX5_CAP_ODP,
1122 MLX5_CAP_ATOMIC,
1123 MLX5_CAP_ROCE,
1124 MLX5_CAP_IPOIB_OFFLOADS,
1125 MLX5_CAP_EOIB_OFFLOADS,
1126 MLX5_CAP_FLOW_TABLE,
1127 /* NUM OF CAP Types */
1128 MLX5_CAP_NUM
1129 };
1130
1131 /* GET Dev Caps macros */
1132 #define MLX5_CAP_GEN(mdev, cap) \
1133 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1134
1135 #define MLX5_CAP_GEN_MAX(mdev, cap) \
1136 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
1137
1138 #define MLX5_CAP_ETH(mdev, cap) \
1139 MLX5_GET(per_protocol_networking_offload_caps,\
1140 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1141
1142 #define MLX5_CAP_ETH_MAX(mdev, cap) \
1143 MLX5_GET(per_protocol_networking_offload_caps,\
1144 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1145
1146 #define MLX5_CAP_ROCE(mdev, cap) \
1147 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1148
1149 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
1150 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1151
1152 #define MLX5_CAP_ATOMIC(mdev, cap) \
1153 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1154
1155 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1156 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1157
1158 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
1159 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1160
1161 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1162 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1163
1164 #define MLX5_CAP_ODP(mdev, cap)\
1165 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1166
1167 enum {
1168 MLX5_CMD_STAT_OK = 0x0,
1169 MLX5_CMD_STAT_INT_ERR = 0x1,
1170 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1171 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1172 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1173 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1174 MLX5_CMD_STAT_RES_BUSY = 0x6,
1175 MLX5_CMD_STAT_LIM_ERR = 0x8,
1176 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1177 MLX5_CMD_STAT_IX_ERR = 0xa,
1178 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1179 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1180 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1181 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1182 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1183 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1184 };
1185
1186 enum {
1187 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1188 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1189 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1190 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1191 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1192 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1193 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11
1194 };
1195
mlx5_to_sw_pkey_sz(int pkey_sz)1196 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1197 {
1198 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1199 return 0;
1200 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1201 }
1202
1203 #endif /* MLX5_DEVICE_H */
1204