Lines Matching +full:fifo +full:- +full:depth
12 /dts-v1/;
14 #include <dt-bindings/net/ti-dp83867.h>
15 #include <dt-bindings/reset/snps,hsdk-reset.h>
21 #address-cells = <1>;
22 #size-cells = <1>;
25 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
33 #address-cells = <1>;
34 #size-cells = <0>;
65 input_clk: input-clk {
66 #clock-cells = <0>;
67 compatible = "fixed-clock";
68 clock-frequency = <33333333>;
71 cpu_intc: cpu-interrupt-controller {
72 compatible = "snps,archs-intc";
73 interrupt-controller;
74 #interrupt-cells = <1>;
77 idu_intc: idu-interrupt-controller {
78 compatible = "snps,archs-idu-intc";
79 interrupt-controller;
80 #interrupt-cells = <1>;
81 interrupt-parent = <&cpu_intc>;
85 compatible = "snps,archs-pct";
86 interrupt-parent = <&cpu_intc>;
92 compatible = "snps,arc-timer";
94 interrupt-parent = <&cpu_intc>;
98 /* 64-bit Global Free Running Counter */
100 compatible = "snps,archs-timer-gfrc";
105 compatible = "simple-bus";
106 #address-cells = <1>;
107 #size-cells = <1>;
108 interrupt-parent = <&idu_intc>;
112 cgu_rst: reset-controller@8a0 {
113 compatible = "snps,hsdk-reset";
114 #reset-cells = <1>;
118 core_clk: core-clk@0 {
119 compatible = "snps,hsdk-core-pll-clock";
121 #clock-cells = <0>;
129 assigned-clocks = <&core_clk>;
130 assigned-clock-rates = <1000000000>;
134 compatible = "snps,dw-apb-uart";
136 clock-frequency = <33330000>;
139 reg-shift = <2>;
140 reg-io-width = <4>;
144 compatible = "fixed-clock";
145 clock-frequency = <400000000>;
146 #clock-cells = <0>;
149 mmcclk_ciu: mmcclk-ciu {
150 compatible = "fixed-clock";
158 * divisor (div-by-2) in HSDK platform code.
162 clock-frequency = <50000000>;
163 #clock-cells = <0>;
166 mmcclk_biu: mmcclk-biu {
167 compatible = "fixed-clock";
168 clock-frequency = <400000000>;
169 #clock-cells = <0>;
173 #interrupt-cells = <1>;
177 interrupt-names = "macirq";
178 phy-mode = "rgmii-id";
180 snps,multicast-filter-bins = <256>;
182 clock-names = "stmmaceth";
183 phy-handle = <&phy0>;
185 reset-names = "stmmaceth";
186 mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
187 dma-coherent;
189 tx-fifo-depth = <4096>;
190 rx-fifo-depth = <4096>;
193 #address-cells = <1>;
194 #size-cells = <0>;
195 compatible = "snps,dwmac-mdio";
196 phy0: ethernet-phy@0 { /* Micrel KSZ9031 */
198 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
199 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
200 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
206 compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
209 dma-coherent;
213 compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
216 dma-coherent;
220 compatible = "altr,socfpga-dw-mshc";
222 num-slots = <1>;
223 fifo-depth = <16>;
224 card-detect-delay = <200>;
226 clock-names = "biu", "ciu";
228 bus-width = <4>;
229 dma-coherent;
234 #address-cells = <1>;
235 #size-cells = <1>;