1/* 2 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9/* 10 * Device Tree for ARC HS Development Kit 11 */ 12/dts-v1/; 13 14#include <dt-bindings/net/ti-dp83867.h> 15#include <dt-bindings/reset/snps,hsdk-reset.h> 16 17/ { 18 model = "snps,hsdk"; 19 compatible = "snps,hsdk"; 20 21 #address-cells = <1>; 22 #size-cells = <1>; 23 24 chosen { 25 bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; 26 }; 27 28 aliases { 29 ethernet = &gmac; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 cpu@0 { 37 device_type = "cpu"; 38 compatible = "snps,archs38"; 39 reg = <0>; 40 clocks = <&core_clk>; 41 }; 42 43 cpu@1 { 44 device_type = "cpu"; 45 compatible = "snps,archs38"; 46 reg = <1>; 47 clocks = <&core_clk>; 48 }; 49 50 cpu@2 { 51 device_type = "cpu"; 52 compatible = "snps,archs38"; 53 reg = <2>; 54 clocks = <&core_clk>; 55 }; 56 57 cpu@3 { 58 device_type = "cpu"; 59 compatible = "snps,archs38"; 60 reg = <3>; 61 clocks = <&core_clk>; 62 }; 63 }; 64 65 input_clk: input-clk { 66 #clock-cells = <0>; 67 compatible = "fixed-clock"; 68 clock-frequency = <33333333>; 69 }; 70 71 cpu_intc: cpu-interrupt-controller { 72 compatible = "snps,archs-intc"; 73 interrupt-controller; 74 #interrupt-cells = <1>; 75 }; 76 77 idu_intc: idu-interrupt-controller { 78 compatible = "snps,archs-idu-intc"; 79 interrupt-controller; 80 #interrupt-cells = <1>; 81 interrupt-parent = <&cpu_intc>; 82 }; 83 84 arcpct: pct { 85 compatible = "snps,archs-pct"; 86 interrupt-parent = <&cpu_intc>; 87 interrupts = <20>; 88 }; 89 90 /* TIMER0 with interrupt for clockevent */ 91 timer { 92 compatible = "snps,arc-timer"; 93 interrupts = <16>; 94 interrupt-parent = <&cpu_intc>; 95 clocks = <&core_clk>; 96 }; 97 98 /* 64-bit Global Free Running Counter */ 99 gfrc { 100 compatible = "snps,archs-timer-gfrc"; 101 clocks = <&core_clk>; 102 }; 103 104 soc { 105 compatible = "simple-bus"; 106 #address-cells = <1>; 107 #size-cells = <1>; 108 interrupt-parent = <&idu_intc>; 109 110 ranges = <0x00000000 0xf0000000 0x10000000>; 111 112 cgu_rst: reset-controller@8a0 { 113 compatible = "snps,hsdk-reset"; 114 #reset-cells = <1>; 115 reg = <0x8A0 0x4>, <0xFF0 0x4>; 116 }; 117 118 core_clk: core-clk@0 { 119 compatible = "snps,hsdk-core-pll-clock"; 120 reg = <0x00 0x10>, <0x14B8 0x4>; 121 #clock-cells = <0>; 122 clocks = <&input_clk>; 123 124 /* 125 * Set initial core pll output frequency to 1GHz. 126 * It will be applied at the core pll driver probing 127 * on early boot. 128 */ 129 assigned-clocks = <&core_clk>; 130 assigned-clock-rates = <1000000000>; 131 }; 132 133 serial: serial@5000 { 134 compatible = "snps,dw-apb-uart"; 135 reg = <0x5000 0x100>; 136 clock-frequency = <33330000>; 137 interrupts = <6>; 138 baud = <115200>; 139 reg-shift = <2>; 140 reg-io-width = <4>; 141 }; 142 143 gmacclk: gmacclk { 144 compatible = "fixed-clock"; 145 clock-frequency = <400000000>; 146 #clock-cells = <0>; 147 }; 148 149 mmcclk_ciu: mmcclk-ciu { 150 compatible = "fixed-clock"; 151 /* 152 * DW sdio controller has external ciu clock divider 153 * controlled via register in SDIO IP. Due to its 154 * unexpected default value (it should divide by 1 155 * but it divides by 8) SDIO IP uses wrong clock and 156 * works unstable (see STAR 9001204800) 157 * We switched to the minimum possible value of the 158 * divisor (div-by-2) in HSDK platform code. 159 * So add temporary fix and change clock frequency 160 * to 50000000 Hz until we fix dw sdio driver itself. 161 */ 162 clock-frequency = <50000000>; 163 #clock-cells = <0>; 164 }; 165 166 mmcclk_biu: mmcclk-biu { 167 compatible = "fixed-clock"; 168 clock-frequency = <400000000>; 169 #clock-cells = <0>; 170 }; 171 172 gmac: ethernet@8000 { 173 #interrupt-cells = <1>; 174 compatible = "snps,dwmac"; 175 reg = <0x8000 0x2000>; 176 interrupts = <10>; 177 interrupt-names = "macirq"; 178 phy-mode = "rgmii-id"; 179 snps,pbl = <32>; 180 snps,multicast-filter-bins = <256>; 181 clocks = <&gmacclk>; 182 clock-names = "stmmaceth"; 183 phy-handle = <&phy0>; 184 resets = <&cgu_rst HSDK_ETH_RESET>; 185 reset-names = "stmmaceth"; 186 mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */ 187 dma-coherent; 188 189 tx-fifo-depth = <4096>; 190 rx-fifo-depth = <4096>; 191 192 mdio { 193 #address-cells = <1>; 194 #size-cells = <0>; 195 compatible = "snps,dwmac-mdio"; 196 phy0: ethernet-phy@0 { /* Micrel KSZ9031 */ 197 reg = <0>; 198 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 199 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 200 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 201 }; 202 }; 203 }; 204 205 ohci@60000 { 206 compatible = "snps,hsdk-v1.0-ohci", "generic-ohci"; 207 reg = <0x60000 0x100>; 208 interrupts = <15>; 209 dma-coherent; 210 }; 211 212 ehci@40000 { 213 compatible = "snps,hsdk-v1.0-ehci", "generic-ehci"; 214 reg = <0x40000 0x100>; 215 interrupts = <15>; 216 dma-coherent; 217 }; 218 219 mmc@a000 { 220 compatible = "altr,socfpga-dw-mshc"; 221 reg = <0xa000 0x400>; 222 num-slots = <1>; 223 fifo-depth = <16>; 224 card-detect-delay = <200>; 225 clocks = <&mmcclk_biu>, <&mmcclk_ciu>; 226 clock-names = "biu", "ciu"; 227 interrupts = <12>; 228 bus-width = <4>; 229 dma-coherent; 230 }; 231 }; 232 233 memory@80000000 { 234 #address-cells = <1>; 235 #size-cells = <1>; 236 device_type = "memory"; 237 reg = <0x80000000 0x40000000>; /* 1 GiB */ 238 }; 239}; 240