Lines Matching +full:uniphier +full:- +full:system +full:- +full:cache
1 # SPDX-License-Identifier: GPL-2.0
115 The ARM series is a line of low-power-consumption RISC chip designs
117 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
118 manufactured, but legacy ARM-based PC hardware remains popular in
170 ---help---
179 Say Y here if you are building a kernel for an EISA-based machine.
251 Patch phys-to-virt and virt-to-phys translation functions at
253 kernel in system memory.
255 This can only be used with non-XIP MMU kernels where the base
291 location of main memory in your system.
302 menu "System Type"
305 bool "MMU-based Paged Memory Management Support"
308 Select if you want MMU-based virtualised addressing space
320 # The "ARM system type" choice list is ordered alphabetically by option
324 prompt "ARM system type"
344 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
357 bool "EBSA-110"
366 from Digital. It has limited hardware on-board, including an
371 bool "EP93xx-based"
407 bool "IOP13xx-based"
420 bool "IOP32x-based"
433 bool "IOP33x-based"
445 bool "IXP4xx-based"
486 System-on-Chip devices.
520 bool "PXA2xx/PXA3xx-based"
558 On the Acorn Risc-PC, Linux can support the internal IDE disk and
559 CD-ROM interface, serial and parallel port, and the floppy drive.
562 bool "SA1100-based"
681 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
709 # This is sorted alphabetically by mach-* pathname. However, plat-*
711 # plat- suffix) or along side the corresponding mach-* source.
713 source "arch/arm/mach-actions/Kconfig"
715 source "arch/arm/mach-alpine/Kconfig"
717 source "arch/arm/mach-artpec/Kconfig"
719 source "arch/arm/mach-asm9260/Kconfig"
721 source "arch/arm/mach-aspeed/Kconfig"
723 source "arch/arm/mach-at91/Kconfig"
725 source "arch/arm/mach-axxia/Kconfig"
727 source "arch/arm/mach-bcm/Kconfig"
729 source "arch/arm/mach-berlin/Kconfig"
731 source "arch/arm/mach-clps711x/Kconfig"
733 source "arch/arm/mach-cns3xxx/Kconfig"
735 source "arch/arm/mach-davinci/Kconfig"
737 source "arch/arm/mach-digicolor/Kconfig"
739 source "arch/arm/mach-dove/Kconfig"
741 source "arch/arm/mach-ep93xx/Kconfig"
743 source "arch/arm/mach-exynos/Kconfig"
744 source "arch/arm/plat-samsung/Kconfig"
746 source "arch/arm/mach-footbridge/Kconfig"
748 source "arch/arm/mach-gemini/Kconfig"
750 source "arch/arm/mach-highbank/Kconfig"
752 source "arch/arm/mach-hisi/Kconfig"
754 source "arch/arm/mach-imx/Kconfig"
756 source "arch/arm/mach-integrator/Kconfig"
758 source "arch/arm/mach-iop13xx/Kconfig"
760 source "arch/arm/mach-iop32x/Kconfig"
762 source "arch/arm/mach-iop33x/Kconfig"
764 source "arch/arm/mach-ixp4xx/Kconfig"
766 source "arch/arm/mach-keystone/Kconfig"
768 source "arch/arm/mach-ks8695/Kconfig"
770 source "arch/arm/mach-mediatek/Kconfig"
772 source "arch/arm/mach-meson/Kconfig"
774 source "arch/arm/mach-mmp/Kconfig"
776 source "arch/arm/mach-moxart/Kconfig"
778 source "arch/arm/mach-mv78xx0/Kconfig"
780 source "arch/arm/mach-mvebu/Kconfig"
782 source "arch/arm/mach-mxs/Kconfig"
784 source "arch/arm/mach-netx/Kconfig"
786 source "arch/arm/mach-nomadik/Kconfig"
788 source "arch/arm/mach-npcm/Kconfig"
790 source "arch/arm/mach-nspire/Kconfig"
792 source "arch/arm/plat-omap/Kconfig"
794 source "arch/arm/mach-omap1/Kconfig"
796 source "arch/arm/mach-omap2/Kconfig"
798 source "arch/arm/mach-orion5x/Kconfig"
800 source "arch/arm/mach-oxnas/Kconfig"
802 source "arch/arm/mach-picoxcell/Kconfig"
804 source "arch/arm/mach-prima2/Kconfig"
806 source "arch/arm/mach-pxa/Kconfig"
807 source "arch/arm/plat-pxa/Kconfig"
809 source "arch/arm/mach-qcom/Kconfig"
811 source "arch/arm/mach-realview/Kconfig"
813 source "arch/arm/mach-rockchip/Kconfig"
815 source "arch/arm/mach-s3c24xx/Kconfig"
817 source "arch/arm/mach-s3c64xx/Kconfig"
819 source "arch/arm/mach-s5pv210/Kconfig"
821 source "arch/arm/mach-sa1100/Kconfig"
823 source "arch/arm/mach-shmobile/Kconfig"
825 source "arch/arm/mach-socfpga/Kconfig"
827 source "arch/arm/mach-spear/Kconfig"
829 source "arch/arm/mach-sti/Kconfig"
831 source "arch/arm/mach-stm32/Kconfig"
833 source "arch/arm/mach-sunxi/Kconfig"
835 source "arch/arm/mach-tango/Kconfig"
837 source "arch/arm/mach-tegra/Kconfig"
839 source "arch/arm/mach-u300/Kconfig"
841 source "arch/arm/mach-uniphier/Kconfig"
843 source "arch/arm/mach-ux500/Kconfig"
845 source "arch/arm/mach-versatile/Kconfig"
847 source "arch/arm/mach-vexpress/Kconfig"
848 source "arch/arm/plat-versatile/Kconfig"
850 source "arch/arm/mach-vt8500/Kconfig"
852 source "arch/arm/mach-w90x900/Kconfig"
854 source "arch/arm/mach-zx/Kconfig"
856 source "arch/arm/mach-zynq/Kconfig"
858 # ARMv7-M architecture
875 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
884 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
885 with a range of available cores like Cortex-M3/M4/M7.
928 source "arch/arm/Kconfig-nommu"
946 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
949 Executing a SWP instruction to read-only memory does not set bit 11
955 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
958 Invalidation of the Instruction Cache operation can
967 This option enables the workaround for the 430973 Cortex-A8
970 same virtual address, whether due to self-modifying code or virtual
971 to physical address re-mapping, Cortex-A8 does not recover from the
972 stale interworking branch prediction. This results in Cortex-A8
975 and also flushes the branch target cache at every context switch.
977 available in non-secure mode.
984 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
986 possible for a hazard condition intended for a cache line to instead
987 be incorrectly associated with a different cache line. This false
991 register may not be available in non-secure mode.
994 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
998 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
999 erratum. Any asynchronous access to the L2 cache may encounter a
1000 situation in which recent store transactions to the L2 cache are lost
1002 workaround disables the write-allocate mode for the L2 cache via the
1004 may not be available in non-secure mode.
1011 This option enables the workaround for the 742230 Cortex-A9
1015 the diagnostic register of the Cortex-A9 which causes the DMB
1024 This option enables the workaround for the 742231 Cortex-A9
1026 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1027 accessing some data located in the same cache line, may get corrupted
1031 register of the Cortex-A9 which reduces the linefill issuing
1039 This option enables the workaround for the 643719 Cortex-A9 (prior to
1042 corrects this value, ensuring cache maintenance operations which use
1049 This option enables the workaround for the 720789 Cortex-A9 (prior to
1053 invalidated are not, resulting in an incoherency in the system page
1062 This option enables the workaround for the 743622 Cortex-A9
1064 optimisation in the Cortex-A9 Store Buffer may lead to data
1066 register of the Cortex-A9 which disables the Store Buffer
1076 This option enables the workaround for the 751472 Cortex-A9 (prior
1080 potentially leading to corrupted entries in the cache or TLB.
1086 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1089 can populate the micro-TLB with a stale entry which may be hit with
1097 This option enables the workaround for the 754327 Cortex-A9 (prior to
1105 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1109 r0p2 erratum (possible cache data corruption with
1110 hit-under-miss enabled). It sets the undocumented bit 31 in
1112 register, thus disabling hit-under-miss without putting the
1117 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1121 affecting Cortex-A9 MPCore with two or more processors (all
1123 cache line maintenance operation by MVA targeting an Inner
1126 system. This workaround adds a DSB instruction before the
1127 relevant cache maintenance functions and sets a specific bit
1131 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1134 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1135 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1138 an abort may occur on cache maintenance.
1141 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1144 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1154 This option enables the workaround for the 773022 Cortex-A15
1164 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1166 - Cortex-A12 852422: Execution of a sequence of instructions might
1168 any Cortex-A12 cores yet.
1177 This option enables the workaround for the 821420 Cortex-A12
1181 deadlock when the VMOV instructions are issued out-of-order.
1187 This option enables the workaround for the 825619 Cortex-A12
1190 and Device/Strongly-Ordered loads and stores might cause deadlock
1196 This option enables the workaround for the 852421 Cortex-A17
1206 - Cortex-A17 852423: Execution of a sequence of instructions might
1208 any Cortex-A17 cores yet.
1209 This is identical to Cortex-A12 erratum 852422. It is a separate
1223 name of a bus system, i.e. the way the CPU talks to the other stuff
1225 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1241 bus system, i.e. the way the CPU talks to the other stuff inside
1284 This option should be selected by machines which have an SMP-
1287 The only effect of this option is to make the SMP-related
1291 bool "Symmetric Multi-Processing"
1299 a system with only one CPU, say N. If you have a system with more
1302 If you say N here, the kernel will run on uni- and multiprocessor
1308 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1309 <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at
1310 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1319 SMP kernels contain instructions which fail on non-SMP processors.
1333 topology of an ARM System.
1336 bool "Multi-core scheduler support"
1339 Multi-core scheduler support improves the CPU scheduler's decision
1340 making when dealing with multi-core CPU chips at a cost of slightly
1354 This option enables support for the ARM system coherency unit
1371 bool "Multi-Cluster Power Management"
1375 for (multi-)cluster based systems, such as big.LITTLE based
1393 system architecture.
1402 and a cluster of A7's in a big.LITTLE system.
1442 int "Maximum number of CPUs (2-32)"
1448 bool "Support for hot-pluggable CPUs"
1453 can be controlled through /sys/devices/system/cpu.
1460 Say Y here if you want Linux to communicate with system firmware
1461 implementing the PSCI specification for CPU-centric power
1463 0022A ("Power State Coordination Interface System Software on
1483 Maximum number of GPIOs in the system.
1531 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1537 Thumb-2 mode.
1542 bool "Work around buggy Thumb-2 short branch relocations in gas"
1546 Various binutils versions can resolve Thumb-2 branches to
1547 locally-defined, preemptible global symbols as short-range "b.n"
1561 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1566 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1568 Only Thumb-2 kernels are affected.
1618 The seccomp filter system will not be available when this is
1665 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1673 user-space 2nd level page tables to reside in high memory.
1676 bool "Enable use of CPU domains to implement privileged no-access"
1682 use-after-free bugs becoming an exploitable privilege escalation
1686 CPUs with low-vector mappings use a best-efforts implementation.
1719 Disabling this is usually safe for small single-platform
1746 address divisible by 4. On 32-bit ARM processors, these non-aligned
1749 correct operation of some network protocols. With an IP-only
1758 cores where a 8-word STM instruction give significantly higher
1765 However, if the CPU data cache is using a write-allocate mode,
1771 ---help---
1853 The physical address at which the ROM-able zImage is to be
1855 ROM-able zImage formats normally set this to a suitable
1865 for the ROM-able zImage which must be available while the
1868 Platforms which normally make use of ROM-able zImage formats
1920 Uses the command-line options passed by the boot loader instead of
1927 The command-line arguments provided by the boot loader will be
1938 architectures, you should supply some command-line options at build
1950 Uses the command-line options passed by the boot loader. If
1957 The command-line arguments provided by the boot loader will be
1966 command-line options your boot loader passes to the kernel.
1970 bool "Kernel Execute-In-Place from ROM"
1973 Execute-In-Place allows the kernel to run from non-volatile storage
1976 to RAM. Read-write sections, such as the data section and stack,
2011 bool "Kexec system call (EXPERIMENTAL)"
2016 kexec is a system call that implements the ability to shutdown your
2018 but it is independent of the system firmware. And like a reboot
2038 loaded in the main kernel with kexec-tools into a specially
2050 will be determined at run-time by masking the current IP with
2065 ---help---
2067 by UEFI firmware (such as non-volatile variables, realtime
2082 continue to boot on existing non-UEFI platforms.
2088 to be enabled much earlier than we do on ARM, which is non-trivial.
2107 ---help---
2111 your machine has an FPA or floating point co-processor podule.
2120 Say Y to include 80-bit support in the kernel floating-point
2121 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2122 Note that gcc does not generate 80-bit operations by default,
2131 ---help---
2135 It is very simple, and approximately 3-6 times faster than NWFPE.
2143 bool "VFP-format floating point maths"
2149 Please see <file:Documentation/arm/VFP/release-notes.txt> for