1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_CLOCKSOURCE_DATA 6 select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DEVMEM_IS_ALLOWED 9 select ARCH_HAS_ELF_RANDOMIZE 10 select ARCH_HAS_FORTIFY_SOURCE 11 select ARCH_HAS_KCOV 12 select ARCH_HAS_MEMBARRIER_SYNC_CORE 13 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 14 select ARCH_HAS_PHYS_TO_DMA 15 select ARCH_HAS_SET_MEMORY 16 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 17 select ARCH_HAS_STRICT_MODULE_RWX if MMU 18 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 19 select ARCH_HAVE_CUSTOM_GPIO_H 20 select ARCH_HAS_GCOV_PROFILE_ALL 21 select ARCH_MIGHT_HAVE_PC_PARPORT 22 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 23 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 24 select ARCH_SUPPORTS_ATOMIC_RMW 25 select ARCH_USE_BUILTIN_BSWAP 26 select ARCH_USE_CMPXCHG_LOCKREF 27 select ARCH_WANT_IPC_PARSE_VERSION 28 select BUILDTIME_EXTABLE_SORT if MMU 29 select CLONE_BACKWARDS 30 select CPU_PM if (SUSPEND || CPU_IDLE) 31 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 32 select DMA_DIRECT_OPS if !MMU 33 select EDAC_SUPPORT 34 select EDAC_ATOMIC_SCRUB 35 select GENERIC_ALLOCATOR 36 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 37 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) 38 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 39 select GENERIC_CPU_AUTOPROBE 40 select GENERIC_EARLY_IOREMAP 41 select GENERIC_IDLE_POLL_SETUP 42 select GENERIC_IRQ_PROBE 43 select GENERIC_IRQ_SHOW 44 select GENERIC_IRQ_SHOW_LEVEL 45 select GENERIC_PCI_IOMAP 46 select GENERIC_SCHED_CLOCK 47 select GENERIC_SMP_IDLE_THREAD 48 select GENERIC_STRNCPY_FROM_USER 49 select GENERIC_STRNLEN_USER 50 select HANDLE_DOMAIN_IRQ 51 select HARDIRQS_SW_RESEND 52 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) 53 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 54 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 55 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 56 select HAVE_ARCH_MMAP_RND_BITS if MMU 57 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) 58 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 59 select HAVE_ARCH_TRACEHOOK 60 select HAVE_ARM_SMCCC if CPU_V7 61 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 62 select HAVE_CONTEXT_TRACKING 63 select HAVE_C_RECORDMCOUNT 64 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 65 select HAVE_DMA_CONTIGUOUS if MMU 66 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU 67 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 68 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 69 select HAVE_EXIT_THREAD 70 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 71 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 72 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 73 select HAVE_GCC_PLUGINS 74 select HAVE_GENERIC_DMA_COHERENT 75 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 76 select HAVE_IDE if PCI || ISA || PCMCIA 77 select HAVE_IRQ_TIME_ACCOUNTING 78 select HAVE_KERNEL_GZIP 79 select HAVE_KERNEL_LZ4 80 select HAVE_KERNEL_LZMA 81 select HAVE_KERNEL_LZO 82 select HAVE_KERNEL_XZ 83 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 84 select HAVE_KRETPROBES if (HAVE_KPROBES) 85 select HAVE_MEMBLOCK 86 select HAVE_MOD_ARCH_SPECIFIC 87 select HAVE_NMI 88 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 89 select HAVE_OPTPROBES if !THUMB2_KERNEL 90 select HAVE_PERF_EVENTS 91 select HAVE_PERF_REGS 92 select HAVE_PERF_USER_STACK_DUMP 93 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE) 94 select HAVE_REGS_AND_STACK_ACCESS_API 95 select HAVE_RSEQ 96 select HAVE_STACKPROTECTOR 97 select HAVE_SYSCALL_TRACEPOINTS 98 select HAVE_UID16 99 select HAVE_VIRT_CPU_ACCOUNTING_GEN 100 select IRQ_FORCED_THREADING 101 select MODULES_USE_ELF_REL 102 select NEED_DMA_MAP_STATE 103 select NO_BOOTMEM 104 select OF_EARLY_FLATTREE if OF 105 select OF_RESERVED_MEM if OF 106 select OLD_SIGACTION 107 select OLD_SIGSUSPEND3 108 select PERF_USE_VMALLOC 109 select REFCOUNT_FULL 110 select RTC_LIB 111 select SYS_SUPPORTS_APM_EMULATION 112 # Above selects are sorted alphabetically; please add new ones 113 # according to that. Thanks. 114 help 115 The ARM series is a line of low-power-consumption RISC chip designs 116 licensed by ARM Ltd and targeted at embedded applications and 117 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 118 manufactured, but legacy ARM-based PC hardware remains popular in 119 Europe. There is an ARM Linux project with a web page at 120 <http://www.arm.linux.org.uk/>. 121 122config ARM_HAS_SG_CHAIN 123 select ARCH_HAS_SG_CHAIN 124 bool 125 126config ARM_DMA_USE_IOMMU 127 bool 128 select ARM_HAS_SG_CHAIN 129 select NEED_SG_DMA_LENGTH 130 131if ARM_DMA_USE_IOMMU 132 133config ARM_DMA_IOMMU_ALIGNMENT 134 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 135 range 4 9 136 default 8 137 help 138 DMA mapping framework by default aligns all buffers to the smallest 139 PAGE_SIZE order which is greater than or equal to the requested buffer 140 size. This works well for buffers up to a few hundreds kilobytes, but 141 for larger buffers it just a waste of address space. Drivers which has 142 relatively small addressing window (like 64Mib) might run out of 143 virtual space with just a few allocations. 144 145 With this parameter you can specify the maximum PAGE_SIZE order for 146 DMA IOMMU buffers. Larger buffers will be aligned only to this 147 specified order. The order is expressed as a power of two multiplied 148 by the PAGE_SIZE. 149 150endif 151 152config MIGHT_HAVE_PCI 153 bool 154 155config SYS_SUPPORTS_APM_EMULATION 156 bool 157 158config HAVE_TCM 159 bool 160 select GENERIC_ALLOCATOR 161 162config HAVE_PROC_CPU 163 bool 164 165config NO_IOPORT_MAP 166 bool 167 168config EISA 169 bool 170 ---help--- 171 The Extended Industry Standard Architecture (EISA) bus was 172 developed as an open alternative to the IBM MicroChannel bus. 173 174 The EISA bus provided some of the features of the IBM MicroChannel 175 bus while maintaining backward compatibility with cards made for 176 the older ISA bus. The EISA bus saw limited use between 1988 and 177 1995 when it was made obsolete by the PCI bus. 178 179 Say Y here if you are building a kernel for an EISA-based machine. 180 181 Otherwise, say N. 182 183config SBUS 184 bool 185 186config STACKTRACE_SUPPORT 187 bool 188 default y 189 190config LOCKDEP_SUPPORT 191 bool 192 default y 193 194config TRACE_IRQFLAGS_SUPPORT 195 bool 196 default !CPU_V7M 197 198config RWSEM_XCHGADD_ALGORITHM 199 bool 200 default y 201 202config ARCH_HAS_ILOG2_U32 203 bool 204 205config ARCH_HAS_ILOG2_U64 206 bool 207 208config ARCH_HAS_BANDGAP 209 bool 210 211config FIX_EARLYCON_MEM 212 def_bool y if MMU 213 214config GENERIC_HWEIGHT 215 bool 216 default y 217 218config GENERIC_CALIBRATE_DELAY 219 bool 220 default y 221 222config ARCH_MAY_HAVE_PC_FDC 223 bool 224 225config ZONE_DMA 226 bool 227 228config ARCH_SUPPORTS_UPROBES 229 def_bool y 230 231config ARCH_HAS_DMA_SET_COHERENT_MASK 232 bool 233 234config GENERIC_ISA_DMA 235 bool 236 237config FIQ 238 bool 239 240config NEED_RET_TO_USER 241 bool 242 243config ARCH_MTD_XIP 244 bool 245 246config ARM_PATCH_PHYS_VIRT 247 bool "Patch physical to virtual translations at runtime" if EMBEDDED 248 default y 249 depends on !XIP_KERNEL && MMU 250 help 251 Patch phys-to-virt and virt-to-phys translation functions at 252 boot and module load time according to the position of the 253 kernel in system memory. 254 255 This can only be used with non-XIP MMU kernels where the base 256 of physical memory is at a 16MB boundary. 257 258 Only disable this option if you know that you do not require 259 this feature (eg, building a kernel for a single machine) and 260 you need to shrink the kernel to the minimal size. 261 262config NEED_MACH_IO_H 263 bool 264 help 265 Select this when mach/io.h is required to provide special 266 definitions for this platform. The need for mach/io.h should 267 be avoided when possible. 268 269config NEED_MACH_MEMORY_H 270 bool 271 help 272 Select this when mach/memory.h is required to provide special 273 definitions for this platform. The need for mach/memory.h should 274 be avoided when possible. 275 276config PHYS_OFFSET 277 hex "Physical address of main memory" if MMU 278 depends on !ARM_PATCH_PHYS_VIRT 279 default DRAM_BASE if !MMU 280 default 0x00000000 if ARCH_EBSA110 || \ 281 ARCH_FOOTBRIDGE || \ 282 ARCH_INTEGRATOR || \ 283 ARCH_IOP13XX || \ 284 ARCH_KS8695 || \ 285 ARCH_REALVIEW 286 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 287 default 0x20000000 if ARCH_S5PV210 288 default 0xc0000000 if ARCH_SA1100 289 help 290 Please provide the physical address corresponding to the 291 location of main memory in your system. 292 293config GENERIC_BUG 294 def_bool y 295 depends on BUG 296 297config PGTABLE_LEVELS 298 int 299 default 3 if ARM_LPAE 300 default 2 301 302menu "System Type" 303 304config MMU 305 bool "MMU-based Paged Memory Management Support" 306 default y 307 help 308 Select if you want MMU-based virtualised addressing space 309 support by paged memory management. If unsure, say 'Y'. 310 311config ARCH_MMAP_RND_BITS_MIN 312 default 8 313 314config ARCH_MMAP_RND_BITS_MAX 315 default 14 if PAGE_OFFSET=0x40000000 316 default 15 if PAGE_OFFSET=0x80000000 317 default 16 318 319# 320# The "ARM system type" choice list is ordered alphabetically by option 321# text. Please add new entries in the option alphabetic order. 322# 323choice 324 prompt "ARM system type" 325 default ARM_SINGLE_ARMV7M if !MMU 326 default ARCH_MULTIPLATFORM if MMU 327 328config ARCH_MULTIPLATFORM 329 bool "Allow multiple platforms to be selected" 330 depends on MMU 331 select ARM_HAS_SG_CHAIN 332 select ARM_PATCH_PHYS_VIRT 333 select AUTO_ZRELADDR 334 select TIMER_OF 335 select COMMON_CLK 336 select GENERIC_CLOCKEVENTS 337 select GENERIC_IRQ_MULTI_HANDLER 338 select MIGHT_HAVE_PCI 339 select PCI_DOMAINS if PCI 340 select SPARSE_IRQ 341 select USE_OF 342 343config ARM_SINGLE_ARMV7M 344 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 345 depends on !MMU 346 select ARM_NVIC 347 select AUTO_ZRELADDR 348 select TIMER_OF 349 select COMMON_CLK 350 select CPU_V7M 351 select GENERIC_CLOCKEVENTS 352 select NO_IOPORT_MAP 353 select SPARSE_IRQ 354 select USE_OF 355 356config ARCH_EBSA110 357 bool "EBSA-110" 358 select ARCH_USES_GETTIMEOFFSET 359 select CPU_SA110 360 select ISA 361 select NEED_MACH_IO_H 362 select NEED_MACH_MEMORY_H 363 select NO_IOPORT_MAP 364 help 365 This is an evaluation board for the StrongARM processor available 366 from Digital. It has limited hardware on-board, including an 367 Ethernet interface, two PCMCIA sockets, two serial ports and a 368 parallel port. 369 370config ARCH_EP93XX 371 bool "EP93xx-based" 372 select ARCH_SPARSEMEM_ENABLE 373 select ARM_AMBA 374 imply ARM_PATCH_PHYS_VIRT 375 select ARM_VIC 376 select AUTO_ZRELADDR 377 select CLKDEV_LOOKUP 378 select CLKSRC_MMIO 379 select CPU_ARM920T 380 select GENERIC_CLOCKEVENTS 381 select GPIOLIB 382 help 383 This enables support for the Cirrus EP93xx series of CPUs. 384 385config ARCH_FOOTBRIDGE 386 bool "FootBridge" 387 select CPU_SA110 388 select FOOTBRIDGE 389 select GENERIC_CLOCKEVENTS 390 select HAVE_IDE 391 select NEED_MACH_IO_H if !MMU 392 select NEED_MACH_MEMORY_H 393 help 394 Support for systems based on the DC21285 companion chip 395 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 396 397config ARCH_NETX 398 bool "Hilscher NetX based" 399 select ARM_VIC 400 select CLKSRC_MMIO 401 select CPU_ARM926T 402 select GENERIC_CLOCKEVENTS 403 help 404 This enables support for systems based on the Hilscher NetX Soc 405 406config ARCH_IOP13XX 407 bool "IOP13xx-based" 408 depends on MMU 409 select CPU_XSC3 410 select NEED_MACH_MEMORY_H 411 select NEED_RET_TO_USER 412 select PCI 413 select PLAT_IOP 414 select VMSPLIT_1G 415 select SPARSE_IRQ 416 help 417 Support for Intel's IOP13XX (XScale) family of processors. 418 419config ARCH_IOP32X 420 bool "IOP32x-based" 421 depends on MMU 422 select CPU_XSCALE 423 select GPIO_IOP 424 select GPIOLIB 425 select NEED_RET_TO_USER 426 select PCI 427 select PLAT_IOP 428 help 429 Support for Intel's 80219 and IOP32X (XScale) family of 430 processors. 431 432config ARCH_IOP33X 433 bool "IOP33x-based" 434 depends on MMU 435 select CPU_XSCALE 436 select GPIO_IOP 437 select GPIOLIB 438 select NEED_RET_TO_USER 439 select PCI 440 select PLAT_IOP 441 help 442 Support for Intel's IOP33X (XScale) family of processors. 443 444config ARCH_IXP4XX 445 bool "IXP4xx-based" 446 depends on MMU 447 select ARCH_HAS_DMA_SET_COHERENT_MASK 448 select ARCH_SUPPORTS_BIG_ENDIAN 449 select CLKSRC_MMIO 450 select CPU_XSCALE 451 select DMABOUNCE if PCI 452 select GENERIC_CLOCKEVENTS 453 select GPIOLIB 454 select MIGHT_HAVE_PCI 455 select NEED_MACH_IO_H 456 select USB_EHCI_BIG_ENDIAN_DESC 457 select USB_EHCI_BIG_ENDIAN_MMIO 458 help 459 Support for Intel's IXP4XX (XScale) family of processors. 460 461config ARCH_DOVE 462 bool "Marvell Dove" 463 select CPU_PJ4 464 select GENERIC_CLOCKEVENTS 465 select GENERIC_IRQ_MULTI_HANDLER 466 select GPIOLIB 467 select MIGHT_HAVE_PCI 468 select MVEBU_MBUS 469 select PINCTRL 470 select PINCTRL_DOVE 471 select PLAT_ORION_LEGACY 472 select SPARSE_IRQ 473 select PM_GENERIC_DOMAINS if PM 474 help 475 Support for the Marvell Dove SoC 88AP510 476 477config ARCH_KS8695 478 bool "Micrel/Kendin KS8695" 479 select CLKSRC_MMIO 480 select CPU_ARM922T 481 select GENERIC_CLOCKEVENTS 482 select GPIOLIB 483 select NEED_MACH_MEMORY_H 484 help 485 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 486 System-on-Chip devices. 487 488config ARCH_W90X900 489 bool "Nuvoton W90X900 CPU" 490 select CLKDEV_LOOKUP 491 select CLKSRC_MMIO 492 select CPU_ARM926T 493 select GENERIC_CLOCKEVENTS 494 select GPIOLIB 495 help 496 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 497 At present, the w90x900 has been renamed nuc900, regarding 498 the ARM series product line, you can login the following 499 link address to know more. 500 501 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 502 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 503 504config ARCH_LPC32XX 505 bool "NXP LPC32XX" 506 select ARM_AMBA 507 select CLKDEV_LOOKUP 508 select CLKSRC_LPC32XX 509 select COMMON_CLK 510 select CPU_ARM926T 511 select GENERIC_CLOCKEVENTS 512 select GENERIC_IRQ_MULTI_HANDLER 513 select GPIOLIB 514 select SPARSE_IRQ 515 select USE_OF 516 help 517 Support for the NXP LPC32XX family of processors 518 519config ARCH_PXA 520 bool "PXA2xx/PXA3xx-based" 521 depends on MMU 522 select ARCH_MTD_XIP 523 select ARM_CPU_SUSPEND if PM 524 select AUTO_ZRELADDR 525 select COMMON_CLK 526 select CLKDEV_LOOKUP 527 select CLKSRC_PXA 528 select CLKSRC_MMIO 529 select TIMER_OF 530 select CPU_XSCALE if !CPU_XSC3 531 select GENERIC_CLOCKEVENTS 532 select GENERIC_IRQ_MULTI_HANDLER 533 select GPIO_PXA 534 select GPIOLIB 535 select HAVE_IDE 536 select IRQ_DOMAIN 537 select PLAT_PXA 538 select SPARSE_IRQ 539 help 540 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 541 542config ARCH_RPC 543 bool "RiscPC" 544 depends on MMU 545 select ARCH_ACORN 546 select ARCH_MAY_HAVE_PC_FDC 547 select ARCH_SPARSEMEM_ENABLE 548 select ARCH_USES_GETTIMEOFFSET 549 select CPU_SA110 550 select FIQ 551 select HAVE_IDE 552 select HAVE_PATA_PLATFORM 553 select ISA_DMA_API 554 select NEED_MACH_IO_H 555 select NEED_MACH_MEMORY_H 556 select NO_IOPORT_MAP 557 help 558 On the Acorn Risc-PC, Linux can support the internal IDE disk and 559 CD-ROM interface, serial and parallel port, and the floppy drive. 560 561config ARCH_SA1100 562 bool "SA1100-based" 563 select ARCH_MTD_XIP 564 select ARCH_SPARSEMEM_ENABLE 565 select CLKDEV_LOOKUP 566 select CLKSRC_MMIO 567 select CLKSRC_PXA 568 select TIMER_OF if OF 569 select CPU_FREQ 570 select CPU_SA1100 571 select GENERIC_CLOCKEVENTS 572 select GENERIC_IRQ_MULTI_HANDLER 573 select GPIOLIB 574 select HAVE_IDE 575 select IRQ_DOMAIN 576 select ISA 577 select NEED_MACH_MEMORY_H 578 select SPARSE_IRQ 579 help 580 Support for StrongARM 11x0 based boards. 581 582config ARCH_S3C24XX 583 bool "Samsung S3C24XX SoCs" 584 select ATAGS 585 select CLKDEV_LOOKUP 586 select CLKSRC_SAMSUNG_PWM 587 select GENERIC_CLOCKEVENTS 588 select GPIO_SAMSUNG 589 select GPIOLIB 590 select GENERIC_IRQ_MULTI_HANDLER 591 select HAVE_S3C2410_I2C if I2C 592 select HAVE_S3C2410_WATCHDOG if WATCHDOG 593 select HAVE_S3C_RTC if RTC_CLASS 594 select NEED_MACH_IO_H 595 select S3C2410_WATCHDOG 596 select SAMSUNG_ATAGS 597 select USE_OF 598 select WATCHDOG 599 help 600 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 601 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 602 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 603 Samsung SMDK2410 development board (and derivatives). 604 605config ARCH_DAVINCI 606 bool "TI DaVinci" 607 select ARCH_HAS_HOLES_MEMORYMODEL 608 select COMMON_CLK 609 select CPU_ARM926T 610 select GENERIC_ALLOCATOR 611 select GENERIC_CLOCKEVENTS 612 select GENERIC_IRQ_CHIP 613 select GPIOLIB 614 select HAVE_IDE 615 select PM_GENERIC_DOMAINS if PM 616 select PM_GENERIC_DOMAINS_OF if PM && OF 617 select REGMAP_MMIO 618 select RESET_CONTROLLER 619 select USE_OF 620 select ZONE_DMA 621 help 622 Support for TI's DaVinci platform. 623 624config ARCH_OMAP1 625 bool "TI OMAP1" 626 depends on MMU 627 select ARCH_HAS_HOLES_MEMORYMODEL 628 select ARCH_OMAP 629 select CLKDEV_LOOKUP 630 select CLKSRC_MMIO 631 select GENERIC_CLOCKEVENTS 632 select GENERIC_IRQ_CHIP 633 select GENERIC_IRQ_MULTI_HANDLER 634 select GPIOLIB 635 select HAVE_IDE 636 select IRQ_DOMAIN 637 select NEED_MACH_IO_H if PCCARD 638 select NEED_MACH_MEMORY_H 639 select SPARSE_IRQ 640 help 641 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 642 643endchoice 644 645menu "Multiple platform selection" 646 depends on ARCH_MULTIPLATFORM 647 648comment "CPU Core family selection" 649 650config ARCH_MULTI_V4 651 bool "ARMv4 based platforms (FA526)" 652 depends on !ARCH_MULTI_V6_V7 653 select ARCH_MULTI_V4_V5 654 select CPU_FA526 655 656config ARCH_MULTI_V4T 657 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 658 depends on !ARCH_MULTI_V6_V7 659 select ARCH_MULTI_V4_V5 660 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 661 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 662 CPU_ARM925T || CPU_ARM940T) 663 664config ARCH_MULTI_V5 665 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 666 depends on !ARCH_MULTI_V6_V7 667 select ARCH_MULTI_V4_V5 668 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 669 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 670 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 671 672config ARCH_MULTI_V4_V5 673 bool 674 675config ARCH_MULTI_V6 676 bool "ARMv6 based platforms (ARM11)" 677 select ARCH_MULTI_V6_V7 678 select CPU_V6K 679 680config ARCH_MULTI_V7 681 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 682 default y 683 select ARCH_MULTI_V6_V7 684 select CPU_V7 685 select HAVE_SMP 686 687config ARCH_MULTI_V6_V7 688 bool 689 select MIGHT_HAVE_CACHE_L2X0 690 691config ARCH_MULTI_CPU_AUTO 692 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 693 select ARCH_MULTI_V5 694 695endmenu 696 697config ARCH_VIRT 698 bool "Dummy Virtual Machine" 699 depends on ARCH_MULTI_V7 700 select ARM_AMBA 701 select ARM_GIC 702 select ARM_GIC_V2M if PCI 703 select ARM_GIC_V3 704 select ARM_GIC_V3_ITS if PCI 705 select ARM_PSCI 706 select HAVE_ARM_ARCH_TIMER 707 708# 709# This is sorted alphabetically by mach-* pathname. However, plat-* 710# Kconfigs may be included either alphabetically (according to the 711# plat- suffix) or along side the corresponding mach-* source. 712# 713source "arch/arm/mach-actions/Kconfig" 714 715source "arch/arm/mach-alpine/Kconfig" 716 717source "arch/arm/mach-artpec/Kconfig" 718 719source "arch/arm/mach-asm9260/Kconfig" 720 721source "arch/arm/mach-aspeed/Kconfig" 722 723source "arch/arm/mach-at91/Kconfig" 724 725source "arch/arm/mach-axxia/Kconfig" 726 727source "arch/arm/mach-bcm/Kconfig" 728 729source "arch/arm/mach-berlin/Kconfig" 730 731source "arch/arm/mach-clps711x/Kconfig" 732 733source "arch/arm/mach-cns3xxx/Kconfig" 734 735source "arch/arm/mach-davinci/Kconfig" 736 737source "arch/arm/mach-digicolor/Kconfig" 738 739source "arch/arm/mach-dove/Kconfig" 740 741source "arch/arm/mach-ep93xx/Kconfig" 742 743source "arch/arm/mach-exynos/Kconfig" 744source "arch/arm/plat-samsung/Kconfig" 745 746source "arch/arm/mach-footbridge/Kconfig" 747 748source "arch/arm/mach-gemini/Kconfig" 749 750source "arch/arm/mach-highbank/Kconfig" 751 752source "arch/arm/mach-hisi/Kconfig" 753 754source "arch/arm/mach-imx/Kconfig" 755 756source "arch/arm/mach-integrator/Kconfig" 757 758source "arch/arm/mach-iop13xx/Kconfig" 759 760source "arch/arm/mach-iop32x/Kconfig" 761 762source "arch/arm/mach-iop33x/Kconfig" 763 764source "arch/arm/mach-ixp4xx/Kconfig" 765 766source "arch/arm/mach-keystone/Kconfig" 767 768source "arch/arm/mach-ks8695/Kconfig" 769 770source "arch/arm/mach-mediatek/Kconfig" 771 772source "arch/arm/mach-meson/Kconfig" 773 774source "arch/arm/mach-mmp/Kconfig" 775 776source "arch/arm/mach-moxart/Kconfig" 777 778source "arch/arm/mach-mv78xx0/Kconfig" 779 780source "arch/arm/mach-mvebu/Kconfig" 781 782source "arch/arm/mach-mxs/Kconfig" 783 784source "arch/arm/mach-netx/Kconfig" 785 786source "arch/arm/mach-nomadik/Kconfig" 787 788source "arch/arm/mach-npcm/Kconfig" 789 790source "arch/arm/mach-nspire/Kconfig" 791 792source "arch/arm/plat-omap/Kconfig" 793 794source "arch/arm/mach-omap1/Kconfig" 795 796source "arch/arm/mach-omap2/Kconfig" 797 798source "arch/arm/mach-orion5x/Kconfig" 799 800source "arch/arm/mach-oxnas/Kconfig" 801 802source "arch/arm/mach-picoxcell/Kconfig" 803 804source "arch/arm/mach-prima2/Kconfig" 805 806source "arch/arm/mach-pxa/Kconfig" 807source "arch/arm/plat-pxa/Kconfig" 808 809source "arch/arm/mach-qcom/Kconfig" 810 811source "arch/arm/mach-realview/Kconfig" 812 813source "arch/arm/mach-rockchip/Kconfig" 814 815source "arch/arm/mach-s3c24xx/Kconfig" 816 817source "arch/arm/mach-s3c64xx/Kconfig" 818 819source "arch/arm/mach-s5pv210/Kconfig" 820 821source "arch/arm/mach-sa1100/Kconfig" 822 823source "arch/arm/mach-shmobile/Kconfig" 824 825source "arch/arm/mach-socfpga/Kconfig" 826 827source "arch/arm/mach-spear/Kconfig" 828 829source "arch/arm/mach-sti/Kconfig" 830 831source "arch/arm/mach-stm32/Kconfig" 832 833source "arch/arm/mach-sunxi/Kconfig" 834 835source "arch/arm/mach-tango/Kconfig" 836 837source "arch/arm/mach-tegra/Kconfig" 838 839source "arch/arm/mach-u300/Kconfig" 840 841source "arch/arm/mach-uniphier/Kconfig" 842 843source "arch/arm/mach-ux500/Kconfig" 844 845source "arch/arm/mach-versatile/Kconfig" 846 847source "arch/arm/mach-vexpress/Kconfig" 848source "arch/arm/plat-versatile/Kconfig" 849 850source "arch/arm/mach-vt8500/Kconfig" 851 852source "arch/arm/mach-w90x900/Kconfig" 853 854source "arch/arm/mach-zx/Kconfig" 855 856source "arch/arm/mach-zynq/Kconfig" 857 858# ARMv7-M architecture 859config ARCH_EFM32 860 bool "Energy Micro efm32" 861 depends on ARM_SINGLE_ARMV7M 862 select GPIOLIB 863 help 864 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 865 processors. 866 867config ARCH_LPC18XX 868 bool "NXP LPC18xx/LPC43xx" 869 depends on ARM_SINGLE_ARMV7M 870 select ARCH_HAS_RESET_CONTROLLER 871 select ARM_AMBA 872 select CLKSRC_LPC32XX 873 select PINCTRL 874 help 875 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 876 high performance microcontrollers. 877 878config ARCH_MPS2 879 bool "ARM MPS2 platform" 880 depends on ARM_SINGLE_ARMV7M 881 select ARM_AMBA 882 select CLKSRC_MPS2 883 help 884 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 885 with a range of available cores like Cortex-M3/M4/M7. 886 887 Please, note that depends which Application Note is used memory map 888 for the platform may vary, so adjustment of RAM base might be needed. 889 890# Definitions to make life easier 891config ARCH_ACORN 892 bool 893 894config PLAT_IOP 895 bool 896 select GENERIC_CLOCKEVENTS 897 898config PLAT_ORION 899 bool 900 select CLKSRC_MMIO 901 select COMMON_CLK 902 select GENERIC_IRQ_CHIP 903 select IRQ_DOMAIN 904 905config PLAT_ORION_LEGACY 906 bool 907 select PLAT_ORION 908 909config PLAT_PXA 910 bool 911 912config PLAT_VERSATILE 913 bool 914 915source "arch/arm/firmware/Kconfig" 916 917source arch/arm/mm/Kconfig 918 919config IWMMXT 920 bool "Enable iWMMXt support" 921 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 922 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 923 help 924 Enable support for iWMMXt context switching at run time if 925 running on a CPU that supports it. 926 927if !MMU 928source "arch/arm/Kconfig-nommu" 929endif 930 931config PJ4B_ERRATA_4742 932 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 933 depends on CPU_PJ4B && MACH_ARMADA_370 934 default y 935 help 936 When coming out of either a Wait for Interrupt (WFI) or a Wait for 937 Event (WFE) IDLE states, a specific timing sensitivity exists between 938 the retiring WFI/WFE instructions and the newly issued subsequent 939 instructions. This sensitivity can result in a CPU hang scenario. 940 Workaround: 941 The software must insert either a Data Synchronization Barrier (DSB) 942 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 943 instruction 944 945config ARM_ERRATA_326103 946 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 947 depends on CPU_V6 948 help 949 Executing a SWP instruction to read-only memory does not set bit 11 950 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 951 treat the access as a read, preventing a COW from occurring and 952 causing the faulting task to livelock. 953 954config ARM_ERRATA_411920 955 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 956 depends on CPU_V6 || CPU_V6K 957 help 958 Invalidation of the Instruction Cache operation can 959 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 960 It does not affect the MPCore. This option enables the ARM Ltd. 961 recommended workaround. 962 963config ARM_ERRATA_430973 964 bool "ARM errata: Stale prediction on replaced interworking branch" 965 depends on CPU_V7 966 help 967 This option enables the workaround for the 430973 Cortex-A8 968 r1p* erratum. If a code sequence containing an ARM/Thumb 969 interworking branch is replaced with another code sequence at the 970 same virtual address, whether due to self-modifying code or virtual 971 to physical address re-mapping, Cortex-A8 does not recover from the 972 stale interworking branch prediction. This results in Cortex-A8 973 executing the new code sequence in the incorrect ARM or Thumb state. 974 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 975 and also flushes the branch target cache at every context switch. 976 Note that setting specific bits in the ACTLR register may not be 977 available in non-secure mode. 978 979config ARM_ERRATA_458693 980 bool "ARM errata: Processor deadlock when a false hazard is created" 981 depends on CPU_V7 982 depends on !ARCH_MULTIPLATFORM 983 help 984 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 985 erratum. For very specific sequences of memory operations, it is 986 possible for a hazard condition intended for a cache line to instead 987 be incorrectly associated with a different cache line. This false 988 hazard might then cause a processor deadlock. The workaround enables 989 the L1 caching of the NEON accesses and disables the PLD instruction 990 in the ACTLR register. Note that setting specific bits in the ACTLR 991 register may not be available in non-secure mode. 992 993config ARM_ERRATA_460075 994 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 995 depends on CPU_V7 996 depends on !ARCH_MULTIPLATFORM 997 help 998 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 999 erratum. Any asynchronous access to the L2 cache may encounter a 1000 situation in which recent store transactions to the L2 cache are lost 1001 and overwritten with stale memory contents from external memory. The 1002 workaround disables the write-allocate mode for the L2 cache via the 1003 ACTLR register. Note that setting specific bits in the ACTLR register 1004 may not be available in non-secure mode. 1005 1006config ARM_ERRATA_742230 1007 bool "ARM errata: DMB operation may be faulty" 1008 depends on CPU_V7 && SMP 1009 depends on !ARCH_MULTIPLATFORM 1010 help 1011 This option enables the workaround for the 742230 Cortex-A9 1012 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1013 between two write operations may not ensure the correct visibility 1014 ordering of the two writes. This workaround sets a specific bit in 1015 the diagnostic register of the Cortex-A9 which causes the DMB 1016 instruction to behave as a DSB, ensuring the correct behaviour of 1017 the two writes. 1018 1019config ARM_ERRATA_742231 1020 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1021 depends on CPU_V7 && SMP 1022 depends on !ARCH_MULTIPLATFORM 1023 help 1024 This option enables the workaround for the 742231 Cortex-A9 1025 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1026 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1027 accessing some data located in the same cache line, may get corrupted 1028 data due to bad handling of the address hazard when the line gets 1029 replaced from one of the CPUs at the same time as another CPU is 1030 accessing it. This workaround sets specific bits in the diagnostic 1031 register of the Cortex-A9 which reduces the linefill issuing 1032 capabilities of the processor. 1033 1034config ARM_ERRATA_643719 1035 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1036 depends on CPU_V7 && SMP 1037 default y 1038 help 1039 This option enables the workaround for the 643719 Cortex-A9 (prior to 1040 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1041 register returns zero when it should return one. The workaround 1042 corrects this value, ensuring cache maintenance operations which use 1043 it behave as intended and avoiding data corruption. 1044 1045config ARM_ERRATA_720789 1046 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1047 depends on CPU_V7 1048 help 1049 This option enables the workaround for the 720789 Cortex-A9 (prior to 1050 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1051 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1052 As a consequence of this erratum, some TLB entries which should be 1053 invalidated are not, resulting in an incoherency in the system page 1054 tables. The workaround changes the TLB flushing routines to invalidate 1055 entries regardless of the ASID. 1056 1057config ARM_ERRATA_743622 1058 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1059 depends on CPU_V7 1060 depends on !ARCH_MULTIPLATFORM 1061 help 1062 This option enables the workaround for the 743622 Cortex-A9 1063 (r2p*) erratum. Under very rare conditions, a faulty 1064 optimisation in the Cortex-A9 Store Buffer may lead to data 1065 corruption. This workaround sets a specific bit in the diagnostic 1066 register of the Cortex-A9 which disables the Store Buffer 1067 optimisation, preventing the defect from occurring. This has no 1068 visible impact on the overall performance or power consumption of the 1069 processor. 1070 1071config ARM_ERRATA_751472 1072 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1073 depends on CPU_V7 1074 depends on !ARCH_MULTIPLATFORM 1075 help 1076 This option enables the workaround for the 751472 Cortex-A9 (prior 1077 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1078 completion of a following broadcasted operation if the second 1079 operation is received by a CPU before the ICIALLUIS has completed, 1080 potentially leading to corrupted entries in the cache or TLB. 1081 1082config ARM_ERRATA_754322 1083 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1084 depends on CPU_V7 1085 help 1086 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1087 r3p*) erratum. A speculative memory access may cause a page table walk 1088 which starts prior to an ASID switch but completes afterwards. This 1089 can populate the micro-TLB with a stale entry which may be hit with 1090 the new ASID. This workaround places two dsb instructions in the mm 1091 switching code so that no page table walks can cross the ASID switch. 1092 1093config ARM_ERRATA_754327 1094 bool "ARM errata: no automatic Store Buffer drain" 1095 depends on CPU_V7 && SMP 1096 help 1097 This option enables the workaround for the 754327 Cortex-A9 (prior to 1098 r2p0) erratum. The Store Buffer does not have any automatic draining 1099 mechanism and therefore a livelock may occur if an external agent 1100 continuously polls a memory location waiting to observe an update. 1101 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1102 written polling loops from denying visibility of updates to memory. 1103 1104config ARM_ERRATA_364296 1105 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1106 depends on CPU_V6 1107 help 1108 This options enables the workaround for the 364296 ARM1136 1109 r0p2 erratum (possible cache data corruption with 1110 hit-under-miss enabled). It sets the undocumented bit 31 in 1111 the auxiliary control register and the FI bit in the control 1112 register, thus disabling hit-under-miss without putting the 1113 processor into full low interrupt latency mode. ARM11MPCore 1114 is not affected. 1115 1116config ARM_ERRATA_764369 1117 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1118 depends on CPU_V7 && SMP 1119 help 1120 This option enables the workaround for erratum 764369 1121 affecting Cortex-A9 MPCore with two or more processors (all 1122 current revisions). Under certain timing circumstances, a data 1123 cache line maintenance operation by MVA targeting an Inner 1124 Shareable memory region may fail to proceed up to either the 1125 Point of Coherency or to the Point of Unification of the 1126 system. This workaround adds a DSB instruction before the 1127 relevant cache maintenance functions and sets a specific bit 1128 in the diagnostic control register of the SCU. 1129 1130config ARM_ERRATA_775420 1131 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1132 depends on CPU_V7 1133 help 1134 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1135 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1136 operation aborts with MMU exception, it might cause the processor 1137 to deadlock. This workaround puts DSB before executing ISB if 1138 an abort may occur on cache maintenance. 1139 1140config ARM_ERRATA_798181 1141 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1142 depends on CPU_V7 && SMP 1143 help 1144 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1145 adequately shooting down all use of the old entries. This 1146 option enables the Linux kernel workaround for this erratum 1147 which sends an IPI to the CPUs that are running the same ASID 1148 as the one being invalidated. 1149 1150config ARM_ERRATA_773022 1151 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1152 depends on CPU_V7 1153 help 1154 This option enables the workaround for the 773022 Cortex-A15 1155 (up to r0p4) erratum. In certain rare sequences of code, the 1156 loop buffer may deliver incorrect instructions. This 1157 workaround disables the loop buffer to avoid the erratum. 1158 1159config ARM_ERRATA_818325_852422 1160 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1161 depends on CPU_V7 1162 help 1163 This option enables the workaround for: 1164 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1165 instruction might deadlock. Fixed in r0p1. 1166 - Cortex-A12 852422: Execution of a sequence of instructions might 1167 lead to either a data corruption or a CPU deadlock. Not fixed in 1168 any Cortex-A12 cores yet. 1169 This workaround for all both errata involves setting bit[12] of the 1170 Feature Register. This bit disables an optimisation applied to a 1171 sequence of 2 instructions that use opposing condition codes. 1172 1173config ARM_ERRATA_821420 1174 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1175 depends on CPU_V7 1176 help 1177 This option enables the workaround for the 821420 Cortex-A12 1178 (all revs) erratum. In very rare timing conditions, a sequence 1179 of VMOV to Core registers instructions, for which the second 1180 one is in the shadow of a branch or abort, can lead to a 1181 deadlock when the VMOV instructions are issued out-of-order. 1182 1183config ARM_ERRATA_825619 1184 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1185 depends on CPU_V7 1186 help 1187 This option enables the workaround for the 825619 Cortex-A12 1188 (all revs) erratum. Within rare timing constraints, executing a 1189 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1190 and Device/Strongly-Ordered loads and stores might cause deadlock 1191 1192config ARM_ERRATA_852421 1193 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1194 depends on CPU_V7 1195 help 1196 This option enables the workaround for the 852421 Cortex-A17 1197 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1198 execution of a DMB ST instruction might fail to properly order 1199 stores from GroupA and stores from GroupB. 1200 1201config ARM_ERRATA_852423 1202 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1203 depends on CPU_V7 1204 help 1205 This option enables the workaround for: 1206 - Cortex-A17 852423: Execution of a sequence of instructions might 1207 lead to either a data corruption or a CPU deadlock. Not fixed in 1208 any Cortex-A17 cores yet. 1209 This is identical to Cortex-A12 erratum 852422. It is a separate 1210 config option from the A12 erratum due to the way errata are checked 1211 for and handled. 1212 1213endmenu 1214 1215source "arch/arm/common/Kconfig" 1216 1217menu "Bus support" 1218 1219config ISA 1220 bool 1221 help 1222 Find out whether you have ISA slots on your motherboard. ISA is the 1223 name of a bus system, i.e. the way the CPU talks to the other stuff 1224 inside your box. Other bus systems are PCI, EISA, MicroChannel 1225 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1226 newer boards don't support it. If you have ISA, say Y, otherwise N. 1227 1228# Select ISA DMA controller support 1229config ISA_DMA 1230 bool 1231 select ISA_DMA_API 1232 1233# Select ISA DMA interface 1234config ISA_DMA_API 1235 bool 1236 1237config PCI 1238 bool "PCI support" if MIGHT_HAVE_PCI 1239 help 1240 Find out whether you have a PCI motherboard. PCI is the name of a 1241 bus system, i.e. the way the CPU talks to the other stuff inside 1242 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1243 VESA. If you have PCI, say Y, otherwise N. 1244 1245config PCI_DOMAINS 1246 bool "Support for multiple PCI domains" 1247 depends on PCI 1248 help 1249 Enable PCI domains kernel management. Say Y if your machine 1250 has a PCI bus hierarchy that requires more than one PCI 1251 domain (aka segment) to be correctly managed. Say N otherwise. 1252 1253 If you don't know what to do here, say N. 1254 1255config PCI_DOMAINS_GENERIC 1256 def_bool PCI_DOMAINS 1257 1258config PCI_NANOENGINE 1259 bool "BSE nanoEngine PCI support" 1260 depends on SA1100_NANOENGINE 1261 help 1262 Enable PCI on the BSE nanoEngine board. 1263 1264config PCI_SYSCALL 1265 def_bool PCI 1266 1267config PCI_HOST_ITE8152 1268 bool 1269 depends on PCI && MACH_ARMCORE 1270 default y 1271 select DMABOUNCE 1272 1273source "drivers/pci/Kconfig" 1274 1275source "drivers/pcmcia/Kconfig" 1276 1277endmenu 1278 1279menu "Kernel Features" 1280 1281config HAVE_SMP 1282 bool 1283 help 1284 This option should be selected by machines which have an SMP- 1285 capable CPU. 1286 1287 The only effect of this option is to make the SMP-related 1288 options available to the user for configuration. 1289 1290config SMP 1291 bool "Symmetric Multi-Processing" 1292 depends on CPU_V6K || CPU_V7 1293 depends on GENERIC_CLOCKEVENTS 1294 depends on HAVE_SMP 1295 depends on MMU || ARM_MPU 1296 select IRQ_WORK 1297 help 1298 This enables support for systems with more than one CPU. If you have 1299 a system with only one CPU, say N. If you have a system with more 1300 than one CPU, say Y. 1301 1302 If you say N here, the kernel will run on uni- and multiprocessor 1303 machines, but will use only one CPU of a multiprocessor machine. If 1304 you say Y here, the kernel will run on many, but not all, 1305 uniprocessor machines. On a uniprocessor machine, the kernel 1306 will run faster if you say N here. 1307 1308 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1309 <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at 1310 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1311 1312 If you don't know what to do here, say N. 1313 1314config SMP_ON_UP 1315 bool "Allow booting SMP kernel on uniprocessor systems" 1316 depends on SMP && !XIP_KERNEL && MMU 1317 default y 1318 help 1319 SMP kernels contain instructions which fail on non-SMP processors. 1320 Enabling this option allows the kernel to modify itself to make 1321 these instructions safe. Disabling it allows about 1K of space 1322 savings. 1323 1324 If you don't know what to do here, say Y. 1325 1326config ARM_CPU_TOPOLOGY 1327 bool "Support cpu topology definition" 1328 depends on SMP && CPU_V7 1329 default y 1330 help 1331 Support ARM cpu topology definition. The MPIDR register defines 1332 affinity between processors which is then used to describe the cpu 1333 topology of an ARM System. 1334 1335config SCHED_MC 1336 bool "Multi-core scheduler support" 1337 depends on ARM_CPU_TOPOLOGY 1338 help 1339 Multi-core scheduler support improves the CPU scheduler's decision 1340 making when dealing with multi-core CPU chips at a cost of slightly 1341 increased overhead in some places. If unsure say N here. 1342 1343config SCHED_SMT 1344 bool "SMT scheduler support" 1345 depends on ARM_CPU_TOPOLOGY 1346 help 1347 Improves the CPU scheduler's decision making when dealing with 1348 MultiThreading at a cost of slightly increased overhead in some 1349 places. If unsure say N here. 1350 1351config HAVE_ARM_SCU 1352 bool 1353 help 1354 This option enables support for the ARM system coherency unit 1355 1356config HAVE_ARM_ARCH_TIMER 1357 bool "Architected timer support" 1358 depends on CPU_V7 1359 select ARM_ARCH_TIMER 1360 select GENERIC_CLOCKEVENTS 1361 help 1362 This option enables support for the ARM architected timer 1363 1364config HAVE_ARM_TWD 1365 bool 1366 select TIMER_OF if OF 1367 help 1368 This options enables support for the ARM timer and watchdog unit 1369 1370config MCPM 1371 bool "Multi-Cluster Power Management" 1372 depends on CPU_V7 && SMP 1373 help 1374 This option provides the common power management infrastructure 1375 for (multi-)cluster based systems, such as big.LITTLE based 1376 systems. 1377 1378config MCPM_QUAD_CLUSTER 1379 bool 1380 depends on MCPM 1381 help 1382 To avoid wasting resources unnecessarily, MCPM only supports up 1383 to 2 clusters by default. 1384 Platforms with 3 or 4 clusters that use MCPM must select this 1385 option to allow the additional clusters to be managed. 1386 1387config BIG_LITTLE 1388 bool "big.LITTLE support (Experimental)" 1389 depends on CPU_V7 && SMP 1390 select MCPM 1391 help 1392 This option enables support selections for the big.LITTLE 1393 system architecture. 1394 1395config BL_SWITCHER 1396 bool "big.LITTLE switcher support" 1397 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1398 select CPU_PM 1399 help 1400 The big.LITTLE "switcher" provides the core functionality to 1401 transparently handle transition between a cluster of A15's 1402 and a cluster of A7's in a big.LITTLE system. 1403 1404config BL_SWITCHER_DUMMY_IF 1405 tristate "Simple big.LITTLE switcher user interface" 1406 depends on BL_SWITCHER && DEBUG_KERNEL 1407 help 1408 This is a simple and dummy char dev interface to control 1409 the big.LITTLE switcher core code. It is meant for 1410 debugging purposes only. 1411 1412choice 1413 prompt "Memory split" 1414 depends on MMU 1415 default VMSPLIT_3G 1416 help 1417 Select the desired split between kernel and user memory. 1418 1419 If you are not absolutely sure what you are doing, leave this 1420 option alone! 1421 1422 config VMSPLIT_3G 1423 bool "3G/1G user/kernel split" 1424 config VMSPLIT_3G_OPT 1425 depends on !ARM_LPAE 1426 bool "3G/1G user/kernel split (for full 1G low memory)" 1427 config VMSPLIT_2G 1428 bool "2G/2G user/kernel split" 1429 config VMSPLIT_1G 1430 bool "1G/3G user/kernel split" 1431endchoice 1432 1433config PAGE_OFFSET 1434 hex 1435 default PHYS_OFFSET if !MMU 1436 default 0x40000000 if VMSPLIT_1G 1437 default 0x80000000 if VMSPLIT_2G 1438 default 0xB0000000 if VMSPLIT_3G_OPT 1439 default 0xC0000000 1440 1441config NR_CPUS 1442 int "Maximum number of CPUs (2-32)" 1443 range 2 32 1444 depends on SMP 1445 default "4" 1446 1447config HOTPLUG_CPU 1448 bool "Support for hot-pluggable CPUs" 1449 depends on SMP 1450 select GENERIC_IRQ_MIGRATION 1451 help 1452 Say Y here to experiment with turning CPUs off and on. CPUs 1453 can be controlled through /sys/devices/system/cpu. 1454 1455config ARM_PSCI 1456 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1457 depends on HAVE_ARM_SMCCC 1458 select ARM_PSCI_FW 1459 help 1460 Say Y here if you want Linux to communicate with system firmware 1461 implementing the PSCI specification for CPU-centric power 1462 management operations described in ARM document number ARM DEN 1463 0022A ("Power State Coordination Interface System Software on 1464 ARM processors"). 1465 1466# The GPIO number here must be sorted by descending number. In case of 1467# a multiplatform kernel, we just want the highest value required by the 1468# selected platforms. 1469config ARCH_NR_GPIO 1470 int 1471 default 2048 if ARCH_SOCFPGA 1472 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1473 ARCH_ZYNQ 1474 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1475 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1476 default 416 if ARCH_SUNXI 1477 default 392 if ARCH_U8500 1478 default 352 if ARCH_VT8500 1479 default 288 if ARCH_ROCKCHIP 1480 default 264 if MACH_H4700 1481 default 0 1482 help 1483 Maximum number of GPIOs in the system. 1484 1485 If unsure, leave the default value. 1486 1487config HZ_FIXED 1488 int 1489 default 200 if ARCH_EBSA110 1490 default 128 if SOC_AT91RM9200 1491 default 0 1492 1493choice 1494 depends on HZ_FIXED = 0 1495 prompt "Timer frequency" 1496 1497config HZ_100 1498 bool "100 Hz" 1499 1500config HZ_200 1501 bool "200 Hz" 1502 1503config HZ_250 1504 bool "250 Hz" 1505 1506config HZ_300 1507 bool "300 Hz" 1508 1509config HZ_500 1510 bool "500 Hz" 1511 1512config HZ_1000 1513 bool "1000 Hz" 1514 1515endchoice 1516 1517config HZ 1518 int 1519 default HZ_FIXED if HZ_FIXED != 0 1520 default 100 if HZ_100 1521 default 200 if HZ_200 1522 default 250 if HZ_250 1523 default 300 if HZ_300 1524 default 500 if HZ_500 1525 default 1000 1526 1527config SCHED_HRTICK 1528 def_bool HIGH_RES_TIMERS 1529 1530config THUMB2_KERNEL 1531 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1532 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1533 default y if CPU_THUMBONLY 1534 select ARM_UNWIND 1535 help 1536 By enabling this option, the kernel will be compiled in 1537 Thumb-2 mode. 1538 1539 If unsure, say N. 1540 1541config THUMB2_AVOID_R_ARM_THM_JUMP11 1542 bool "Work around buggy Thumb-2 short branch relocations in gas" 1543 depends on THUMB2_KERNEL && MODULES 1544 default y 1545 help 1546 Various binutils versions can resolve Thumb-2 branches to 1547 locally-defined, preemptible global symbols as short-range "b.n" 1548 branch instructions. 1549 1550 This is a problem, because there's no guarantee the final 1551 destination of the symbol, or any candidate locations for a 1552 trampoline, are within range of the branch. For this reason, the 1553 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1554 relocation in modules at all, and it makes little sense to add 1555 support. 1556 1557 The symptom is that the kernel fails with an "unsupported 1558 relocation" error when loading some modules. 1559 1560 Until fixed tools are available, passing 1561 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1562 code which hits this problem, at the cost of a bit of extra runtime 1563 stack usage in some cases. 1564 1565 The problem is described in more detail at: 1566 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1567 1568 Only Thumb-2 kernels are affected. 1569 1570 Unless you are sure your tools don't have this problem, say Y. 1571 1572config ARM_PATCH_IDIV 1573 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1574 depends on CPU_32v7 && !XIP_KERNEL 1575 default y 1576 help 1577 The ARM compiler inserts calls to __aeabi_idiv() and 1578 __aeabi_uidiv() when it needs to perform division on signed 1579 and unsigned integers. Some v7 CPUs have support for the sdiv 1580 and udiv instructions that can be used to implement those 1581 functions. 1582 1583 Enabling this option allows the kernel to modify itself to 1584 replace the first two instructions of these library functions 1585 with the sdiv or udiv plus "bx lr" instructions when the CPU 1586 it is running on supports them. Typically this will be faster 1587 and less power intensive than running the original library 1588 code to do integer division. 1589 1590config AEABI 1591 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1592 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1593 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1594 help 1595 This option allows for the kernel to be compiled using the latest 1596 ARM ABI (aka EABI). This is only useful if you are using a user 1597 space environment that is also compiled with EABI. 1598 1599 Since there are major incompatibilities between the legacy ABI and 1600 EABI, especially with regard to structure member alignment, this 1601 option also changes the kernel syscall calling convention to 1602 disambiguate both ABIs and allow for backward compatibility support 1603 (selected with CONFIG_OABI_COMPAT). 1604 1605 To use this you need GCC version 4.0.0 or later. 1606 1607config OABI_COMPAT 1608 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1609 depends on AEABI && !THUMB2_KERNEL 1610 help 1611 This option preserves the old syscall interface along with the 1612 new (ARM EABI) one. It also provides a compatibility layer to 1613 intercept syscalls that have structure arguments which layout 1614 in memory differs between the legacy ABI and the new ARM EABI 1615 (only for non "thumb" binaries). This option adds a tiny 1616 overhead to all syscalls and produces a slightly larger kernel. 1617 1618 The seccomp filter system will not be available when this is 1619 selected, since there is no way yet to sensibly distinguish 1620 between calling conventions during filtering. 1621 1622 If you know you'll be using only pure EABI user space then you 1623 can say N here. If this option is not selected and you attempt 1624 to execute a legacy ABI binary then the result will be 1625 UNPREDICTABLE (in fact it can be predicted that it won't work 1626 at all). If in doubt say N. 1627 1628config ARCH_HAS_HOLES_MEMORYMODEL 1629 bool 1630 1631config ARCH_SPARSEMEM_ENABLE 1632 bool 1633 1634config ARCH_SPARSEMEM_DEFAULT 1635 def_bool ARCH_SPARSEMEM_ENABLE 1636 1637config ARCH_SELECT_MEMORY_MODEL 1638 def_bool ARCH_SPARSEMEM_ENABLE 1639 1640config HAVE_ARCH_PFN_VALID 1641 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1642 1643config HAVE_GENERIC_GUP 1644 def_bool y 1645 depends on ARM_LPAE 1646 1647config HIGHMEM 1648 bool "High Memory Support" 1649 depends on MMU 1650 help 1651 The address space of ARM processors is only 4 Gigabytes large 1652 and it has to accommodate user address space, kernel address 1653 space as well as some memory mapped IO. That means that, if you 1654 have a large amount of physical memory and/or IO, not all of the 1655 memory can be "permanently mapped" by the kernel. The physical 1656 memory that is not permanently mapped is called "high memory". 1657 1658 Depending on the selected kernel/user memory split, minimum 1659 vmalloc space and actual amount of RAM, you may not need this 1660 option which should result in a slightly faster kernel. 1661 1662 If unsure, say n. 1663 1664config HIGHPTE 1665 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1666 depends on HIGHMEM 1667 default y 1668 help 1669 The VM uses one page of physical memory for each page table. 1670 For systems with a lot of processes, this can use a lot of 1671 precious low memory, eventually leading to low memory being 1672 consumed by page tables. Setting this option will allow 1673 user-space 2nd level page tables to reside in high memory. 1674 1675config CPU_SW_DOMAIN_PAN 1676 bool "Enable use of CPU domains to implement privileged no-access" 1677 depends on MMU && !ARM_LPAE 1678 default y 1679 help 1680 Increase kernel security by ensuring that normal kernel accesses 1681 are unable to access userspace addresses. This can help prevent 1682 use-after-free bugs becoming an exploitable privilege escalation 1683 by ensuring that magic values (such as LIST_POISON) will always 1684 fault when dereferenced. 1685 1686 CPUs with low-vector mappings use a best-efforts implementation. 1687 Their lower 1MB needs to remain accessible for the vectors, but 1688 the remainder of userspace will become appropriately inaccessible. 1689 1690config HW_PERF_EVENTS 1691 def_bool y 1692 depends on ARM_PMU 1693 1694config SYS_SUPPORTS_HUGETLBFS 1695 def_bool y 1696 depends on ARM_LPAE 1697 1698config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1699 def_bool y 1700 depends on ARM_LPAE 1701 1702config ARCH_WANT_GENERAL_HUGETLB 1703 def_bool y 1704 1705config ARM_MODULE_PLTS 1706 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1707 depends on MODULES 1708 default y 1709 help 1710 Allocate PLTs when loading modules so that jumps and calls whose 1711 targets are too far away for their relative offsets to be encoded 1712 in the instructions themselves can be bounced via veneers in the 1713 module's PLT. This allows modules to be allocated in the generic 1714 vmalloc area after the dedicated module memory area has been 1715 exhausted. The modules will use slightly more memory, but after 1716 rounding up to page size, the actual memory footprint is usually 1717 the same. 1718 1719 Disabling this is usually safe for small single-platform 1720 configurations. If unsure, say y. 1721 1722config FORCE_MAX_ZONEORDER 1723 int "Maximum zone order" 1724 default "12" if SOC_AM33XX 1725 default "9" if SA1111 || ARCH_EFM32 1726 default "11" 1727 help 1728 The kernel memory allocator divides physically contiguous memory 1729 blocks into "zones", where each zone is a power of two number of 1730 pages. This option selects the largest power of two that the kernel 1731 keeps in the memory allocator. If you need to allocate very large 1732 blocks of physically contiguous memory, then you may need to 1733 increase this value. 1734 1735 This config option is actually maximum order plus one. For example, 1736 a value of 11 means that the largest free memory block is 2^10 pages. 1737 1738config ALIGNMENT_TRAP 1739 bool 1740 depends on CPU_CP15_MMU 1741 default y if !ARCH_EBSA110 1742 select HAVE_PROC_CPU if PROC_FS 1743 help 1744 ARM processors cannot fetch/store information which is not 1745 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1746 address divisible by 4. On 32-bit ARM processors, these non-aligned 1747 fetch/store instructions will be emulated in software if you say 1748 here, which has a severe performance impact. This is necessary for 1749 correct operation of some network protocols. With an IP-only 1750 configuration it is safe to say N, otherwise say Y. 1751 1752config UACCESS_WITH_MEMCPY 1753 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1754 depends on MMU 1755 default y if CPU_FEROCEON 1756 help 1757 Implement faster copy_to_user and clear_user methods for CPU 1758 cores where a 8-word STM instruction give significantly higher 1759 memory write throughput than a sequence of individual 32bit stores. 1760 1761 A possible side effect is a slight increase in scheduling latency 1762 between threads sharing the same address space if they invoke 1763 such copy operations with large buffers. 1764 1765 However, if the CPU data cache is using a write-allocate mode, 1766 this option is unlikely to provide any performance gain. 1767 1768config SECCOMP 1769 bool 1770 prompt "Enable seccomp to safely compute untrusted bytecode" 1771 ---help--- 1772 This kernel feature is useful for number crunching applications 1773 that may need to compute untrusted bytecode during their 1774 execution. By using pipes or other transports made available to 1775 the process as file descriptors supporting the read/write 1776 syscalls, it's possible to isolate those applications in 1777 their own address space using seccomp. Once seccomp is 1778 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1779 and the task is only allowed to execute a few safe syscalls 1780 defined by each seccomp mode. 1781 1782config PARAVIRT 1783 bool "Enable paravirtualization code" 1784 help 1785 This changes the kernel so it can modify itself when it is run 1786 under a hypervisor, potentially improving performance significantly 1787 over full virtualization. 1788 1789config PARAVIRT_TIME_ACCOUNTING 1790 bool "Paravirtual steal time accounting" 1791 select PARAVIRT 1792 default n 1793 help 1794 Select this option to enable fine granularity task steal time 1795 accounting. Time spent executing other tasks in parallel with 1796 the current vCPU is discounted from the vCPU power. To account for 1797 that, there can be a small performance impact. 1798 1799 If in doubt, say N here. 1800 1801config XEN_DOM0 1802 def_bool y 1803 depends on XEN 1804 1805config XEN 1806 bool "Xen guest support on ARM" 1807 depends on ARM && AEABI && OF 1808 depends on CPU_V7 && !CPU_V6 1809 depends on !GENERIC_ATOMIC64 1810 depends on MMU 1811 select ARCH_DMA_ADDR_T_64BIT 1812 select ARM_PSCI 1813 select SWIOTLB 1814 select SWIOTLB_XEN 1815 select PARAVIRT 1816 help 1817 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1818 1819endmenu 1820 1821menu "Boot options" 1822 1823config USE_OF 1824 bool "Flattened Device Tree support" 1825 select IRQ_DOMAIN 1826 select OF 1827 help 1828 Include support for flattened device tree machine descriptions. 1829 1830config ATAGS 1831 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1832 default y 1833 help 1834 This is the traditional way of passing data to the kernel at boot 1835 time. If you are solely relying on the flattened device tree (or 1836 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1837 to remove ATAGS support from your kernel binary. If unsure, 1838 leave this to y. 1839 1840config DEPRECATED_PARAM_STRUCT 1841 bool "Provide old way to pass kernel parameters" 1842 depends on ATAGS 1843 help 1844 This was deprecated in 2001 and announced to live on for 5 years. 1845 Some old boot loaders still use this way. 1846 1847# Compressed boot loader in ROM. Yes, we really want to ask about 1848# TEXT and BSS so we preserve their values in the config files. 1849config ZBOOT_ROM_TEXT 1850 hex "Compressed ROM boot loader base address" 1851 default "0" 1852 help 1853 The physical address at which the ROM-able zImage is to be 1854 placed in the target. Platforms which normally make use of 1855 ROM-able zImage formats normally set this to a suitable 1856 value in their defconfig file. 1857 1858 If ZBOOT_ROM is not enabled, this has no effect. 1859 1860config ZBOOT_ROM_BSS 1861 hex "Compressed ROM boot loader BSS address" 1862 default "0" 1863 help 1864 The base address of an area of read/write memory in the target 1865 for the ROM-able zImage which must be available while the 1866 decompressor is running. It must be large enough to hold the 1867 entire decompressed kernel plus an additional 128 KiB. 1868 Platforms which normally make use of ROM-able zImage formats 1869 normally set this to a suitable value in their defconfig file. 1870 1871 If ZBOOT_ROM is not enabled, this has no effect. 1872 1873config ZBOOT_ROM 1874 bool "Compressed boot loader in ROM/flash" 1875 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1876 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1877 help 1878 Say Y here if you intend to execute your compressed kernel image 1879 (zImage) directly from ROM or flash. If unsure, say N. 1880 1881config ARM_APPENDED_DTB 1882 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1883 depends on OF 1884 help 1885 With this option, the boot code will look for a device tree binary 1886 (DTB) appended to zImage 1887 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1888 1889 This is meant as a backward compatibility convenience for those 1890 systems with a bootloader that can't be upgraded to accommodate 1891 the documented boot protocol using a device tree. 1892 1893 Beware that there is very little in terms of protection against 1894 this option being confused by leftover garbage in memory that might 1895 look like a DTB header after a reboot if no actual DTB is appended 1896 to zImage. Do not leave this option active in a production kernel 1897 if you don't intend to always append a DTB. Proper passing of the 1898 location into r2 of a bootloader provided DTB is always preferable 1899 to this option. 1900 1901config ARM_ATAG_DTB_COMPAT 1902 bool "Supplement the appended DTB with traditional ATAG information" 1903 depends on ARM_APPENDED_DTB 1904 help 1905 Some old bootloaders can't be updated to a DTB capable one, yet 1906 they provide ATAGs with memory configuration, the ramdisk address, 1907 the kernel cmdline string, etc. Such information is dynamically 1908 provided by the bootloader and can't always be stored in a static 1909 DTB. To allow a device tree enabled kernel to be used with such 1910 bootloaders, this option allows zImage to extract the information 1911 from the ATAG list and store it at run time into the appended DTB. 1912 1913choice 1914 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1915 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1916 1917config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1918 bool "Use bootloader kernel arguments if available" 1919 help 1920 Uses the command-line options passed by the boot loader instead of 1921 the device tree bootargs property. If the boot loader doesn't provide 1922 any, the device tree bootargs property will be used. 1923 1924config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1925 bool "Extend with bootloader kernel arguments" 1926 help 1927 The command-line arguments provided by the boot loader will be 1928 appended to the the device tree bootargs property. 1929 1930endchoice 1931 1932config CMDLINE 1933 string "Default kernel command string" 1934 default "" 1935 help 1936 On some architectures (EBSA110 and CATS), there is currently no way 1937 for the boot loader to pass arguments to the kernel. For these 1938 architectures, you should supply some command-line options at build 1939 time by entering them here. As a minimum, you should specify the 1940 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1941 1942choice 1943 prompt "Kernel command line type" if CMDLINE != "" 1944 default CMDLINE_FROM_BOOTLOADER 1945 depends on ATAGS 1946 1947config CMDLINE_FROM_BOOTLOADER 1948 bool "Use bootloader kernel arguments if available" 1949 help 1950 Uses the command-line options passed by the boot loader. If 1951 the boot loader doesn't provide any, the default kernel command 1952 string provided in CMDLINE will be used. 1953 1954config CMDLINE_EXTEND 1955 bool "Extend bootloader kernel arguments" 1956 help 1957 The command-line arguments provided by the boot loader will be 1958 appended to the default kernel command string. 1959 1960config CMDLINE_FORCE 1961 bool "Always use the default kernel command string" 1962 help 1963 Always use the default kernel command string, even if the boot 1964 loader passes other arguments to the kernel. 1965 This is useful if you cannot or don't want to change the 1966 command-line options your boot loader passes to the kernel. 1967endchoice 1968 1969config XIP_KERNEL 1970 bool "Kernel Execute-In-Place from ROM" 1971 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1972 help 1973 Execute-In-Place allows the kernel to run from non-volatile storage 1974 directly addressable by the CPU, such as NOR flash. This saves RAM 1975 space since the text section of the kernel is not loaded from flash 1976 to RAM. Read-write sections, such as the data section and stack, 1977 are still copied to RAM. The XIP kernel is not compressed since 1978 it has to run directly from flash, so it will take more space to 1979 store it. The flash address used to link the kernel object files, 1980 and for storing it, is configuration dependent. Therefore, if you 1981 say Y here, you must know the proper physical address where to 1982 store the kernel image depending on your own flash memory usage. 1983 1984 Also note that the make target becomes "make xipImage" rather than 1985 "make zImage" or "make Image". The final kernel binary to put in 1986 ROM memory will be arch/arm/boot/xipImage. 1987 1988 If unsure, say N. 1989 1990config XIP_PHYS_ADDR 1991 hex "XIP Kernel Physical Location" 1992 depends on XIP_KERNEL 1993 default "0x00080000" 1994 help 1995 This is the physical address in your flash memory the kernel will 1996 be linked for and stored to. This address is dependent on your 1997 own flash usage. 1998 1999config XIP_DEFLATED_DATA 2000 bool "Store kernel .data section compressed in ROM" 2001 depends on XIP_KERNEL 2002 select ZLIB_INFLATE 2003 help 2004 Before the kernel is actually executed, its .data section has to be 2005 copied to RAM from ROM. This option allows for storing that data 2006 in compressed form and decompressed to RAM rather than merely being 2007 copied, saving some precious ROM space. A possible drawback is a 2008 slightly longer boot delay. 2009 2010config KEXEC 2011 bool "Kexec system call (EXPERIMENTAL)" 2012 depends on (!SMP || PM_SLEEP_SMP) 2013 depends on MMU 2014 select KEXEC_CORE 2015 help 2016 kexec is a system call that implements the ability to shutdown your 2017 current kernel, and to start another kernel. It is like a reboot 2018 but it is independent of the system firmware. And like a reboot 2019 you can start any kernel with it, not just Linux. 2020 2021 It is an ongoing process to be certain the hardware in a machine 2022 is properly shutdown, so do not be surprised if this code does not 2023 initially work for you. 2024 2025config ATAGS_PROC 2026 bool "Export atags in procfs" 2027 depends on ATAGS && KEXEC 2028 default y 2029 help 2030 Should the atags used to boot the kernel be exported in an "atags" 2031 file in procfs. Useful with kexec. 2032 2033config CRASH_DUMP 2034 bool "Build kdump crash kernel (EXPERIMENTAL)" 2035 help 2036 Generate crash dump after being started by kexec. This should 2037 be normally only set in special crash dump kernels which are 2038 loaded in the main kernel with kexec-tools into a specially 2039 reserved region and then later executed after a crash by 2040 kdump/kexec. The crash dump kernel must be compiled to a 2041 memory address not used by the main kernel 2042 2043 For more details see Documentation/kdump/kdump.txt 2044 2045config AUTO_ZRELADDR 2046 bool "Auto calculation of the decompressed kernel image address" 2047 help 2048 ZRELADDR is the physical address where the decompressed kernel 2049 image will be placed. If AUTO_ZRELADDR is selected, the address 2050 will be determined at run-time by masking the current IP with 2051 0xf8000000. This assumes the zImage being placed in the first 128MB 2052 from start of memory. 2053 2054config EFI_STUB 2055 bool 2056 2057config EFI 2058 bool "UEFI runtime support" 2059 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 2060 select UCS2_STRING 2061 select EFI_PARAMS_FROM_FDT 2062 select EFI_STUB 2063 select EFI_ARMSTUB 2064 select EFI_RUNTIME_WRAPPERS 2065 ---help--- 2066 This option provides support for runtime services provided 2067 by UEFI firmware (such as non-volatile variables, realtime 2068 clock, and platform reset). A UEFI stub is also provided to 2069 allow the kernel to be booted as an EFI application. This 2070 is only useful for kernels that may run on systems that have 2071 UEFI firmware. 2072 2073config DMI 2074 bool "Enable support for SMBIOS (DMI) tables" 2075 depends on EFI 2076 default y 2077 help 2078 This enables SMBIOS/DMI feature for systems. 2079 2080 This option is only useful on systems that have UEFI firmware. 2081 However, even with this option, the resultant kernel should 2082 continue to boot on existing non-UEFI platforms. 2083 2084 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 2085 i.e., the the practice of identifying the platform via DMI to 2086 decide whether certain workarounds for buggy hardware and/or 2087 firmware need to be enabled. This would require the DMI subsystem 2088 to be enabled much earlier than we do on ARM, which is non-trivial. 2089 2090endmenu 2091 2092menu "CPU Power Management" 2093 2094source "drivers/cpufreq/Kconfig" 2095 2096source "drivers/cpuidle/Kconfig" 2097 2098endmenu 2099 2100menu "Floating point emulation" 2101 2102comment "At least one emulation must be selected" 2103 2104config FPE_NWFPE 2105 bool "NWFPE math emulation" 2106 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2107 ---help--- 2108 Say Y to include the NWFPE floating point emulator in the kernel. 2109 This is necessary to run most binaries. Linux does not currently 2110 support floating point hardware so you need to say Y here even if 2111 your machine has an FPA or floating point co-processor podule. 2112 2113 You may say N here if you are going to load the Acorn FPEmulator 2114 early in the bootup. 2115 2116config FPE_NWFPE_XP 2117 bool "Support extended precision" 2118 depends on FPE_NWFPE 2119 help 2120 Say Y to include 80-bit support in the kernel floating-point 2121 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2122 Note that gcc does not generate 80-bit operations by default, 2123 so in most cases this option only enlarges the size of the 2124 floating point emulator without any good reason. 2125 2126 You almost surely want to say N here. 2127 2128config FPE_FASTFPE 2129 bool "FastFPE math emulation (EXPERIMENTAL)" 2130 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2131 ---help--- 2132 Say Y here to include the FAST floating point emulator in the kernel. 2133 This is an experimental much faster emulator which now also has full 2134 precision for the mantissa. It does not support any exceptions. 2135 It is very simple, and approximately 3-6 times faster than NWFPE. 2136 2137 It should be sufficient for most programs. It may be not suitable 2138 for scientific calculations, but you have to check this for yourself. 2139 If you do not feel you need a faster FP emulation you should better 2140 choose NWFPE. 2141 2142config VFP 2143 bool "VFP-format floating point maths" 2144 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2145 help 2146 Say Y to include VFP support code in the kernel. This is needed 2147 if your hardware includes a VFP unit. 2148 2149 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2150 release notes and additional status information. 2151 2152 Say N if your target does not have VFP hardware. 2153 2154config VFPv3 2155 bool 2156 depends on VFP 2157 default y if CPU_V7 2158 2159config NEON 2160 bool "Advanced SIMD (NEON) Extension support" 2161 depends on VFPv3 && CPU_V7 2162 help 2163 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2164 Extension. 2165 2166config KERNEL_MODE_NEON 2167 bool "Support for NEON in kernel mode" 2168 depends on NEON && AEABI 2169 help 2170 Say Y to include support for NEON in kernel mode. 2171 2172endmenu 2173 2174menu "Power management options" 2175 2176source "kernel/power/Kconfig" 2177 2178config ARCH_SUSPEND_POSSIBLE 2179 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2180 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2181 def_bool y 2182 2183config ARM_CPU_SUSPEND 2184 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2185 depends on ARCH_SUSPEND_POSSIBLE 2186 2187config ARCH_HIBERNATION_POSSIBLE 2188 bool 2189 depends on MMU 2190 default y if ARCH_SUSPEND_POSSIBLE 2191 2192endmenu 2193 2194source "drivers/firmware/Kconfig" 2195 2196if CRYPTO 2197source "arch/arm/crypto/Kconfig" 2198endif 2199 2200source "arch/arm/kvm/Kconfig" 2201