Lines Matching full:cluster
11 * Cluster cache enable trampoline code adapted from MCPM framework
88 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster) in sunxi_core_is_cortex_a15() argument
91 int cpu = cluster * SUNXI_CPUS_PER_CLUSTER + core; in sunxi_core_is_cortex_a15()
102 * would be mid way in a core or cluster power sequence. in sunxi_core_is_cortex_a15()
104 pr_err("%s: Couldn't get CPU cluster %u core %u device node\n", in sunxi_core_is_cortex_a15()
105 __func__, cluster, core); in sunxi_core_is_cortex_a15()
113 static int sunxi_cpu_power_switch_set(unsigned int cpu, unsigned int cluster, in sunxi_cpu_power_switch_set() argument
119 reg = readl(prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu)); in sunxi_cpu_power_switch_set()
122 pr_debug("power clamp for cluster %u cpu %u already open\n", in sunxi_cpu_power_switch_set()
123 cluster, cpu); in sunxi_cpu_power_switch_set()
127 writel(0xff, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu)); in sunxi_cpu_power_switch_set()
129 writel(0xfe, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu)); in sunxi_cpu_power_switch_set()
131 writel(0xf8, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu)); in sunxi_cpu_power_switch_set()
133 writel(0xf0, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu)); in sunxi_cpu_power_switch_set()
135 writel(0x00, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu)); in sunxi_cpu_power_switch_set()
138 writel(0xff, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu)); in sunxi_cpu_power_switch_set()
156 static int sunxi_cpu_powerup(unsigned int cpu, unsigned int cluster) in sunxi_cpu_powerup() argument
160 pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu); in sunxi_cpu_powerup()
161 if (cpu >= SUNXI_CPUS_PER_CLUSTER || cluster >= SUNXI_NR_CLUSTERS) in sunxi_cpu_powerup()
165 if (cluster == 0 && cpu == 0) in sunxi_cpu_powerup()
169 reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); in sunxi_cpu_powerup()
171 writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); in sunxi_cpu_powerup()
176 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster)); in sunxi_cpu_powerup()
179 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster)); in sunxi_cpu_powerup()
184 if (!sunxi_core_is_cortex_a15(cpu, cluster)) { in sunxi_cpu_powerup()
185 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster)); in sunxi_cpu_powerup()
187 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster)); in sunxi_cpu_powerup()
191 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); in sunxi_cpu_powerup()
198 if (!sunxi_core_is_cortex_a15(cpu, cluster)) in sunxi_cpu_powerup()
201 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); in sunxi_cpu_powerup()
204 sunxi_cpu_power_switch_set(cpu, cluster, true); in sunxi_cpu_powerup()
213 reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster)); in sunxi_cpu_powerup()
215 writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster)); in sunxi_cpu_powerup()
225 reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); in sunxi_cpu_powerup()
227 writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); in sunxi_cpu_powerup()
231 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster)); in sunxi_cpu_powerup()
234 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster)); in sunxi_cpu_powerup()
239 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); in sunxi_cpu_powerup()
242 if (!sunxi_core_is_cortex_a15(cpu, cluster)) in sunxi_cpu_powerup()
246 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); in sunxi_cpu_powerup()
251 static int sunxi_cluster_powerup(unsigned int cluster) in sunxi_cluster_powerup() argument
255 pr_debug("%s: cluster %u\n", __func__, cluster); in sunxi_cluster_powerup()
256 if (cluster >= SUNXI_NR_CLUSTERS) in sunxi_cluster_powerup()
259 /* For A83T, assert cluster cores resets */ in sunxi_cluster_powerup()
261 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); in sunxi_cluster_powerup()
263 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); in sunxi_cluster_powerup()
268 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster)); in sunxi_cluster_powerup()
270 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster)); in sunxi_cluster_powerup()
272 /* assert cluster processor power-on resets */ in sunxi_cluster_powerup()
273 reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); in sunxi_cluster_powerup()
275 writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster)); in sunxi_cluster_powerup()
277 /* assert cluster cores resets */ in sunxi_cluster_powerup()
280 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster)); in sunxi_cluster_powerup()
283 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster)); in sunxi_cluster_powerup()
287 /* assert cluster resets */ in sunxi_cluster_powerup()
288 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); in sunxi_cluster_powerup()
298 if (!sunxi_core_is_cortex_a15(0, cluster)) in sunxi_cluster_powerup()
301 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); in sunxi_cluster_powerup()
304 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster)); in sunxi_cluster_powerup()
305 if (sunxi_core_is_cortex_a15(0, cluster)) { in sunxi_cluster_powerup()
313 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster)); in sunxi_cluster_powerup()
315 /* clear cluster power gate */ in sunxi_cluster_powerup()
316 reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster)); in sunxi_cluster_powerup()
321 writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster)); in sunxi_cluster_powerup()
324 /* de-assert cluster resets */ in sunxi_cluster_powerup()
325 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); in sunxi_cluster_powerup()
329 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); in sunxi_cluster_powerup()
332 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster)); in sunxi_cluster_powerup()
334 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster)); in sunxi_cluster_powerup()
341 * enable CCI-400 and proper cluster cache disable before power down.
357 /* Flush all cache levels for this cluster. */ in sunxi_cluster_cache_disable_without_axi()
361 * Disable cluster-level coherency by masking in sunxi_cluster_cache_disable_without_axi()
372 static bool sunxi_mc_smp_cluster_is_down(unsigned int cluster) in sunxi_mc_smp_cluster_is_down() argument
377 if (sunxi_mc_smp_cpu_table[cluster][i]) in sunxi_mc_smp_cluster_is_down()
391 unsigned int mpidr, cpu, cluster; in sunxi_mc_smp_boot_secondary() local
395 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in sunxi_mc_smp_boot_secondary()
399 if (cluster >= SUNXI_NR_CLUSTERS || cpu >= SUNXI_CPUS_PER_CLUSTER) in sunxi_mc_smp_boot_secondary()
404 if (sunxi_mc_smp_cpu_table[cluster][cpu]) in sunxi_mc_smp_boot_secondary()
407 if (sunxi_mc_smp_cluster_is_down(cluster)) { in sunxi_mc_smp_boot_secondary()
409 sunxi_cluster_powerup(cluster); in sunxi_mc_smp_boot_secondary()
416 sunxi_cpu_powerup(cpu, cluster); in sunxi_mc_smp_boot_secondary()
419 sunxi_mc_smp_cpu_table[cluster][cpu]++; in sunxi_mc_smp_boot_secondary()
428 unsigned int cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1); in sunxi_cluster_cache_disable() local
431 pr_debug("%s: cluster %u\n", __func__, cluster); in sunxi_cluster_cache_disable()
436 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster)); in sunxi_cluster_cache_disable()
438 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster)); in sunxi_cluster_cache_disable()
443 unsigned int mpidr, cpu, cluster; in sunxi_mc_smp_cpu_die() local
448 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in sunxi_mc_smp_cpu_die()
449 pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu); in sunxi_mc_smp_cpu_die()
452 sunxi_mc_smp_cpu_table[cluster][cpu]--; in sunxi_mc_smp_cpu_die()
453 if (sunxi_mc_smp_cpu_table[cluster][cpu] == 1) { in sunxi_mc_smp_cpu_die()
459 } else if (sunxi_mc_smp_cpu_table[cluster][cpu] > 1) { in sunxi_mc_smp_cpu_die()
460 pr_err("Cluster %d CPU%d boots multiple times\n", in sunxi_mc_smp_cpu_die()
461 cluster, cpu); in sunxi_mc_smp_cpu_die()
465 last_man = sunxi_mc_smp_cluster_is_down(cluster); in sunxi_mc_smp_cpu_die()
478 static int sunxi_cpu_powerdown(unsigned int cpu, unsigned int cluster) in sunxi_cpu_powerdown() argument
483 pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu); in sunxi_cpu_powerdown()
484 if (cpu >= SUNXI_CPUS_PER_CLUSTER || cluster >= SUNXI_NR_CLUSTERS) in sunxi_cpu_powerdown()
491 reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster)); in sunxi_cpu_powerdown()
493 writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster)); in sunxi_cpu_powerdown()
497 sunxi_cpu_power_switch_set(cpu, cluster, false); in sunxi_cpu_powerdown()
502 static int sunxi_cluster_powerdown(unsigned int cluster) in sunxi_cluster_powerdown() argument
506 pr_debug("%s: cluster %u\n", __func__, cluster); in sunxi_cluster_powerdown()
507 if (cluster >= SUNXI_NR_CLUSTERS) in sunxi_cluster_powerdown()
510 /* assert cluster resets or system will hang */ in sunxi_cluster_powerdown()
511 pr_debug("%s: assert cluster reset\n", __func__); in sunxi_cluster_powerdown()
512 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); in sunxi_cluster_powerdown()
516 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster)); in sunxi_cluster_powerdown()
518 /* gate cluster power */ in sunxi_cluster_powerdown()
519 pr_debug("%s: gate cluster power\n", __func__); in sunxi_cluster_powerdown()
520 reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster)); in sunxi_cluster_powerdown()
525 writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster)); in sunxi_cluster_powerdown()
533 unsigned int mpidr, cpu, cluster; in sunxi_mc_smp_cpu_kill() local
540 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in sunxi_mc_smp_cpu_kill()
543 if (WARN_ON(cluster >= SUNXI_NR_CLUSTERS || in sunxi_mc_smp_cpu_kill()
562 if (sunxi_mc_smp_cpu_table[cluster][cpu]) in sunxi_mc_smp_cpu_kill()
565 reg = readl(cpucfg_base + CPUCFG_CX_STATUS(cluster)); in sunxi_mc_smp_cpu_kill()
576 sunxi_cpu_powerdown(cpu, cluster); in sunxi_mc_smp_cpu_kill()
578 if (!sunxi_mc_smp_cluster_is_down(cluster)) in sunxi_mc_smp_cpu_kill()
581 /* wait for cluster L2 WFI */ in sunxi_mc_smp_cpu_kill()
582 ret = readl_poll_timeout(cpucfg_base + CPUCFG_CX_STATUS(cluster), reg, in sunxi_mc_smp_cpu_kill()
587 * Ignore timeout on the cluster. Leaving the cluster on in sunxi_mc_smp_cpu_kill()
596 /* Power down cluster */ in sunxi_mc_smp_cpu_kill()
597 sunxi_cluster_powerdown(cluster); in sunxi_mc_smp_cpu_kill()
601 pr_debug("%s: cluster %u cpu %u powerdown: %d\n", in sunxi_mc_smp_cpu_kill()
602 __func__, cluster, cpu, ret); in sunxi_mc_smp_cpu_kill()
628 unsigned int mpidr, cpu, cluster; in sunxi_mc_smp_cpu_table_init() local
632 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in sunxi_mc_smp_cpu_table_init()
634 if (cluster >= SUNXI_NR_CLUSTERS || cpu >= SUNXI_CPUS_PER_CLUSTER) { in sunxi_mc_smp_cpu_table_init()
638 sunxi_mc_smp_cpu_table[cluster][cpu] = 1; in sunxi_mc_smp_cpu_table_init()
645 * We need the trampoline code to enable CCI-400 on the first cluster
866 /* Configure CCI-400 for boot cluster */ in sunxi_mc_smp_init()
869 pr_err("%s: failed to configure boot cluster: %d\n", in sunxi_mc_smp_init()
884 /* Actually enable multi cluster SMP */ in sunxi_mc_smp_init()
887 pr_info("sunxi multi cluster SMP support installed\n"); in sunxi_mc_smp_init()