Lines Matching +full:1 +full:c
47 * [ ] [ sample ] [cache] [ pmc ] [unit ] c m [ pmcxsel ]
78 * MMCRC[53:55] = cache_sel[1:3] (L2EVENT_SEL)
81 * MMCRC[47:49] = cache_sel[1:3] (L3EVENT_SEL0)
82 * else if cache_sel[0] == 1:
84 * else if cache_sel[1]: # L1 event
89 * MMCRA[63] = 1 (SAMPLE_ENABLE)
228 return -1; in power8_bhrb_filter_map()
231 return -1; in power8_bhrb_filter_map()
234 return -1; in power8_bhrb_filter_map()
242 return -1; in power8_bhrb_filter_map()
253 #define C(x) PERF_COUNT_HW_CACHE_##x macro
257 * 0 means not supported, -1 means nonsensical, other values
260 static int power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
261 [ C(L1D) ] = {
262 [ C(OP_READ) ] = {
263 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
264 [ C(RESULT_MISS) ] = PM_LD_MISS_L1,
266 [ C(OP_WRITE) ] = {
267 [ C(RESULT_ACCESS) ] = 0,
268 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
270 [ C(OP_PREFETCH) ] = {
271 [ C(RESULT_ACCESS) ] = PM_L1_PREF,
272 [ C(RESULT_MISS) ] = 0,
275 [ C(L1I) ] = {
276 [ C(OP_READ) ] = {
277 [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
278 [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS,
280 [ C(OP_WRITE) ] = {
281 [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
282 [ C(RESULT_MISS) ] = -1,
284 [ C(OP_PREFETCH) ] = {
285 [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
286 [ C(RESULT_MISS) ] = 0,
289 [ C(LL) ] = {
290 [ C(OP_READ) ] = {
291 [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
292 [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS,
294 [ C(OP_WRITE) ] = {
295 [ C(RESULT_ACCESS) ] = PM_L2_ST,
296 [ C(RESULT_MISS) ] = PM_L2_ST_MISS,
298 [ C(OP_PREFETCH) ] = {
299 [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
300 [ C(RESULT_MISS) ] = 0,
303 [ C(DTLB) ] = {
304 [ C(OP_READ) ] = {
305 [ C(RESULT_ACCESS) ] = 0,
306 [ C(RESULT_MISS) ] = PM_DTLB_MISS,
308 [ C(OP_WRITE) ] = {
309 [ C(RESULT_ACCESS) ] = -1,
310 [ C(RESULT_MISS) ] = -1,
312 [ C(OP_PREFETCH) ] = {
313 [ C(RESULT_ACCESS) ] = -1,
314 [ C(RESULT_MISS) ] = -1,
317 [ C(ITLB) ] = {
318 [ C(OP_READ) ] = {
319 [ C(RESULT_ACCESS) ] = 0,
320 [ C(RESULT_MISS) ] = PM_ITLB_MISS,
322 [ C(OP_WRITE) ] = {
323 [ C(RESULT_ACCESS) ] = -1,
324 [ C(RESULT_MISS) ] = -1,
326 [ C(OP_PREFETCH) ] = {
327 [ C(RESULT_ACCESS) ] = -1,
328 [ C(RESULT_MISS) ] = -1,
331 [ C(BPU) ] = {
332 [ C(OP_READ) ] = {
333 [ C(RESULT_ACCESS) ] = PM_BRU_FIN,
334 [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL,
336 [ C(OP_WRITE) ] = {
337 [ C(RESULT_ACCESS) ] = -1,
338 [ C(RESULT_MISS) ] = -1,
340 [ C(OP_PREFETCH) ] = {
341 [ C(RESULT_ACCESS) ] = -1,
342 [ C(RESULT_MISS) ] = -1,
345 [ C(NODE) ] = {
346 [ C(OP_READ) ] = {
347 [ C(RESULT_ACCESS) ] = -1,
348 [ C(RESULT_MISS) ] = -1,
350 [ C(OP_WRITE) ] = {
351 [ C(RESULT_ACCESS) ] = -1,
352 [ C(RESULT_MISS) ] = -1,
354 [ C(OP_PREFETCH) ] = {
355 [ C(RESULT_ACCESS) ] = -1,
356 [ C(RESULT_MISS) ] = -1,
361 #undef C
366 .max_alternatives = MAX_ALT + 1,