1 /*
2 * Performance counter support for POWER8 processors.
3 *
4 * Copyright 2009 Paul Mackerras, IBM Corporation.
5 * Copyright 2013 Michael Ellerman, IBM Corporation.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13 #define pr_fmt(fmt) "power8-pmu: " fmt
14
15 #include "isa207-common.h"
16
17 /*
18 * Some power8 event codes.
19 */
20 #define EVENT(_name, _code) _name = _code,
21
22 enum {
23 #include "power8-events-list.h"
24 };
25
26 #undef EVENT
27
28 /* MMCRA IFM bits - POWER8 */
29 #define POWER8_MMCRA_IFM1 0x0000000040000000UL
30 #define POWER8_MMCRA_IFM2 0x0000000080000000UL
31 #define POWER8_MMCRA_IFM3 0x00000000C0000000UL
32 #define POWER8_MMCRA_BHRB_MASK 0x00000000C0000000UL
33
34 /*
35 * Raw event encoding for PowerISA v2.07 (Power8):
36 *
37 * 60 56 52 48 44 40 36 32
38 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
39 * | | [ ] [ thresh_cmp ] [ thresh_ctl ]
40 * | | | |
41 * | | *- IFM (Linux) thresh start/stop OR FAB match -*
42 * | *- BHRB (Linux)
43 * *- EBB (Linux)
44 *
45 * 28 24 20 16 12 8 4 0
46 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
47 * [ ] [ sample ] [cache] [ pmc ] [unit ] c m [ pmcxsel ]
48 * | | | | |
49 * | | | | *- mark
50 * | | *- L1/L2/L3 cache_sel |
51 * | | |
52 * | *- sampling mode for marked events *- combine
53 * |
54 * *- thresh_sel
55 *
56 * Below uses IBM bit numbering.
57 *
58 * MMCR1[x:y] = unit (PMCxUNIT)
59 * MMCR1[x] = combine (PMCxCOMB)
60 *
61 * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
62 * # PM_MRK_FAB_RSP_MATCH
63 * MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
64 * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
65 * # PM_MRK_FAB_RSP_MATCH_CYC
66 * MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
67 * else
68 * MMCRA[48:55] = thresh_ctl (THRESH START/END)
69 *
70 * if thresh_sel:
71 * MMCRA[45:47] = thresh_sel
72 *
73 * if thresh_cmp:
74 * MMCRA[22:24] = thresh_cmp[0:2]
75 * MMCRA[25:31] = thresh_cmp[3:9]
76 *
77 * if unit == 6 or unit == 7
78 * MMCRC[53:55] = cache_sel[1:3] (L2EVENT_SEL)
79 * else if unit == 8 or unit == 9:
80 * if cache_sel[0] == 0: # L3 bank
81 * MMCRC[47:49] = cache_sel[1:3] (L3EVENT_SEL0)
82 * else if cache_sel[0] == 1:
83 * MMCRC[50:51] = cache_sel[2:3] (L3EVENT_SEL1)
84 * else if cache_sel[1]: # L1 event
85 * MMCR1[16] = cache_sel[2]
86 * MMCR1[17] = cache_sel[3]
87 *
88 * if mark:
89 * MMCRA[63] = 1 (SAMPLE_ENABLE)
90 * MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG)
91 * MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE)
92 *
93 * if EBB and BHRB:
94 * MMCRA[32:33] = IFM
95 *
96 */
97
98 /* PowerISA v2.07 format attribute structure*/
99 extern struct attribute_group isa207_pmu_format_group;
100
101 /* Table of alternatives, sorted by column 0 */
102 static const unsigned int event_alternatives[][MAX_ALT] = {
103 { PM_MRK_ST_CMPL, PM_MRK_ST_CMPL_ALT },
104 { PM_BR_MRK_2PATH, PM_BR_MRK_2PATH_ALT },
105 { PM_L3_CO_MEPF, PM_L3_CO_MEPF_ALT },
106 { PM_MRK_DATA_FROM_L2MISS, PM_MRK_DATA_FROM_L2MISS_ALT },
107 { PM_CMPLU_STALL_ALT, PM_CMPLU_STALL },
108 { PM_BR_2PATH, PM_BR_2PATH_ALT },
109 { PM_INST_DISP, PM_INST_DISP_ALT },
110 { PM_RUN_CYC_ALT, PM_RUN_CYC },
111 { PM_MRK_FILT_MATCH, PM_MRK_FILT_MATCH_ALT },
112 { PM_LD_MISS_L1, PM_LD_MISS_L1_ALT },
113 { PM_RUN_INST_CMPL_ALT, PM_RUN_INST_CMPL },
114 };
115
power8_get_alternatives(u64 event,unsigned int flags,u64 alt[])116 static int power8_get_alternatives(u64 event, unsigned int flags, u64 alt[])
117 {
118 int num_alt = 0;
119
120 num_alt = isa207_get_alternatives(event, alt,
121 ARRAY_SIZE(event_alternatives), flags,
122 event_alternatives);
123
124 return num_alt;
125 }
126
127 GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC);
128 GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_GCT_NOSLOT_CYC);
129 GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL);
130 GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL);
131 GENERIC_EVENT_ATTR(branch-instructions, PM_BRU_FIN);
132 GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
133 GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1);
134 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1);
135 GENERIC_EVENT_ATTR(mem_access, MEM_ACCESS);
136
137 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
138 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
139
140 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);
141 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
142 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
143 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
144 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
145
146 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
147 CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3);
148 CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PREF_ALL);
149 CACHE_EVENT_ATTR(LLC-store-misses, PM_L2_ST_MISS);
150 CACHE_EVENT_ATTR(LLC-stores, PM_L2_ST);
151
152 CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);
153 CACHE_EVENT_ATTR(branch-loads, PM_BRU_FIN);
154 CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);
155 CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);
156
157 static struct attribute *power8_events_attr[] = {
158 GENERIC_EVENT_PTR(PM_CYC),
159 GENERIC_EVENT_PTR(PM_GCT_NOSLOT_CYC),
160 GENERIC_EVENT_PTR(PM_CMPLU_STALL),
161 GENERIC_EVENT_PTR(PM_INST_CMPL),
162 GENERIC_EVENT_PTR(PM_BRU_FIN),
163 GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
164 GENERIC_EVENT_PTR(PM_LD_REF_L1),
165 GENERIC_EVENT_PTR(PM_LD_MISS_L1),
166 GENERIC_EVENT_PTR(MEM_ACCESS),
167
168 CACHE_EVENT_PTR(PM_LD_MISS_L1),
169 CACHE_EVENT_PTR(PM_LD_REF_L1),
170 CACHE_EVENT_PTR(PM_L1_PREF),
171 CACHE_EVENT_PTR(PM_ST_MISS_L1),
172 CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
173 CACHE_EVENT_PTR(PM_INST_FROM_L1),
174 CACHE_EVENT_PTR(PM_IC_PREF_WRITE),
175 CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
176 CACHE_EVENT_PTR(PM_DATA_FROM_L3),
177 CACHE_EVENT_PTR(PM_L3_PREF_ALL),
178 CACHE_EVENT_PTR(PM_L2_ST_MISS),
179 CACHE_EVENT_PTR(PM_L2_ST),
180
181 CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
182 CACHE_EVENT_PTR(PM_BRU_FIN),
183
184 CACHE_EVENT_PTR(PM_DTLB_MISS),
185 CACHE_EVENT_PTR(PM_ITLB_MISS),
186 NULL
187 };
188
189 static struct attribute_group power8_pmu_events_group = {
190 .name = "events",
191 .attrs = power8_events_attr,
192 };
193
194 static const struct attribute_group *power8_pmu_attr_groups[] = {
195 &isa207_pmu_format_group,
196 &power8_pmu_events_group,
197 NULL,
198 };
199
200 static int power8_generic_events[] = {
201 [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
202 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_GCT_NOSLOT_CYC,
203 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL,
204 [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL,
205 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BRU_FIN,
206 [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL,
207 [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1,
208 [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1,
209 };
210
power8_bhrb_filter_map(u64 branch_sample_type)211 static u64 power8_bhrb_filter_map(u64 branch_sample_type)
212 {
213 u64 pmu_bhrb_filter = 0;
214
215 /* BHRB and regular PMU events share the same privilege state
216 * filter configuration. BHRB is always recorded along with a
217 * regular PMU event. As the privilege state filter is handled
218 * in the basic PMC configuration of the accompanying regular
219 * PMU event, we ignore any separate BHRB specific request.
220 */
221
222 /* No branch filter requested */
223 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY)
224 return pmu_bhrb_filter;
225
226 /* Invalid branch filter options - HW does not support */
227 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
228 return -1;
229
230 if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL)
231 return -1;
232
233 if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL)
234 return -1;
235
236 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) {
237 pmu_bhrb_filter |= POWER8_MMCRA_IFM1;
238 return pmu_bhrb_filter;
239 }
240
241 /* Every thing else is unsupported */
242 return -1;
243 }
244
power8_config_bhrb(u64 pmu_bhrb_filter)245 static void power8_config_bhrb(u64 pmu_bhrb_filter)
246 {
247 pmu_bhrb_filter &= POWER8_MMCRA_BHRB_MASK;
248
249 /* Enable BHRB filter in PMU */
250 mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
251 }
252
253 #define C(x) PERF_COUNT_HW_CACHE_##x
254
255 /*
256 * Table of generalized cache-related events.
257 * 0 means not supported, -1 means nonsensical, other values
258 * are event codes.
259 */
260 static int power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
261 [ C(L1D) ] = {
262 [ C(OP_READ) ] = {
263 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
264 [ C(RESULT_MISS) ] = PM_LD_MISS_L1,
265 },
266 [ C(OP_WRITE) ] = {
267 [ C(RESULT_ACCESS) ] = 0,
268 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
269 },
270 [ C(OP_PREFETCH) ] = {
271 [ C(RESULT_ACCESS) ] = PM_L1_PREF,
272 [ C(RESULT_MISS) ] = 0,
273 },
274 },
275 [ C(L1I) ] = {
276 [ C(OP_READ) ] = {
277 [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
278 [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS,
279 },
280 [ C(OP_WRITE) ] = {
281 [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
282 [ C(RESULT_MISS) ] = -1,
283 },
284 [ C(OP_PREFETCH) ] = {
285 [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
286 [ C(RESULT_MISS) ] = 0,
287 },
288 },
289 [ C(LL) ] = {
290 [ C(OP_READ) ] = {
291 [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
292 [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS,
293 },
294 [ C(OP_WRITE) ] = {
295 [ C(RESULT_ACCESS) ] = PM_L2_ST,
296 [ C(RESULT_MISS) ] = PM_L2_ST_MISS,
297 },
298 [ C(OP_PREFETCH) ] = {
299 [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
300 [ C(RESULT_MISS) ] = 0,
301 },
302 },
303 [ C(DTLB) ] = {
304 [ C(OP_READ) ] = {
305 [ C(RESULT_ACCESS) ] = 0,
306 [ C(RESULT_MISS) ] = PM_DTLB_MISS,
307 },
308 [ C(OP_WRITE) ] = {
309 [ C(RESULT_ACCESS) ] = -1,
310 [ C(RESULT_MISS) ] = -1,
311 },
312 [ C(OP_PREFETCH) ] = {
313 [ C(RESULT_ACCESS) ] = -1,
314 [ C(RESULT_MISS) ] = -1,
315 },
316 },
317 [ C(ITLB) ] = {
318 [ C(OP_READ) ] = {
319 [ C(RESULT_ACCESS) ] = 0,
320 [ C(RESULT_MISS) ] = PM_ITLB_MISS,
321 },
322 [ C(OP_WRITE) ] = {
323 [ C(RESULT_ACCESS) ] = -1,
324 [ C(RESULT_MISS) ] = -1,
325 },
326 [ C(OP_PREFETCH) ] = {
327 [ C(RESULT_ACCESS) ] = -1,
328 [ C(RESULT_MISS) ] = -1,
329 },
330 },
331 [ C(BPU) ] = {
332 [ C(OP_READ) ] = {
333 [ C(RESULT_ACCESS) ] = PM_BRU_FIN,
334 [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL,
335 },
336 [ C(OP_WRITE) ] = {
337 [ C(RESULT_ACCESS) ] = -1,
338 [ C(RESULT_MISS) ] = -1,
339 },
340 [ C(OP_PREFETCH) ] = {
341 [ C(RESULT_ACCESS) ] = -1,
342 [ C(RESULT_MISS) ] = -1,
343 },
344 },
345 [ C(NODE) ] = {
346 [ C(OP_READ) ] = {
347 [ C(RESULT_ACCESS) ] = -1,
348 [ C(RESULT_MISS) ] = -1,
349 },
350 [ C(OP_WRITE) ] = {
351 [ C(RESULT_ACCESS) ] = -1,
352 [ C(RESULT_MISS) ] = -1,
353 },
354 [ C(OP_PREFETCH) ] = {
355 [ C(RESULT_ACCESS) ] = -1,
356 [ C(RESULT_MISS) ] = -1,
357 },
358 },
359 };
360
361 #undef C
362
363 static struct power_pmu power8_pmu = {
364 .name = "POWER8",
365 .n_counter = MAX_PMU_COUNTERS,
366 .max_alternatives = MAX_ALT + 1,
367 .add_fields = ISA207_ADD_FIELDS,
368 .test_adder = ISA207_TEST_ADDER,
369 .compute_mmcr = isa207_compute_mmcr,
370 .config_bhrb = power8_config_bhrb,
371 .bhrb_filter_map = power8_bhrb_filter_map,
372 .get_constraint = isa207_get_constraint,
373 .get_alternatives = power8_get_alternatives,
374 .get_mem_data_src = isa207_get_mem_data_src,
375 .get_mem_weight = isa207_get_mem_weight,
376 .disable_pmc = isa207_disable_pmc,
377 .flags = PPMU_HAS_SIER | PPMU_ARCH_207S,
378 .n_generic = ARRAY_SIZE(power8_generic_events),
379 .generic_events = power8_generic_events,
380 .cache_events = &power8_cache_events,
381 .attr_groups = power8_pmu_attr_groups,
382 .bhrb_nr = 32,
383 };
384
init_power8_pmu(void)385 static int __init init_power8_pmu(void)
386 {
387 int rc;
388
389 if (!cur_cpu_spec->oprofile_cpu_type ||
390 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power8"))
391 return -ENODEV;
392
393 rc = register_power_pmu(&power8_pmu);
394 if (rc)
395 return rc;
396
397 /* Tell userspace that EBB is supported */
398 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
399
400 if (cpu_has_feature(CPU_FTR_PMAO_BUG))
401 pr_info("PMAO restore workaround active.\n");
402
403 return 0;
404 }
405 early_initcall(init_power8_pmu);
406