Lines Matching +full:0 +full:xd
47 #define DBG_VERBOSE(fmt...) do { } while(0)
81 * or 0 if there is no new entry.
90 return 0; in xive_read_eq()
95 return 0; in xive_read_eq()
103 if (q->idx == 0) in xive_read_eq()
107 return cur & 0x7fffffff; in xive_read_eq()
117 * (0xff if none) and return what was found (0 if none).
135 u32 irq = 0; in xive_scan_interrupts()
139 while (xc->pending_prio != 0) { in xive_scan_interrupts()
162 int p = atomic_xchg(&q->pending_count, 0); in xive_scan_interrupts()
170 /* If nothing was found, set CPPR to 0xff */ in xive_scan_interrupts()
171 if (irq == 0) in xive_scan_interrupts()
172 prio = 0xff; in xive_scan_interrupts()
188 static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset) in xive_esb_read() argument
193 if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG) in xive_esb_read()
196 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw) in xive_esb_read()
197 val = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0); in xive_esb_read()
199 val = in_be64(xd->eoi_mmio + offset); in xive_esb_read()
204 static void xive_esb_write(struct xive_irq_data *xd, u32 offset, u64 data) in xive_esb_write() argument
207 if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG) in xive_esb_write()
210 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw) in xive_esb_write()
211 xive_ops->esb_rw(xd->hw_irq, offset, data, 1); in xive_esb_write()
213 out_be64(xd->eoi_mmio + offset, data); in xive_esb_write()
275 DBG_VERBOSE("get_irq: got irq 0x%x, new pending=0x%02x\n", in xive_get_irq()
280 return 0; in xive_get_irq()
296 if (xive_scan_interrupts(xc, true) != 0) { in xive_do_queue_eoi()
297 DBG_VERBOSE("eoi: pending=0x%02x\n", xc->pending_prio); in xive_do_queue_eoi()
306 void xive_do_source_eoi(u32 hw_irq, struct xive_irq_data *xd) in xive_do_source_eoi() argument
309 if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI) in xive_do_source_eoi()
310 xive_esb_write(xd, XIVE_ESB_STORE_EOI, 0); in xive_do_source_eoi()
311 else if (hw_irq && xd->flags & XIVE_IRQ_FLAG_EOI_FW) { in xive_do_source_eoi()
316 * on P9 DD1.0 needed a latch to be clared in the LPC bridge in xive_do_source_eoi()
338 if (xd->flags & XIVE_IRQ_FLAG_LSI) in xive_do_source_eoi()
339 xive_esb_read(xd, XIVE_ESB_LOAD_EOI); in xive_do_source_eoi()
341 eoi_val = xive_esb_read(xd, XIVE_ESB_SET_PQ_00); in xive_do_source_eoi()
345 if ((eoi_val & XIVE_ESB_VAL_Q) && xd->trig_mmio) in xive_do_source_eoi()
346 out_be64(xd->trig_mmio, 0); in xive_do_source_eoi()
354 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); in xive_irq_eoi() local
357 DBG_VERBOSE("eoi_irq: irq=%d [0x%lx] pending=%02x\n", in xive_irq_eoi()
365 !(xd->flags & XIVE_IRQ_NO_EOI)) in xive_irq_eoi()
366 xive_do_source_eoi(irqd_to_hwirq(d), xd); in xive_irq_eoi()
372 xd->saved_p = false; in xive_irq_eoi()
383 static void xive_do_source_set_mask(struct xive_irq_data *xd, in xive_do_source_set_mask() argument
397 val = xive_esb_read(xd, XIVE_ESB_SET_PQ_01); in xive_do_source_set_mask()
398 xd->saved_p = !!(val & XIVE_ESB_VAL_P); in xive_do_source_set_mask()
399 } else if (xd->saved_p) in xive_do_source_set_mask()
400 xive_esb_read(xd, XIVE_ESB_SET_PQ_10); in xive_do_source_set_mask()
402 xive_esb_read(xd, XIVE_ESB_SET_PQ_00); in xive_do_source_set_mask()
439 if (unlikely(WARN_ON(cpu < 0 || !xc))) { in xive_dec_target_count()
466 for (i = 0; i < first && cpu < nr_cpu_ids; i++) in xive_find_target_in_mask()
505 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); in xive_pick_irq_target() local
513 if (xd->src_chip != XIVE_INVALID_CHIP_ID && in xive_pick_irq_target()
518 if (xc->chip_id == xd->src_chip) in xive_pick_irq_target()
527 if (cpu >= 0) in xive_pick_irq_target()
538 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); in xive_irq_startup() local
542 pr_devel("xive_irq_startup: irq %d [0x%x] data @%p\n", in xive_irq_startup()
570 xd->target = target; in xive_irq_startup()
583 xive_do_source_set_mask(xd, false); in xive_irq_startup()
585 return 0; in xive_irq_startup()
590 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); in xive_irq_shutdown() local
593 pr_devel("xive_irq_shutdown: irq %d [0x%x] data @%p\n", in xive_irq_shutdown()
596 if (WARN_ON(xd->target == XIVE_INVALID_TARGET)) in xive_irq_shutdown()
600 xive_do_source_set_mask(xd, true); in xive_irq_shutdown()
610 xd->saved_p = false; in xive_irq_shutdown()
617 get_hard_smp_processor_id(xd->target), in xive_irq_shutdown()
618 0xff, XIVE_BAD_IRQ); in xive_irq_shutdown()
620 xive_dec_target_count(xd->target); in xive_irq_shutdown()
621 xd->target = XIVE_INVALID_TARGET; in xive_irq_shutdown()
626 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); in xive_irq_unmask() local
628 pr_devel("xive_irq_unmask: irq %d data @%p\n", d->irq, xd); in xive_irq_unmask()
633 * be fixed by P9 DD2.0, if that is the case, firmware in xive_irq_unmask()
636 if (xd->flags & XIVE_IRQ_FLAG_MASK_FW) { in xive_irq_unmask()
639 get_hard_smp_processor_id(xd->target), in xive_irq_unmask()
644 xive_do_source_set_mask(xd, false); in xive_irq_unmask()
649 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); in xive_irq_mask() local
651 pr_devel("xive_irq_mask: irq %d data @%p\n", d->irq, xd); in xive_irq_mask()
656 * be fixed by P9 DD2.0, if that is the case, firmware in xive_irq_mask()
659 if (xd->flags & XIVE_IRQ_FLAG_MASK_FW) { in xive_irq_mask()
662 get_hard_smp_processor_id(xd->target), in xive_irq_mask()
663 0xff, d->irq); in xive_irq_mask()
667 xive_do_source_set_mask(xd, true); in xive_irq_mask()
674 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); in xive_irq_set_affinity() local
677 int rc = 0; in xive_irq_set_affinity()
693 if (xd->target != XIVE_INVALID_TARGET && in xive_irq_set_affinity()
694 cpu_online(xd->target) && in xive_irq_set_affinity()
695 cpumask_test_cpu(xd->target, cpumask)) in xive_irq_set_affinity()
709 old_target = xd->target; in xive_irq_set_affinity()
719 if (rc < 0) { in xive_irq_set_affinity()
724 pr_devel(" target: 0x%x\n", target); in xive_irq_set_affinity()
725 xd->target = target; in xive_irq_set_affinity()
736 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); in xive_irq_set_type() local
763 !!(xd->flags & XIVE_IRQ_FLAG_LSI)) { in xive_irq_set_type()
764 pr_warn("Interrupt %d (HW 0x%x) type mismatch, Linux says %s, FW says %s\n", in xive_irq_set_type()
767 (xd->flags & XIVE_IRQ_FLAG_LSI) ? "Level" : "Edge"); in xive_irq_set_type()
775 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); in xive_irq_retrigger() local
778 if (WARN_ON(xd->flags & XIVE_IRQ_FLAG_LSI)) in xive_irq_retrigger()
779 return 0; in xive_irq_retrigger()
785 xive_esb_read(xd, XIVE_ESB_SET_PQ_11); in xive_irq_retrigger()
788 * Note: We pass "0" to the hw_irq argument in order to in xive_irq_retrigger()
793 xive_do_source_eoi(0, xd); in xive_irq_retrigger()
800 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d); in xive_irq_set_vcpu_affinity() local
809 if (xd->flags & XIVE_IRQ_FLAG_MASK_FW) in xive_irq_set_vcpu_affinity()
820 pq = xive_esb_read(xd, XIVE_ESB_SET_PQ_10); in xive_irq_set_vcpu_affinity()
823 if (xd->target == XIVE_INVALID_TARGET) { in xive_irq_set_vcpu_affinity()
830 return 0; in xive_irq_set_vcpu_affinity()
849 pq = xive_esb_read(xd, XIVE_ESB_SET_PQ_11); in xive_irq_set_vcpu_affinity()
850 xd->saved_p = true; in xive_irq_set_vcpu_affinity()
864 xd->saved_p = false; in xive_irq_set_vcpu_affinity()
869 if (xd->target == XIVE_INVALID_TARGET) { in xive_irq_set_vcpu_affinity()
870 xive_do_source_set_mask(xd, true); in xive_irq_set_vcpu_affinity()
871 return 0; in xive_irq_set_vcpu_affinity()
891 get_hard_smp_processor_id(xd->target), in xive_irq_set_vcpu_affinity()
908 if (!xd->saved_p) in xive_irq_set_vcpu_affinity()
909 xive_do_source_eoi(hw_irq, xd); in xive_irq_set_vcpu_affinity()
912 return 0; in xive_irq_set_vcpu_affinity()
934 void xive_cleanup_irq_data(struct xive_irq_data *xd) in xive_cleanup_irq_data() argument
936 if (xd->eoi_mmio) { in xive_cleanup_irq_data()
937 unmap_kernel_range((unsigned long)xd->eoi_mmio, in xive_cleanup_irq_data()
938 1u << xd->esb_shift); in xive_cleanup_irq_data()
939 iounmap(xd->eoi_mmio); in xive_cleanup_irq_data()
940 if (xd->eoi_mmio == xd->trig_mmio) in xive_cleanup_irq_data()
941 xd->trig_mmio = NULL; in xive_cleanup_irq_data()
942 xd->eoi_mmio = NULL; in xive_cleanup_irq_data()
944 if (xd->trig_mmio) { in xive_cleanup_irq_data()
945 unmap_kernel_range((unsigned long)xd->trig_mmio, in xive_cleanup_irq_data()
946 1u << xd->esb_shift); in xive_cleanup_irq_data()
947 iounmap(xd->trig_mmio); in xive_cleanup_irq_data()
948 xd->trig_mmio = NULL; in xive_cleanup_irq_data()
955 struct xive_irq_data *xd; in xive_irq_alloc_data() local
958 xd = kzalloc(sizeof(struct xive_irq_data), GFP_KERNEL); in xive_irq_alloc_data()
959 if (!xd) in xive_irq_alloc_data()
961 rc = xive_ops->populate_irq_data(hw, xd); in xive_irq_alloc_data()
963 kfree(xd); in xive_irq_alloc_data()
966 xd->target = XIVE_INVALID_TARGET; in xive_irq_alloc_data()
967 irq_set_handler_data(virq, xd); in xive_irq_alloc_data()
976 xive_esb_read(xd, XIVE_ESB_SET_PQ_01); in xive_irq_alloc_data()
978 return 0; in xive_irq_alloc_data()
983 struct xive_irq_data *xd = irq_get_handler_data(virq); in xive_irq_free_data() local
985 if (!xd) in xive_irq_free_data()
988 xive_cleanup_irq_data(xd); in xive_irq_free_data()
989 kfree(xd); in xive_irq_free_data()
997 struct xive_irq_data *xd; in xive_cause_ipi() local
1001 DBG_VERBOSE("IPI CPU %d -> %d (HW IRQ 0x%x)\n", in xive_cause_ipi()
1004 xd = &xc->ipi_data; in xive_cause_ipi()
1005 if (WARN_ON(!xd->trig_mmio)) in xive_cause_ipi()
1007 out_be64(xd->trig_mmio, 0); in xive_cause_ipi()
1023 DBG_VERBOSE("IPI eoi: irq=%d [0x%lx] (HW IRQ 0x%x) pending=%02x\n", in xive_ipi_eoi()
1058 virq = irq_create_mapping(xive_irq_domain, 0); in xive_request_ipi()
1076 return 0; in xive_setup_cpu_ipi()
1104 return 0; in xive_setup_cpu_ipi()
1126 0xff, xive_ipi_irq); in xive_cleanup_cpu_ipi()
1157 /* IPIs are special and come up with HW number 0 */ in xive_irq_domain_map()
1158 if (hw == 0) { in xive_irq_domain_map()
1165 return 0; in xive_irq_domain_map()
1175 return 0; in xive_irq_domain_map()
1196 *out_hwirq = intspec[0]; in xive_irq_domain_xlate()
1210 return 0; in xive_irq_domain_xlate()
1243 int rc = 0; in xive_setup_cpu_queues()
1285 /* Set CPPR to 0xff to enable flow of interrupts */ in xive_setup_cpu()
1286 xc->cppr = 0xff; in xive_setup_cpu()
1287 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff); in xive_setup_cpu()
1323 while ((irq = xive_scan_interrupts(xc, false)) != 0) { in xive_flush_cpu_queue()
1330 struct xive_irq_data *xd; in xive_flush_cpu_queue() local
1337 if (d->domain != xive_irq_domain || hw_irq == 0) in xive_flush_cpu_queue()
1350 xd = irq_desc_get_handler_data(desc); in xive_flush_cpu_queue()
1356 if (xd->flags & XIVE_IRQ_FLAG_LSI) in xive_flush_cpu_queue()
1357 xive_do_source_eoi(irqd_to_hwirq(d), xd); in xive_flush_cpu_queue()
1373 /* Set CPPR to 0 to disable flow of interrupts */ in xive_smp_disable_cpu()
1374 xc->cppr = 0; in xive_smp_disable_cpu()
1375 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0); in xive_smp_disable_cpu()
1381 xc->cppr = 0xff; in xive_smp_disable_cpu()
1382 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff); in xive_smp_disable_cpu()
1403 /* Set CPPR to 0 to disable flow of interrupts */ in xive_teardown_cpu()
1404 xc->cppr = 0; in xive_teardown_cpu()
1405 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0); in xive_teardown_cpu()
1464 memset(qpage, 0, 1 << queue_shift); in xive_queue_page_alloc()
1472 return 0; in xive_off()