Lines Matching +full:clock +full:- +full:presc
1 // SPDX-License-Identifier: GPL-2.0
14 * This driver is based on i2c-stm32f4.c
32 #include "i2c-stm32.h"
166 * struct stm32f7_i2c_spec - private i2c specification timing
175 * @l_min: Min low period of the SCL clock (ns)
176 * @h_min: Min high period of the SCL clock (ns)
192 * struct stm32f7_i2c_setup - private I2C timing setup parameters
195 * @clock_src: I2C clock source frequency (Hz)
198 * @dnf: Digital filter coefficient (0-16)
212 * struct stm32f7_i2c_timings - private I2C output parameters
214 * @presc: Prescaler value
222 u8 presc; member
230 * struct stm32f7_i2c_msg - client specific data
231 * @addr: 8-bit or 10-bit slave addr, including r/w bit
239 * SMBus block read and SMBus block write - block read process call protocols
242 * This buffer has to be 32-bit aligned to be compliant with memory address
258 * struct stm32f7_i2c_dev - private data of the controller
263 * @clk: hw i2c clock
264 * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+
305 * and Fast-mode Plus I2C-bus devices
365 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask); in stm32f7_i2c_disable_irq()
374 setup->clock_src); in stm32f7_i2c_compute_timing()
376 setup->speed_freq); in stm32f7_i2c_compute_timing()
389 if (setup->speed >= STM32_I2C_SPEED_END) { in stm32f7_i2c_compute_timing()
390 dev_err(i2c_dev->dev, "speed out of bound {%d/%d}\n", in stm32f7_i2c_compute_timing()
391 setup->speed, STM32_I2C_SPEED_END - 1); in stm32f7_i2c_compute_timing()
392 return -EINVAL; in stm32f7_i2c_compute_timing()
395 if ((setup->rise_time > i2c_specs[setup->speed].rise_max) || in stm32f7_i2c_compute_timing()
396 (setup->fall_time > i2c_specs[setup->speed].fall_max)) { in stm32f7_i2c_compute_timing()
397 dev_err(i2c_dev->dev, in stm32f7_i2c_compute_timing()
399 setup->rise_time, i2c_specs[setup->speed].rise_max, in stm32f7_i2c_compute_timing()
400 setup->fall_time, i2c_specs[setup->speed].fall_max); in stm32f7_i2c_compute_timing()
401 return -EINVAL; in stm32f7_i2c_compute_timing()
404 if (setup->dnf > STM32F7_I2C_DNF_MAX) { in stm32f7_i2c_compute_timing()
405 dev_err(i2c_dev->dev, in stm32f7_i2c_compute_timing()
407 setup->dnf, STM32F7_I2C_DNF_MAX); in stm32f7_i2c_compute_timing()
408 return -EINVAL; in stm32f7_i2c_compute_timing()
411 if (setup->speed_freq > i2c_specs[setup->speed].rate) { in stm32f7_i2c_compute_timing()
412 dev_err(i2c_dev->dev, "ERROR: Freq {%d/%d}\n", in stm32f7_i2c_compute_timing()
413 setup->speed_freq, i2c_specs[setup->speed].rate); in stm32f7_i2c_compute_timing()
414 return -EINVAL; in stm32f7_i2c_compute_timing()
419 (setup->analog_filter ? in stm32f7_i2c_compute_timing()
422 (setup->analog_filter ? in stm32f7_i2c_compute_timing()
424 dnf_delay = setup->dnf * i2cclk; in stm32f7_i2c_compute_timing()
426 sdadel_min = i2c_specs[setup->speed].hddat_min + setup->fall_time - in stm32f7_i2c_compute_timing()
427 af_delay_min - (setup->dnf + 3) * i2cclk; in stm32f7_i2c_compute_timing()
429 sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time - in stm32f7_i2c_compute_timing()
430 af_delay_max - (setup->dnf + 4) * i2cclk; in stm32f7_i2c_compute_timing()
432 scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min; in stm32f7_i2c_compute_timing()
439 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", in stm32f7_i2c_compute_timing()
443 /* Compute possible values for PRESC, SCLDEL and SDADEL */ in stm32f7_i2c_compute_timing()
459 ret = -ENOMEM; in stm32f7_i2c_compute_timing()
463 v->presc = p; in stm32f7_i2c_compute_timing()
464 v->scldel = l; in stm32f7_i2c_compute_timing()
465 v->sdadel = a; in stm32f7_i2c_compute_timing()
468 list_add_tail(&v->node, in stm32f7_i2c_compute_timing()
476 dev_err(i2c_dev->dev, "no Prescaler solution\n"); in stm32f7_i2c_compute_timing()
477 ret = -EPERM; in stm32f7_i2c_compute_timing()
483 clk_max = NSEC_PER_SEC / i2c_specs[setup->speed].rate_min; in stm32f7_i2c_compute_timing()
484 clk_min = NSEC_PER_SEC / i2c_specs[setup->speed].rate_max; in stm32f7_i2c_compute_timing()
489 * - SCL Low Period has to be higher than SCL Clock Low Period in stm32f7_i2c_compute_timing()
490 * defined by I2C Specification. I2C Clock has to be lower than in stm32f7_i2c_compute_timing()
491 * (SCL Low Period - Analog/Digital filters) / 4. in stm32f7_i2c_compute_timing()
492 * - SCL High Period has to be lower than SCL Clock High Period in stm32f7_i2c_compute_timing()
494 * - I2C Clock has to be lower than SCL High Period in stm32f7_i2c_compute_timing()
497 u32 prescaler = (v->presc + 1) * i2cclk; in stm32f7_i2c_compute_timing()
502 if ((tscl_l < i2c_specs[setup->speed].l_min) || in stm32f7_i2c_compute_timing()
504 ((tscl_l - af_delay_min - dnf_delay) / 4))) { in stm32f7_i2c_compute_timing()
511 setup->rise_time + setup->fall_time; in stm32f7_i2c_compute_timing()
514 (tscl_h >= i2c_specs[setup->speed].h_min) && in stm32f7_i2c_compute_timing()
516 int clk_error = tscl - i2cbus; in stm32f7_i2c_compute_timing()
519 clk_error = -clk_error; in stm32f7_i2c_compute_timing()
523 v->scll = l; in stm32f7_i2c_compute_timing()
524 v->sclh = h; in stm32f7_i2c_compute_timing()
533 dev_err(i2c_dev->dev, "no solution at all\n"); in stm32f7_i2c_compute_timing()
534 ret = -EPERM; in stm32f7_i2c_compute_timing()
538 output->presc = s->presc; in stm32f7_i2c_compute_timing()
539 output->scldel = s->scldel; in stm32f7_i2c_compute_timing()
540 output->sdadel = s->sdadel; in stm32f7_i2c_compute_timing()
541 output->scll = s->scll; in stm32f7_i2c_compute_timing()
542 output->sclh = s->sclh; in stm32f7_i2c_compute_timing()
544 dev_dbg(i2c_dev->dev, in stm32f7_i2c_compute_timing()
545 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n", in stm32f7_i2c_compute_timing()
546 output->presc, in stm32f7_i2c_compute_timing()
547 output->scldel, output->sdadel, in stm32f7_i2c_compute_timing()
548 output->scll, output->sclh); in stm32f7_i2c_compute_timing()
553 list_del(&v->node); in stm32f7_i2c_compute_timing()
565 setup->speed = i2c_dev->speed; in stm32f7_i2c_setup_timing()
566 setup->speed_freq = i2c_specs[setup->speed].rate; in stm32f7_i2c_setup_timing()
567 setup->clock_src = clk_get_rate(i2c_dev->clk); in stm32f7_i2c_setup_timing()
569 if (!setup->clock_src) { in stm32f7_i2c_setup_timing()
570 dev_err(i2c_dev->dev, "clock rate is 0\n"); in stm32f7_i2c_setup_timing()
571 return -EINVAL; in stm32f7_i2c_setup_timing()
576 &i2c_dev->timing); in stm32f7_i2c_setup_timing()
578 dev_err(i2c_dev->dev, in stm32f7_i2c_setup_timing()
580 if (i2c_dev->speed > STM32_I2C_SPEED_STANDARD) { in stm32f7_i2c_setup_timing()
581 i2c_dev->speed--; in stm32f7_i2c_setup_timing()
582 setup->speed = i2c_dev->speed; in stm32f7_i2c_setup_timing()
583 setup->speed_freq = in stm32f7_i2c_setup_timing()
584 i2c_specs[setup->speed].rate; in stm32f7_i2c_setup_timing()
585 dev_warn(i2c_dev->dev, in stm32f7_i2c_setup_timing()
587 i2c_specs[setup->speed].rate); in stm32f7_i2c_setup_timing()
595 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n"); in stm32f7_i2c_setup_timing()
599 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Freq(%i), Clk Source(%i)\n", in stm32f7_i2c_setup_timing()
600 setup->speed, setup->speed_freq, setup->clock_src); in stm32f7_i2c_setup_timing()
601 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n", in stm32f7_i2c_setup_timing()
602 setup->rise_time, setup->fall_time); in stm32f7_i2c_setup_timing()
603 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n", in stm32f7_i2c_setup_timing()
604 (setup->analog_filter ? "On" : "Off"), setup->dnf); in stm32f7_i2c_setup_timing()
611 void __iomem *base = i2c_dev->base; in stm32f7_i2c_disable_dma_req()
620 struct stm32_i2c_dma *dma = i2c_dev->dma; in stm32f7_i2c_dma_callback()
621 struct device *dev = dma->chan_using->device->dev; in stm32f7_i2c_dma_callback()
624 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir); in stm32f7_i2c_dma_callback()
625 complete(&dma->dma_complete); in stm32f7_i2c_dma_callback()
630 struct stm32f7_i2c_timings *t = &i2c_dev->timing; in stm32f7_i2c_hw_config()
634 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc); in stm32f7_i2c_hw_config()
635 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel); in stm32f7_i2c_hw_config()
636 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel); in stm32f7_i2c_hw_config()
637 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh); in stm32f7_i2c_hw_config()
638 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll); in stm32f7_i2c_hw_config()
639 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR); in stm32f7_i2c_hw_config()
642 if (i2c_dev->setup.analog_filter) in stm32f7_i2c_hw_config()
643 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_hw_config()
646 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_hw_config()
648 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_hw_config()
654 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_write_tx_data()
655 void __iomem *base = i2c_dev->base; in stm32f7_i2c_write_tx_data()
657 if (f7_msg->count) { in stm32f7_i2c_write_tx_data()
658 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR); in stm32f7_i2c_write_tx_data()
659 f7_msg->count--; in stm32f7_i2c_write_tx_data()
665 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_read_rx_data()
666 void __iomem *base = i2c_dev->base; in stm32f7_i2c_read_rx_data()
668 if (f7_msg->count) { in stm32f7_i2c_read_rx_data()
669 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR); in stm32f7_i2c_read_rx_data()
670 f7_msg->count--; in stm32f7_i2c_read_rx_data()
679 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_reload()
682 if (i2c_dev->use_dma) in stm32f7_i2c_reload()
683 f7_msg->count -= STM32F7_I2C_MAX_LEN; in stm32f7_i2c_reload()
685 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_reload()
688 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { in stm32f7_i2c_reload()
692 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); in stm32f7_i2c_reload()
695 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_reload()
700 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_smbus_reload()
713 val = f7_msg->buf - sizeof(u8); in stm32f7_i2c_smbus_reload()
714 f7_msg->count = *val; in stm32f7_i2c_smbus_reload()
715 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_smbus_reload()
717 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); in stm32f7_i2c_smbus_reload()
718 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_smbus_reload()
725 dev_info(i2c_dev->dev, "Trying to recover bus\n"); in stm32f7_i2c_release_bus()
727 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, in stm32f7_i2c_release_bus()
740 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR, in stm32f7_i2c_wait_free_bus()
747 dev_info(i2c_dev->dev, "bus busy\n"); in stm32f7_i2c_wait_free_bus()
749 ret = stm32f7_i2c_release_bus(&i2c_dev->adap); in stm32f7_i2c_wait_free_bus()
751 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret); in stm32f7_i2c_wait_free_bus()
755 return -EBUSY; in stm32f7_i2c_wait_free_bus()
761 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_xfer_msg()
762 void __iomem *base = i2c_dev->base; in stm32f7_i2c_xfer_msg()
766 f7_msg->addr = msg->addr; in stm32f7_i2c_xfer_msg()
767 f7_msg->buf = msg->buf; in stm32f7_i2c_xfer_msg()
768 f7_msg->count = msg->len; in stm32f7_i2c_xfer_msg()
769 f7_msg->result = 0; in stm32f7_i2c_xfer_msg()
770 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1); in stm32f7_i2c_xfer_msg()
772 reinit_completion(&i2c_dev->complete); in stm32f7_i2c_xfer_msg()
779 if (msg->flags & I2C_M_RD) in stm32f7_i2c_xfer_msg()
784 if (msg->flags & I2C_M_TEN) { in stm32f7_i2c_xfer_msg()
786 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr); in stm32f7_i2c_xfer_msg()
790 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); in stm32f7_i2c_xfer_msg()
795 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { in stm32f7_i2c_xfer_msg()
799 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); in stm32f7_i2c_xfer_msg()
811 i2c_dev->use_dma = false; in stm32f7_i2c_xfer_msg()
812 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) { in stm32f7_i2c_xfer_msg()
813 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, in stm32f7_i2c_xfer_msg()
814 msg->flags & I2C_M_RD, in stm32f7_i2c_xfer_msg()
815 f7_msg->count, f7_msg->buf, in stm32f7_i2c_xfer_msg()
819 i2c_dev->use_dma = true; in stm32f7_i2c_xfer_msg()
821 dev_warn(i2c_dev->dev, "can't use DMA\n"); in stm32f7_i2c_xfer_msg()
824 if (!i2c_dev->use_dma) { in stm32f7_i2c_xfer_msg()
825 if (msg->flags & I2C_M_RD) in stm32f7_i2c_xfer_msg()
830 if (msg->flags & I2C_M_RD) in stm32f7_i2c_xfer_msg()
839 i2c_dev->master_mode = true; in stm32f7_i2c_xfer_msg()
850 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_smbus_xfer_msg()
851 struct device *dev = i2c_dev->dev; in stm32f7_i2c_smbus_xfer_msg()
852 void __iomem *base = i2c_dev->base; in stm32f7_i2c_smbus_xfer_msg()
856 f7_msg->result = 0; in stm32f7_i2c_smbus_xfer_msg()
857 reinit_completion(&i2c_dev->complete); in stm32f7_i2c_smbus_xfer_msg()
864 if (f7_msg->read_write) in stm32f7_i2c_smbus_xfer_msg()
869 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); in stm32f7_i2c_smbus_xfer_msg()
871 f7_msg->smbus_buf[0] = command; in stm32f7_i2c_smbus_xfer_msg()
872 switch (f7_msg->size) { in stm32f7_i2c_smbus_xfer_msg()
874 f7_msg->stop = true; in stm32f7_i2c_smbus_xfer_msg()
875 f7_msg->count = 0; in stm32f7_i2c_smbus_xfer_msg()
878 f7_msg->stop = true; in stm32f7_i2c_smbus_xfer_msg()
879 f7_msg->count = 1; in stm32f7_i2c_smbus_xfer_msg()
882 if (f7_msg->read_write) { in stm32f7_i2c_smbus_xfer_msg()
883 f7_msg->stop = false; in stm32f7_i2c_smbus_xfer_msg()
884 f7_msg->count = 1; in stm32f7_i2c_smbus_xfer_msg()
887 f7_msg->stop = true; in stm32f7_i2c_smbus_xfer_msg()
888 f7_msg->count = 2; in stm32f7_i2c_smbus_xfer_msg()
889 f7_msg->smbus_buf[1] = data->byte; in stm32f7_i2c_smbus_xfer_msg()
893 if (f7_msg->read_write) { in stm32f7_i2c_smbus_xfer_msg()
894 f7_msg->stop = false; in stm32f7_i2c_smbus_xfer_msg()
895 f7_msg->count = 1; in stm32f7_i2c_smbus_xfer_msg()
898 f7_msg->stop = true; in stm32f7_i2c_smbus_xfer_msg()
899 f7_msg->count = 3; in stm32f7_i2c_smbus_xfer_msg()
900 f7_msg->smbus_buf[1] = data->word & 0xff; in stm32f7_i2c_smbus_xfer_msg()
901 f7_msg->smbus_buf[2] = data->word >> 8; in stm32f7_i2c_smbus_xfer_msg()
905 if (f7_msg->read_write) { in stm32f7_i2c_smbus_xfer_msg()
906 f7_msg->stop = false; in stm32f7_i2c_smbus_xfer_msg()
907 f7_msg->count = 1; in stm32f7_i2c_smbus_xfer_msg()
910 f7_msg->stop = true; in stm32f7_i2c_smbus_xfer_msg()
911 if (data->block[0] > I2C_SMBUS_BLOCK_MAX || in stm32f7_i2c_smbus_xfer_msg()
912 !data->block[0]) { in stm32f7_i2c_smbus_xfer_msg()
914 data->block[0]); in stm32f7_i2c_smbus_xfer_msg()
915 return -EINVAL; in stm32f7_i2c_smbus_xfer_msg()
917 f7_msg->count = data->block[0] + 2; in stm32f7_i2c_smbus_xfer_msg()
918 for (i = 1; i < f7_msg->count; i++) in stm32f7_i2c_smbus_xfer_msg()
919 f7_msg->smbus_buf[i] = data->block[i - 1]; in stm32f7_i2c_smbus_xfer_msg()
923 f7_msg->stop = false; in stm32f7_i2c_smbus_xfer_msg()
924 f7_msg->count = 3; in stm32f7_i2c_smbus_xfer_msg()
925 f7_msg->smbus_buf[1] = data->word & 0xff; in stm32f7_i2c_smbus_xfer_msg()
926 f7_msg->smbus_buf[2] = data->word >> 8; in stm32f7_i2c_smbus_xfer_msg()
928 f7_msg->read_write = I2C_SMBUS_READ; in stm32f7_i2c_smbus_xfer_msg()
931 f7_msg->stop = false; in stm32f7_i2c_smbus_xfer_msg()
932 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) { in stm32f7_i2c_smbus_xfer_msg()
934 data->block[0]); in stm32f7_i2c_smbus_xfer_msg()
935 return -EINVAL; in stm32f7_i2c_smbus_xfer_msg()
937 f7_msg->count = data->block[0] + 2; in stm32f7_i2c_smbus_xfer_msg()
938 for (i = 1; i < f7_msg->count; i++) in stm32f7_i2c_smbus_xfer_msg()
939 f7_msg->smbus_buf[i] = data->block[i - 1]; in stm32f7_i2c_smbus_xfer_msg()
941 f7_msg->read_write = I2C_SMBUS_READ; in stm32f7_i2c_smbus_xfer_msg()
944 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size); in stm32f7_i2c_smbus_xfer_msg()
945 return -EOPNOTSUPP; in stm32f7_i2c_smbus_xfer_msg()
948 f7_msg->buf = f7_msg->smbus_buf; in stm32f7_i2c_smbus_xfer_msg()
951 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) { in stm32f7_i2c_smbus_xfer_msg()
954 if (!f7_msg->read_write) in stm32f7_i2c_smbus_xfer_msg()
955 f7_msg->count++; in stm32f7_i2c_smbus_xfer_msg()
963 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); in stm32f7_i2c_smbus_xfer_msg()
974 i2c_dev->use_dma = false; in stm32f7_i2c_smbus_xfer_msg()
975 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) { in stm32f7_i2c_smbus_xfer_msg()
976 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, in stm32f7_i2c_smbus_xfer_msg()
978 f7_msg->count, f7_msg->buf, in stm32f7_i2c_smbus_xfer_msg()
982 i2c_dev->use_dma = true; in stm32f7_i2c_smbus_xfer_msg()
984 dev_warn(i2c_dev->dev, "can't use DMA\n"); in stm32f7_i2c_smbus_xfer_msg()
987 if (!i2c_dev->use_dma) { in stm32f7_i2c_smbus_xfer_msg()
1002 i2c_dev->master_mode = true; in stm32f7_i2c_smbus_xfer_msg()
1013 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_smbus_rep_start()
1014 void __iomem *base = i2c_dev->base; in stm32f7_i2c_smbus_rep_start()
1024 switch (f7_msg->size) { in stm32f7_i2c_smbus_rep_start()
1026 f7_msg->count = 1; in stm32f7_i2c_smbus_rep_start()
1030 f7_msg->count = 2; in stm32f7_i2c_smbus_rep_start()
1034 f7_msg->count = 1; in stm32f7_i2c_smbus_rep_start()
1039 f7_msg->buf = f7_msg->smbus_buf; in stm32f7_i2c_smbus_rep_start()
1040 f7_msg->stop = true; in stm32f7_i2c_smbus_rep_start()
1044 f7_msg->count++; in stm32f7_i2c_smbus_rep_start()
1048 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); in stm32f7_i2c_smbus_rep_start()
1064 i2c_dev->use_dma = false; in stm32f7_i2c_smbus_rep_start()
1065 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN && in stm32f7_i2c_smbus_rep_start()
1066 f7_msg->size != I2C_SMBUS_BLOCK_DATA && in stm32f7_i2c_smbus_rep_start()
1067 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) { in stm32f7_i2c_smbus_rep_start()
1068 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, in stm32f7_i2c_smbus_rep_start()
1070 f7_msg->count, f7_msg->buf, in stm32f7_i2c_smbus_rep_start()
1075 i2c_dev->use_dma = true; in stm32f7_i2c_smbus_rep_start()
1077 dev_warn(i2c_dev->dev, "can't use DMA\n"); in stm32f7_i2c_smbus_rep_start()
1080 if (!i2c_dev->use_dma) in stm32f7_i2c_smbus_rep_start()
1095 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_smbus_check_pec()
1098 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR); in stm32f7_i2c_smbus_check_pec()
1100 switch (f7_msg->size) { in stm32f7_i2c_smbus_check_pec()
1103 received_pec = f7_msg->smbus_buf[1]; in stm32f7_i2c_smbus_check_pec()
1107 received_pec = f7_msg->smbus_buf[2]; in stm32f7_i2c_smbus_check_pec()
1111 count = f7_msg->smbus_buf[0]; in stm32f7_i2c_smbus_check_pec()
1112 received_pec = f7_msg->smbus_buf[count]; in stm32f7_i2c_smbus_check_pec()
1115 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n"); in stm32f7_i2c_smbus_check_pec()
1116 return -EINVAL; in stm32f7_i2c_smbus_check_pec()
1120 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n", in stm32f7_i2c_smbus_check_pec()
1122 return -EBADMSG; in stm32f7_i2c_smbus_check_pec()
1135 if (slave->flags & I2C_CLIENT_TEN) { in stm32f7_i2c_is_addr_match()
1137 * For 10-bit addr, addcode = 11110XY with in stm32f7_i2c_is_addr_match()
1141 addr = slave->addr >> 8; in stm32f7_i2c_is_addr_match()
1146 addr = slave->addr & 0x7f; in stm32f7_i2c_is_addr_match()
1156 struct i2c_client *slave = i2c_dev->slave_running; in stm32f7_i2c_slave_start()
1157 void __iomem *base = i2c_dev->base; in stm32f7_i2c_slave_start()
1161 if (i2c_dev->slave_dir) { in stm32f7_i2c_slave_start()
1204 void __iomem *base = i2c_dev->base; in stm32f7_i2c_slave_addr()
1208 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); in stm32f7_i2c_slave_addr()
1213 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) { in stm32f7_i2c_slave_addr()
1214 i2c_dev->slave_running = i2c_dev->slave[i]; in stm32f7_i2c_slave_addr()
1215 i2c_dev->slave_dir = dir; in stm32f7_i2c_slave_addr()
1234 if (i2c_dev->slave[i] == slave) { in stm32f7_i2c_get_slave_id()
1240 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr); in stm32f7_i2c_get_slave_id()
1242 return -ENODEV; in stm32f7_i2c_get_slave_id()
1248 struct device *dev = i2c_dev->dev; in stm32f7_i2c_get_free_slave_id()
1252 * slave[0] supports 7-bit and 10-bit slave address in stm32f7_i2c_get_free_slave_id()
1253 * slave[1] supports 7-bit slave address only in stm32f7_i2c_get_free_slave_id()
1255 for (i = STM32F7_I2C_MAX_SLAVE - 1; i >= 0; i--) { in stm32f7_i2c_get_free_slave_id()
1256 if (i == 1 && (slave->flags & I2C_CLIENT_TEN)) in stm32f7_i2c_get_free_slave_id()
1258 if (!i2c_dev->slave[i]) { in stm32f7_i2c_get_free_slave_id()
1264 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr); in stm32f7_i2c_get_free_slave_id()
1266 return -EINVAL; in stm32f7_i2c_get_free_slave_id()
1274 if (i2c_dev->slave[i]) in stm32f7_i2c_is_slave_registered()
1287 if (i2c_dev->slave[i]) in stm32f7_i2c_is_slave_busy()
1296 void __iomem *base = i2c_dev->base; in stm32f7_i2c_slave_isr_event()
1301 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); in stm32f7_i2c_slave_isr_event()
1305 i2c_slave_event(i2c_dev->slave_running, in stm32f7_i2c_slave_isr_event()
1319 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR); in stm32f7_i2c_slave_isr_event()
1320 ret = i2c_slave_event(i2c_dev->slave_running, in stm32f7_i2c_slave_isr_event()
1324 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_slave_isr_event()
1326 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); in stm32f7_i2c_slave_isr_event()
1335 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__); in stm32f7_i2c_slave_isr_event()
1344 if (i2c_dev->slave_dir) { in stm32f7_i2c_slave_isr_event()
1357 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val); in stm32f7_i2c_slave_isr_event()
1359 i2c_dev->slave_running = NULL; in stm32f7_i2c_slave_isr_event()
1372 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_isr_event()
1373 void __iomem *base = i2c_dev->base; in stm32f7_i2c_isr_event()
1378 if (!i2c_dev->master_mode) { in stm32f7_i2c_isr_event()
1383 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); in stm32f7_i2c_isr_event()
1395 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__); in stm32f7_i2c_isr_event()
1397 f7_msg->result = -ENXIO; in stm32f7_i2c_isr_event()
1412 if (i2c_dev->use_dma) { in stm32f7_i2c_isr_event()
1415 i2c_dev->master_mode = false; in stm32f7_i2c_isr_event()
1416 complete(&i2c_dev->complete); in stm32f7_i2c_isr_event()
1422 if (f7_msg->stop) { in stm32f7_i2c_isr_event()
1425 } else if (i2c_dev->use_dma) { in stm32f7_i2c_isr_event()
1427 } else if (f7_msg->smbus) { in stm32f7_i2c_isr_event()
1430 i2c_dev->msg_id++; in stm32f7_i2c_isr_event()
1431 i2c_dev->msg++; in stm32f7_i2c_isr_event()
1432 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); in stm32f7_i2c_isr_event()
1437 if (f7_msg->smbus) in stm32f7_i2c_isr_event()
1449 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_isr_event_thread()
1450 struct stm32_i2c_dma *dma = i2c_dev->dma; in stm32f7_i2c_isr_event_thread()
1458 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ); in stm32f7_i2c_isr_event_thread()
1460 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__); in stm32f7_i2c_isr_event_thread()
1462 dmaengine_terminate_all(dma->chan_using); in stm32f7_i2c_isr_event_thread()
1463 f7_msg->result = -ETIMEDOUT; in stm32f7_i2c_isr_event_thread()
1466 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); in stm32f7_i2c_isr_event_thread()
1469 if (f7_msg->smbus) { in stm32f7_i2c_isr_event_thread()
1472 i2c_dev->msg_id++; in stm32f7_i2c_isr_event_thread()
1473 i2c_dev->msg++; in stm32f7_i2c_isr_event_thread()
1474 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); in stm32f7_i2c_isr_event_thread()
1477 i2c_dev->master_mode = false; in stm32f7_i2c_isr_event_thread()
1478 complete(&i2c_dev->complete); in stm32f7_i2c_isr_event_thread()
1487 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_isr_error()
1488 void __iomem *base = i2c_dev->base; in stm32f7_i2c_isr_error()
1489 struct device *dev = i2c_dev->dev; in stm32f7_i2c_isr_error()
1490 struct stm32_i2c_dma *dma = i2c_dev->dma; in stm32f7_i2c_isr_error()
1493 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); in stm32f7_i2c_isr_error()
1499 stm32f7_i2c_release_bus(&i2c_dev->adap); in stm32f7_i2c_isr_error()
1500 f7_msg->result = -EIO; in stm32f7_i2c_isr_error()
1507 f7_msg->result = -EAGAIN; in stm32f7_i2c_isr_error()
1513 f7_msg->result = -EINVAL; in stm32f7_i2c_isr_error()
1516 if (!i2c_dev->slave_running) { in stm32f7_i2c_isr_error()
1527 if (i2c_dev->use_dma) { in stm32f7_i2c_isr_error()
1529 dmaengine_terminate_all(dma->chan_using); in stm32f7_i2c_isr_error()
1532 i2c_dev->master_mode = false; in stm32f7_i2c_isr_error()
1533 complete(&i2c_dev->complete); in stm32f7_i2c_isr_error()
1542 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_xfer()
1543 struct stm32_i2c_dma *dma = i2c_dev->dma; in stm32f7_i2c_xfer()
1547 i2c_dev->msg = msgs; in stm32f7_i2c_xfer()
1548 i2c_dev->msg_num = num; in stm32f7_i2c_xfer()
1549 i2c_dev->msg_id = 0; in stm32f7_i2c_xfer()
1550 f7_msg->smbus = false; in stm32f7_i2c_xfer()
1552 ret = clk_enable(i2c_dev->clk); in stm32f7_i2c_xfer()
1554 dev_err(i2c_dev->dev, "Failed to enable clock\n"); in stm32f7_i2c_xfer()
1564 time_left = wait_for_completion_timeout(&i2c_dev->complete, in stm32f7_i2c_xfer()
1565 i2c_dev->adap.timeout); in stm32f7_i2c_xfer()
1566 ret = f7_msg->result; in stm32f7_i2c_xfer()
1569 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n", in stm32f7_i2c_xfer()
1570 i2c_dev->msg->addr); in stm32f7_i2c_xfer()
1571 if (i2c_dev->use_dma) in stm32f7_i2c_xfer()
1572 dmaengine_terminate_all(dma->chan_using); in stm32f7_i2c_xfer()
1573 ret = -ETIMEDOUT; in stm32f7_i2c_xfer()
1577 clk_disable(i2c_dev->clk); in stm32f7_i2c_xfer()
1588 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; in stm32f7_i2c_smbus_xfer()
1589 struct stm32_i2c_dma *dma = i2c_dev->dma; in stm32f7_i2c_smbus_xfer()
1590 struct device *dev = i2c_dev->dev; in stm32f7_i2c_smbus_xfer()
1594 f7_msg->addr = addr; in stm32f7_i2c_smbus_xfer()
1595 f7_msg->size = size; in stm32f7_i2c_smbus_xfer()
1596 f7_msg->read_write = read_write; in stm32f7_i2c_smbus_xfer()
1597 f7_msg->smbus = true; in stm32f7_i2c_smbus_xfer()
1599 ret = clk_enable(i2c_dev->clk); in stm32f7_i2c_smbus_xfer()
1601 dev_err(i2c_dev->dev, "Failed to enable clock\n"); in stm32f7_i2c_smbus_xfer()
1613 timeout = wait_for_completion_timeout(&i2c_dev->complete, in stm32f7_i2c_smbus_xfer()
1614 i2c_dev->adap.timeout); in stm32f7_i2c_smbus_xfer()
1615 ret = f7_msg->result; in stm32f7_i2c_smbus_xfer()
1620 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr); in stm32f7_i2c_smbus_xfer()
1621 if (i2c_dev->use_dma) in stm32f7_i2c_smbus_xfer()
1622 dmaengine_terminate_all(dma->chan_using); in stm32f7_i2c_smbus_xfer()
1623 ret = -ETIMEDOUT; in stm32f7_i2c_smbus_xfer()
1638 data->byte = f7_msg->smbus_buf[0]; in stm32f7_i2c_smbus_xfer()
1642 data->word = f7_msg->smbus_buf[0] | in stm32f7_i2c_smbus_xfer()
1643 (f7_msg->smbus_buf[1] << 8); in stm32f7_i2c_smbus_xfer()
1647 for (i = 0; i <= f7_msg->smbus_buf[0]; i++) in stm32f7_i2c_smbus_xfer()
1648 data->block[i] = f7_msg->smbus_buf[i]; in stm32f7_i2c_smbus_xfer()
1652 ret = -EINVAL; in stm32f7_i2c_smbus_xfer()
1657 clk_disable(i2c_dev->clk); in stm32f7_i2c_smbus_xfer()
1663 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); in stm32f7_i2c_reg_slave()
1664 void __iomem *base = i2c_dev->base; in stm32f7_i2c_reg_slave()
1665 struct device *dev = i2c_dev->dev; in stm32f7_i2c_reg_slave()
1669 if (slave->flags & I2C_CLIENT_PEC) { in stm32f7_i2c_reg_slave()
1671 return -EINVAL; in stm32f7_i2c_reg_slave()
1676 return -EBUSY; in stm32f7_i2c_reg_slave()
1684 ret = clk_enable(i2c_dev->clk); in stm32f7_i2c_reg_slave()
1686 dev_err(dev, "Failed to enable clock\n"); in stm32f7_i2c_reg_slave()
1693 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); in stm32f7_i2c_reg_slave()
1695 if (slave->flags & I2C_CLIENT_TEN) { in stm32f7_i2c_reg_slave()
1696 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr); in stm32f7_i2c_reg_slave()
1699 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr); in stm32f7_i2c_reg_slave()
1702 i2c_dev->slave[id] = slave; in stm32f7_i2c_reg_slave()
1703 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1); in stm32f7_i2c_reg_slave()
1706 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); in stm32f7_i2c_reg_slave()
1708 if (slave->flags & I2C_CLIENT_TEN) { in stm32f7_i2c_reg_slave()
1709 ret = -EOPNOTSUPP; in stm32f7_i2c_reg_slave()
1713 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr); in stm32f7_i2c_reg_slave()
1715 i2c_dev->slave[id] = slave; in stm32f7_i2c_reg_slave()
1716 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2); in stm32f7_i2c_reg_slave()
1718 ret = -ENODEV; in stm32f7_i2c_reg_slave()
1734 clk_disable(i2c_dev->clk); in stm32f7_i2c_reg_slave()
1741 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); in stm32f7_i2c_unreg_slave()
1742 void __iomem *base = i2c_dev->base; in stm32f7_i2c_unreg_slave()
1750 WARN_ON(!i2c_dev->slave[id]); in stm32f7_i2c_unreg_slave()
1760 i2c_dev->slave[id] = NULL; in stm32f7_i2c_unreg_slave()
1764 clk_disable(i2c_dev->clk); in stm32f7_i2c_unreg_slave()
1798 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); in stm32f7_i2c_probe()
1800 return -ENOMEM; in stm32f7_i2c_probe()
1803 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res); in stm32f7_i2c_probe()
1804 if (IS_ERR(i2c_dev->base)) in stm32f7_i2c_probe()
1805 return PTR_ERR(i2c_dev->base); in stm32f7_i2c_probe()
1806 phy_addr = (dma_addr_t)res->start; in stm32f7_i2c_probe()
1810 if (irq_event != -EPROBE_DEFER) in stm32f7_i2c_probe()
1811 dev_err(&pdev->dev, "Failed to get IRQ event: %d\n", in stm32f7_i2c_probe()
1813 return irq_event ? : -ENOENT; in stm32f7_i2c_probe()
1818 if (irq_error != -EPROBE_DEFER) in stm32f7_i2c_probe()
1819 dev_err(&pdev->dev, "Failed to get IRQ error: %d\n", in stm32f7_i2c_probe()
1821 return irq_error ? : -ENOENT; in stm32f7_i2c_probe()
1824 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL); in stm32f7_i2c_probe()
1825 if (IS_ERR(i2c_dev->clk)) { in stm32f7_i2c_probe()
1826 dev_err(&pdev->dev, "Error: Missing controller clock\n"); in stm32f7_i2c_probe()
1827 return PTR_ERR(i2c_dev->clk); in stm32f7_i2c_probe()
1829 ret = clk_prepare_enable(i2c_dev->clk); in stm32f7_i2c_probe()
1831 dev_err(&pdev->dev, "Failed to prepare_enable clock\n"); in stm32f7_i2c_probe()
1835 i2c_dev->speed = STM32_I2C_SPEED_STANDARD; in stm32f7_i2c_probe()
1836 ret = device_property_read_u32(&pdev->dev, "clock-frequency", in stm32f7_i2c_probe()
1839 i2c_dev->speed = STM32_I2C_SPEED_FAST_PLUS; in stm32f7_i2c_probe()
1841 i2c_dev->speed = STM32_I2C_SPEED_FAST; in stm32f7_i2c_probe()
1843 i2c_dev->speed = STM32_I2C_SPEED_STANDARD; in stm32f7_i2c_probe()
1845 rst = devm_reset_control_get(&pdev->dev, NULL); in stm32f7_i2c_probe()
1847 dev_err(&pdev->dev, "Error: Missing controller reset\n"); in stm32f7_i2c_probe()
1855 i2c_dev->dev = &pdev->dev; in stm32f7_i2c_probe()
1857 ret = devm_request_threaded_irq(&pdev->dev, irq_event, in stm32f7_i2c_probe()
1861 pdev->name, i2c_dev); in stm32f7_i2c_probe()
1863 dev_err(&pdev->dev, "Failed to request irq event %i\n", in stm32f7_i2c_probe()
1868 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0, in stm32f7_i2c_probe()
1869 pdev->name, i2c_dev); in stm32f7_i2c_probe()
1871 dev_err(&pdev->dev, "Failed to request irq error %i\n", in stm32f7_i2c_probe()
1876 setup = of_device_get_match_data(&pdev->dev); in stm32f7_i2c_probe()
1878 dev_err(&pdev->dev, "Can't get device data\n"); in stm32f7_i2c_probe()
1879 ret = -ENODEV; in stm32f7_i2c_probe()
1882 i2c_dev->setup = *setup; in stm32f7_i2c_probe()
1884 ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-rising-time-ns", in stm32f7_i2c_probe()
1887 i2c_dev->setup.rise_time = rise_time; in stm32f7_i2c_probe()
1889 ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-falling-time-ns", in stm32f7_i2c_probe()
1892 i2c_dev->setup.fall_time = fall_time; in stm32f7_i2c_probe()
1894 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup); in stm32f7_i2c_probe()
1900 adap = &i2c_dev->adap; in stm32f7_i2c_probe()
1902 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)", in stm32f7_i2c_probe()
1903 &res->start); in stm32f7_i2c_probe()
1904 adap->owner = THIS_MODULE; in stm32f7_i2c_probe()
1905 adap->timeout = 2 * HZ; in stm32f7_i2c_probe()
1906 adap->retries = 3; in stm32f7_i2c_probe()
1907 adap->algo = &stm32f7_i2c_algo; in stm32f7_i2c_probe()
1908 adap->dev.parent = &pdev->dev; in stm32f7_i2c_probe()
1909 adap->dev.of_node = pdev->dev.of_node; in stm32f7_i2c_probe()
1911 init_completion(&i2c_dev->complete); in stm32f7_i2c_probe()
1914 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr, in stm32f7_i2c_probe()
1917 if (PTR_ERR(i2c_dev->dma) == -ENODEV) in stm32f7_i2c_probe()
1918 i2c_dev->dma = NULL; in stm32f7_i2c_probe()
1919 else if (IS_ERR(i2c_dev->dma)) { in stm32f7_i2c_probe()
1920 ret = PTR_ERR(i2c_dev->dma); in stm32f7_i2c_probe()
1921 if (ret != -EPROBE_DEFER) in stm32f7_i2c_probe()
1922 dev_err(&pdev->dev, in stm32f7_i2c_probe()
1933 clk_disable(i2c_dev->clk); in stm32f7_i2c_probe()
1935 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr); in stm32f7_i2c_probe()
1940 clk_disable_unprepare(i2c_dev->clk); in stm32f7_i2c_probe()
1949 if (i2c_dev->dma) { in stm32f7_i2c_remove()
1950 stm32_i2c_dma_free(i2c_dev->dma); in stm32f7_i2c_remove()
1951 i2c_dev->dma = NULL; in stm32f7_i2c_remove()
1954 i2c_del_adapter(&i2c_dev->adap); in stm32f7_i2c_remove()
1956 clk_unprepare(i2c_dev->clk); in stm32f7_i2c_remove()
1962 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
1969 .name = "stm32f7-i2c",