1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for STMicroelectronics STM32F7 I2C controller
4 *
5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
6 * reference manual.
7 * Please see below a link to the documentation:
8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
9 *
10 * Copyright (C) M'boumba Cedric Madianga 2017
11 * Copyright (C) STMicroelectronics 2017
12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
13 *
14 * This driver is based on i2c-stm32f4.c
15 *
16 */
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/i2c.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23 #include <linux/iopoll.h>
24 #include <linux/module.h>
25 #include <linux/of.h>
26 #include <linux/of_address.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/reset.h>
30 #include <linux/slab.h>
31
32 #include "i2c-stm32.h"
33
34 /* STM32F7 I2C registers */
35 #define STM32F7_I2C_CR1 0x00
36 #define STM32F7_I2C_CR2 0x04
37 #define STM32F7_I2C_OAR1 0x08
38 #define STM32F7_I2C_OAR2 0x0C
39 #define STM32F7_I2C_PECR 0x20
40 #define STM32F7_I2C_TIMINGR 0x10
41 #define STM32F7_I2C_ISR 0x18
42 #define STM32F7_I2C_ICR 0x1C
43 #define STM32F7_I2C_RXDR 0x24
44 #define STM32F7_I2C_TXDR 0x28
45
46 /* STM32F7 I2C control 1 */
47 #define STM32F7_I2C_CR1_PECEN BIT(23)
48 #define STM32F7_I2C_CR1_SBC BIT(16)
49 #define STM32F7_I2C_CR1_RXDMAEN BIT(15)
50 #define STM32F7_I2C_CR1_TXDMAEN BIT(14)
51 #define STM32F7_I2C_CR1_ANFOFF BIT(12)
52 #define STM32F7_I2C_CR1_ERRIE BIT(7)
53 #define STM32F7_I2C_CR1_TCIE BIT(6)
54 #define STM32F7_I2C_CR1_STOPIE BIT(5)
55 #define STM32F7_I2C_CR1_NACKIE BIT(4)
56 #define STM32F7_I2C_CR1_ADDRIE BIT(3)
57 #define STM32F7_I2C_CR1_RXIE BIT(2)
58 #define STM32F7_I2C_CR1_TXIE BIT(1)
59 #define STM32F7_I2C_CR1_PE BIT(0)
60 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \
61 | STM32F7_I2C_CR1_TCIE \
62 | STM32F7_I2C_CR1_STOPIE \
63 | STM32F7_I2C_CR1_NACKIE \
64 | STM32F7_I2C_CR1_RXIE \
65 | STM32F7_I2C_CR1_TXIE)
66 #define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \
67 | STM32F7_I2C_CR1_STOPIE \
68 | STM32F7_I2C_CR1_NACKIE \
69 | STM32F7_I2C_CR1_RXIE \
70 | STM32F7_I2C_CR1_TXIE)
71
72 /* STM32F7 I2C control 2 */
73 #define STM32F7_I2C_CR2_PECBYTE BIT(26)
74 #define STM32F7_I2C_CR2_RELOAD BIT(24)
75 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
76 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16)
77 #define STM32F7_I2C_CR2_NACK BIT(15)
78 #define STM32F7_I2C_CR2_STOP BIT(14)
79 #define STM32F7_I2C_CR2_START BIT(13)
80 #define STM32F7_I2C_CR2_HEAD10R BIT(12)
81 #define STM32F7_I2C_CR2_ADD10 BIT(11)
82 #define STM32F7_I2C_CR2_RD_WRN BIT(10)
83 #define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0)
84 #define STM32F7_I2C_CR2_SADD10(n) (((n) & \
85 STM32F7_I2C_CR2_SADD10_MASK))
86 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1)
87 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1)
88
89 /* STM32F7 I2C Own Address 1 */
90 #define STM32F7_I2C_OAR1_OA1EN BIT(15)
91 #define STM32F7_I2C_OAR1_OA1MODE BIT(10)
92 #define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0)
93 #define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \
94 STM32F7_I2C_OAR1_OA1_10_MASK))
95 #define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1)
96 #define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1)
97 #define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \
98 | STM32F7_I2C_OAR1_OA1_10_MASK \
99 | STM32F7_I2C_OAR1_OA1EN \
100 | STM32F7_I2C_OAR1_OA1MODE)
101
102 /* STM32F7 I2C Own Address 2 */
103 #define STM32F7_I2C_OAR2_OA2EN BIT(15)
104 #define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8)
105 #define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8)
106 #define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1)
107 #define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1)
108 #define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \
109 | STM32F7_I2C_OAR2_OA2_7_MASK \
110 | STM32F7_I2C_OAR2_OA2EN)
111
112 /* STM32F7 I2C Interrupt Status */
113 #define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17)
114 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \
115 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
116 #define STM32F7_I2C_ISR_DIR BIT(16)
117 #define STM32F7_I2C_ISR_BUSY BIT(15)
118 #define STM32F7_I2C_ISR_PECERR BIT(11)
119 #define STM32F7_I2C_ISR_ARLO BIT(9)
120 #define STM32F7_I2C_ISR_BERR BIT(8)
121 #define STM32F7_I2C_ISR_TCR BIT(7)
122 #define STM32F7_I2C_ISR_TC BIT(6)
123 #define STM32F7_I2C_ISR_STOPF BIT(5)
124 #define STM32F7_I2C_ISR_NACKF BIT(4)
125 #define STM32F7_I2C_ISR_ADDR BIT(3)
126 #define STM32F7_I2C_ISR_RXNE BIT(2)
127 #define STM32F7_I2C_ISR_TXIS BIT(1)
128 #define STM32F7_I2C_ISR_TXE BIT(0)
129
130 /* STM32F7 I2C Interrupt Clear */
131 #define STM32F7_I2C_ICR_PECCF BIT(11)
132 #define STM32F7_I2C_ICR_ARLOCF BIT(9)
133 #define STM32F7_I2C_ICR_BERRCF BIT(8)
134 #define STM32F7_I2C_ICR_STOPCF BIT(5)
135 #define STM32F7_I2C_ICR_NACKCF BIT(4)
136 #define STM32F7_I2C_ICR_ADDRCF BIT(3)
137
138 /* STM32F7 I2C Timing */
139 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28)
140 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20)
141 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16)
142 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8)
143 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff)
144
145 #define STM32F7_I2C_MAX_LEN 0xff
146 #define STM32F7_I2C_DMA_LEN_MIN 0x16
147 #define STM32F7_I2C_MAX_SLAVE 0x2
148
149 #define STM32F7_I2C_DNF_DEFAULT 0
150 #define STM32F7_I2C_DNF_MAX 16
151
152 #define STM32F7_I2C_ANALOG_FILTER_ENABLE 1
153 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
154 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
155
156 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */
157 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */
158
159 #define STM32F7_PRESC_MAX BIT(4)
160 #define STM32F7_SCLDEL_MAX BIT(4)
161 #define STM32F7_SDADEL_MAX BIT(4)
162 #define STM32F7_SCLH_MAX BIT(8)
163 #define STM32F7_SCLL_MAX BIT(8)
164
165 /**
166 * struct stm32f7_i2c_spec - private i2c specification timing
167 * @rate: I2C bus speed (Hz)
168 * @rate_min: 80% of I2C bus speed (Hz)
169 * @rate_max: 100% of I2C bus speed (Hz)
170 * @fall_max: Max fall time of both SDA and SCL signals (ns)
171 * @rise_max: Max rise time of both SDA and SCL signals (ns)
172 * @hddat_min: Min data hold time (ns)
173 * @vddat_max: Max data valid time (ns)
174 * @sudat_min: Min data setup time (ns)
175 * @l_min: Min low period of the SCL clock (ns)
176 * @h_min: Min high period of the SCL clock (ns)
177 */
178 struct stm32f7_i2c_spec {
179 u32 rate;
180 u32 rate_min;
181 u32 rate_max;
182 u32 fall_max;
183 u32 rise_max;
184 u32 hddat_min;
185 u32 vddat_max;
186 u32 sudat_min;
187 u32 l_min;
188 u32 h_min;
189 };
190
191 /**
192 * struct stm32f7_i2c_setup - private I2C timing setup parameters
193 * @speed: I2C speed mode (standard, Fast Plus)
194 * @speed_freq: I2C speed frequency (Hz)
195 * @clock_src: I2C clock source frequency (Hz)
196 * @rise_time: Rise time (ns)
197 * @fall_time: Fall time (ns)
198 * @dnf: Digital filter coefficient (0-16)
199 * @analog_filter: Analog filter delay (On/Off)
200 */
201 struct stm32f7_i2c_setup {
202 enum stm32_i2c_speed speed;
203 u32 speed_freq;
204 u32 clock_src;
205 u32 rise_time;
206 u32 fall_time;
207 u8 dnf;
208 bool analog_filter;
209 };
210
211 /**
212 * struct stm32f7_i2c_timings - private I2C output parameters
213 * @node: List entry
214 * @presc: Prescaler value
215 * @scldel: Data setup time
216 * @sdadel: Data hold time
217 * @sclh: SCL high period (master mode)
218 * @scll: SCL low period (master mode)
219 */
220 struct stm32f7_i2c_timings {
221 struct list_head node;
222 u8 presc;
223 u8 scldel;
224 u8 sdadel;
225 u8 sclh;
226 u8 scll;
227 };
228
229 /**
230 * struct stm32f7_i2c_msg - client specific data
231 * @addr: 8-bit or 10-bit slave addr, including r/w bit
232 * @count: number of bytes to be transferred
233 * @buf: data buffer
234 * @result: result of the transfer
235 * @stop: last I2C msg to be sent, i.e. STOP to be generated
236 * @smbus: boolean to know if the I2C IP is used in SMBus mode
237 * @size: type of SMBus protocol
238 * @read_write: direction of SMBus protocol
239 * SMBus block read and SMBus block write - block read process call protocols
240 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
241 * contain a maximum of 32 bytes of data + byte command + byte count + PEC
242 * This buffer has to be 32-bit aligned to be compliant with memory address
243 * register in DMA mode.
244 */
245 struct stm32f7_i2c_msg {
246 u16 addr;
247 u32 count;
248 u8 *buf;
249 int result;
250 bool stop;
251 bool smbus;
252 int size;
253 char read_write;
254 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
255 };
256
257 /**
258 * struct stm32f7_i2c_dev - private data of the controller
259 * @adap: I2C adapter for this controller
260 * @dev: device for this controller
261 * @base: virtual memory area
262 * @complete: completion of I2C message
263 * @clk: hw i2c clock
264 * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+
265 * @msg: Pointer to data to be written
266 * @msg_num: number of I2C messages to be executed
267 * @msg_id: message identifiant
268 * @f7_msg: customized i2c msg for driver usage
269 * @setup: I2C timing input setup
270 * @timing: I2C computed timings
271 * @slave: list of slave devices registered on the I2C bus
272 * @slave_running: slave device currently used
273 * @slave_dir: transfer direction for the current slave device
274 * @master_mode: boolean to know in which mode the I2C is running (master or
275 * slave)
276 * @dma: dma data
277 * @use_dma: boolean to know if dma is used in the current transfer
278 */
279 struct stm32f7_i2c_dev {
280 struct i2c_adapter adap;
281 struct device *dev;
282 void __iomem *base;
283 struct completion complete;
284 struct clk *clk;
285 int speed;
286 struct i2c_msg *msg;
287 unsigned int msg_num;
288 unsigned int msg_id;
289 struct stm32f7_i2c_msg f7_msg;
290 struct stm32f7_i2c_setup setup;
291 struct stm32f7_i2c_timings timing;
292 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
293 struct i2c_client *slave_running;
294 u32 slave_dir;
295 bool master_mode;
296 struct stm32_i2c_dma *dma;
297 bool use_dma;
298 };
299
300 /*
301 * All these values are coming from I2C Specification, Version 6.0, 4th of
302 * April 2014.
303 *
304 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
305 * and Fast-mode Plus I2C-bus devices
306 */
307 static struct stm32f7_i2c_spec i2c_specs[] = {
308 [STM32_I2C_SPEED_STANDARD] = {
309 .rate = 100000,
310 .rate_min = 80000,
311 .rate_max = 100000,
312 .fall_max = 300,
313 .rise_max = 1000,
314 .hddat_min = 0,
315 .vddat_max = 3450,
316 .sudat_min = 250,
317 .l_min = 4700,
318 .h_min = 4000,
319 },
320 [STM32_I2C_SPEED_FAST] = {
321 .rate = 400000,
322 .rate_min = 320000,
323 .rate_max = 400000,
324 .fall_max = 300,
325 .rise_max = 300,
326 .hddat_min = 0,
327 .vddat_max = 900,
328 .sudat_min = 100,
329 .l_min = 1300,
330 .h_min = 600,
331 },
332 [STM32_I2C_SPEED_FAST_PLUS] = {
333 .rate = 1000000,
334 .rate_min = 800000,
335 .rate_max = 1000000,
336 .fall_max = 100,
337 .rise_max = 120,
338 .hddat_min = 0,
339 .vddat_max = 450,
340 .sudat_min = 50,
341 .l_min = 500,
342 .h_min = 260,
343 },
344 };
345
346 static const struct stm32f7_i2c_setup stm32f7_setup = {
347 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
348 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
349 .dnf = STM32F7_I2C_DNF_DEFAULT,
350 .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
351 };
352
stm32f7_i2c_set_bits(void __iomem * reg,u32 mask)353 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
354 {
355 writel_relaxed(readl_relaxed(reg) | mask, reg);
356 }
357
stm32f7_i2c_clr_bits(void __iomem * reg,u32 mask)358 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
359 {
360 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
361 }
362
stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev * i2c_dev,u32 mask)363 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
364 {
365 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
366 }
367
stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev * i2c_dev,struct stm32f7_i2c_setup * setup,struct stm32f7_i2c_timings * output)368 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
369 struct stm32f7_i2c_setup *setup,
370 struct stm32f7_i2c_timings *output)
371 {
372 u32 p_prev = STM32F7_PRESC_MAX;
373 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
374 setup->clock_src);
375 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
376 setup->speed_freq);
377 u32 clk_error_prev = i2cbus;
378 u32 tsync;
379 u32 af_delay_min, af_delay_max;
380 u32 dnf_delay;
381 u32 clk_min, clk_max;
382 int sdadel_min, sdadel_max;
383 int scldel_min;
384 struct stm32f7_i2c_timings *v, *_v, *s;
385 struct list_head solutions;
386 u16 p, l, a, h;
387 int ret = 0;
388
389 if (setup->speed >= STM32_I2C_SPEED_END) {
390 dev_err(i2c_dev->dev, "speed out of bound {%d/%d}\n",
391 setup->speed, STM32_I2C_SPEED_END - 1);
392 return -EINVAL;
393 }
394
395 if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
396 (setup->fall_time > i2c_specs[setup->speed].fall_max)) {
397 dev_err(i2c_dev->dev,
398 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
399 setup->rise_time, i2c_specs[setup->speed].rise_max,
400 setup->fall_time, i2c_specs[setup->speed].fall_max);
401 return -EINVAL;
402 }
403
404 if (setup->dnf > STM32F7_I2C_DNF_MAX) {
405 dev_err(i2c_dev->dev,
406 "DNF out of bound %d/%d\n",
407 setup->dnf, STM32F7_I2C_DNF_MAX);
408 return -EINVAL;
409 }
410
411 if (setup->speed_freq > i2c_specs[setup->speed].rate) {
412 dev_err(i2c_dev->dev, "ERROR: Freq {%d/%d}\n",
413 setup->speed_freq, i2c_specs[setup->speed].rate);
414 return -EINVAL;
415 }
416
417 /* Analog and Digital Filters */
418 af_delay_min =
419 (setup->analog_filter ?
420 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
421 af_delay_max =
422 (setup->analog_filter ?
423 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
424 dnf_delay = setup->dnf * i2cclk;
425
426 sdadel_min = i2c_specs[setup->speed].hddat_min + setup->fall_time -
427 af_delay_min - (setup->dnf + 3) * i2cclk;
428
429 sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
430 af_delay_max - (setup->dnf + 4) * i2cclk;
431
432 scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min;
433
434 if (sdadel_min < 0)
435 sdadel_min = 0;
436 if (sdadel_max < 0)
437 sdadel_max = 0;
438
439 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
440 sdadel_min, sdadel_max, scldel_min);
441
442 INIT_LIST_HEAD(&solutions);
443 /* Compute possible values for PRESC, SCLDEL and SDADEL */
444 for (p = 0; p < STM32F7_PRESC_MAX; p++) {
445 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
446 u32 scldel = (l + 1) * (p + 1) * i2cclk;
447
448 if (scldel < scldel_min)
449 continue;
450
451 for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
452 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
453
454 if (((sdadel >= sdadel_min) &&
455 (sdadel <= sdadel_max)) &&
456 (p != p_prev)) {
457 v = kmalloc(sizeof(*v), GFP_KERNEL);
458 if (!v) {
459 ret = -ENOMEM;
460 goto exit;
461 }
462
463 v->presc = p;
464 v->scldel = l;
465 v->sdadel = a;
466 p_prev = p;
467
468 list_add_tail(&v->node,
469 &solutions);
470 }
471 }
472 }
473 }
474
475 if (list_empty(&solutions)) {
476 dev_err(i2c_dev->dev, "no Prescaler solution\n");
477 ret = -EPERM;
478 goto exit;
479 }
480
481 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
482 s = NULL;
483 clk_max = NSEC_PER_SEC / i2c_specs[setup->speed].rate_min;
484 clk_min = NSEC_PER_SEC / i2c_specs[setup->speed].rate_max;
485
486 /*
487 * Among Prescaler possibilities discovered above figures out SCL Low
488 * and High Period. Provided:
489 * - SCL Low Period has to be higher than SCL Clock Low Period
490 * defined by I2C Specification. I2C Clock has to be lower than
491 * (SCL Low Period - Analog/Digital filters) / 4.
492 * - SCL High Period has to be lower than SCL Clock High Period
493 * defined by I2C Specification
494 * - I2C Clock has to be lower than SCL High Period
495 */
496 list_for_each_entry(v, &solutions, node) {
497 u32 prescaler = (v->presc + 1) * i2cclk;
498
499 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
500 u32 tscl_l = (l + 1) * prescaler + tsync;
501
502 if ((tscl_l < i2c_specs[setup->speed].l_min) ||
503 (i2cclk >=
504 ((tscl_l - af_delay_min - dnf_delay) / 4))) {
505 continue;
506 }
507
508 for (h = 0; h < STM32F7_SCLH_MAX; h++) {
509 u32 tscl_h = (h + 1) * prescaler + tsync;
510 u32 tscl = tscl_l + tscl_h +
511 setup->rise_time + setup->fall_time;
512
513 if ((tscl >= clk_min) && (tscl <= clk_max) &&
514 (tscl_h >= i2c_specs[setup->speed].h_min) &&
515 (i2cclk < tscl_h)) {
516 int clk_error = tscl - i2cbus;
517
518 if (clk_error < 0)
519 clk_error = -clk_error;
520
521 if (clk_error < clk_error_prev) {
522 clk_error_prev = clk_error;
523 v->scll = l;
524 v->sclh = h;
525 s = v;
526 }
527 }
528 }
529 }
530 }
531
532 if (!s) {
533 dev_err(i2c_dev->dev, "no solution at all\n");
534 ret = -EPERM;
535 goto exit;
536 }
537
538 output->presc = s->presc;
539 output->scldel = s->scldel;
540 output->sdadel = s->sdadel;
541 output->scll = s->scll;
542 output->sclh = s->sclh;
543
544 dev_dbg(i2c_dev->dev,
545 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
546 output->presc,
547 output->scldel, output->sdadel,
548 output->scll, output->sclh);
549
550 exit:
551 /* Release list and memory */
552 list_for_each_entry_safe(v, _v, &solutions, node) {
553 list_del(&v->node);
554 kfree(v);
555 }
556
557 return ret;
558 }
559
stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev * i2c_dev,struct stm32f7_i2c_setup * setup)560 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
561 struct stm32f7_i2c_setup *setup)
562 {
563 int ret = 0;
564
565 setup->speed = i2c_dev->speed;
566 setup->speed_freq = i2c_specs[setup->speed].rate;
567 setup->clock_src = clk_get_rate(i2c_dev->clk);
568
569 if (!setup->clock_src) {
570 dev_err(i2c_dev->dev, "clock rate is 0\n");
571 return -EINVAL;
572 }
573
574 do {
575 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
576 &i2c_dev->timing);
577 if (ret) {
578 dev_err(i2c_dev->dev,
579 "failed to compute I2C timings.\n");
580 if (i2c_dev->speed > STM32_I2C_SPEED_STANDARD) {
581 i2c_dev->speed--;
582 setup->speed = i2c_dev->speed;
583 setup->speed_freq =
584 i2c_specs[setup->speed].rate;
585 dev_warn(i2c_dev->dev,
586 "downgrade I2C Speed Freq to (%i)\n",
587 i2c_specs[setup->speed].rate);
588 } else {
589 break;
590 }
591 }
592 } while (ret);
593
594 if (ret) {
595 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
596 return ret;
597 }
598
599 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Freq(%i), Clk Source(%i)\n",
600 setup->speed, setup->speed_freq, setup->clock_src);
601 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
602 setup->rise_time, setup->fall_time);
603 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
604 (setup->analog_filter ? "On" : "Off"), setup->dnf);
605
606 return 0;
607 }
608
stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev * i2c_dev)609 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
610 {
611 void __iomem *base = i2c_dev->base;
612 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
613
614 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
615 }
616
stm32f7_i2c_dma_callback(void * arg)617 static void stm32f7_i2c_dma_callback(void *arg)
618 {
619 struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
620 struct stm32_i2c_dma *dma = i2c_dev->dma;
621 struct device *dev = dma->chan_using->device->dev;
622
623 stm32f7_i2c_disable_dma_req(i2c_dev);
624 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir);
625 complete(&dma->dma_complete);
626 }
627
stm32f7_i2c_hw_config(struct stm32f7_i2c_dev * i2c_dev)628 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
629 {
630 struct stm32f7_i2c_timings *t = &i2c_dev->timing;
631 u32 timing = 0;
632
633 /* Timing settings */
634 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
635 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
636 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
637 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
638 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
639 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
640
641 /* Enable I2C */
642 if (i2c_dev->setup.analog_filter)
643 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
644 STM32F7_I2C_CR1_ANFOFF);
645 else
646 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
647 STM32F7_I2C_CR1_ANFOFF);
648 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
649 STM32F7_I2C_CR1_PE);
650 }
651
stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev * i2c_dev)652 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
653 {
654 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
655 void __iomem *base = i2c_dev->base;
656
657 if (f7_msg->count) {
658 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
659 f7_msg->count--;
660 }
661 }
662
stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev * i2c_dev)663 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
664 {
665 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
666 void __iomem *base = i2c_dev->base;
667
668 if (f7_msg->count) {
669 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
670 f7_msg->count--;
671 } else {
672 /* Flush RX buffer has no data is expected */
673 readb_relaxed(base + STM32F7_I2C_RXDR);
674 }
675 }
676
stm32f7_i2c_reload(struct stm32f7_i2c_dev * i2c_dev)677 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
678 {
679 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
680 u32 cr2;
681
682 if (i2c_dev->use_dma)
683 f7_msg->count -= STM32F7_I2C_MAX_LEN;
684
685 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
686
687 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
688 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
689 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
690 } else {
691 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
692 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
693 }
694
695 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
696 }
697
stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev * i2c_dev)698 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
699 {
700 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
701 u32 cr2;
702 u8 *val;
703
704 /*
705 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
706 * data received inform us how many data will follow.
707 */
708 stm32f7_i2c_read_rx_data(i2c_dev);
709
710 /*
711 * Update NBYTES with the value read to continue the transfer
712 */
713 val = f7_msg->buf - sizeof(u8);
714 f7_msg->count = *val;
715 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
716 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
717 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
718 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
719 }
720
stm32f7_i2c_release_bus(struct i2c_adapter * i2c_adap)721 static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
722 {
723 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
724
725 dev_info(i2c_dev->dev, "Trying to recover bus\n");
726
727 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
728 STM32F7_I2C_CR1_PE);
729
730 stm32f7_i2c_hw_config(i2c_dev);
731
732 return 0;
733 }
734
stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev * i2c_dev)735 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
736 {
737 u32 status;
738 int ret;
739
740 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
741 status,
742 !(status & STM32F7_I2C_ISR_BUSY),
743 10, 1000);
744 if (!ret)
745 return 0;
746
747 dev_info(i2c_dev->dev, "bus busy\n");
748
749 ret = stm32f7_i2c_release_bus(&i2c_dev->adap);
750 if (ret) {
751 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
752 return ret;
753 }
754
755 return -EBUSY;
756 }
757
stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev * i2c_dev,struct i2c_msg * msg)758 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
759 struct i2c_msg *msg)
760 {
761 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
762 void __iomem *base = i2c_dev->base;
763 u32 cr1, cr2;
764 int ret;
765
766 f7_msg->addr = msg->addr;
767 f7_msg->buf = msg->buf;
768 f7_msg->count = msg->len;
769 f7_msg->result = 0;
770 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
771
772 reinit_completion(&i2c_dev->complete);
773
774 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
775 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
776
777 /* Set transfer direction */
778 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
779 if (msg->flags & I2C_M_RD)
780 cr2 |= STM32F7_I2C_CR2_RD_WRN;
781
782 /* Set slave address */
783 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
784 if (msg->flags & I2C_M_TEN) {
785 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
786 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
787 cr2 |= STM32F7_I2C_CR2_ADD10;
788 } else {
789 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
790 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
791 }
792
793 /* Set nb bytes to transfer and reload if needed */
794 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
795 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
796 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
797 cr2 |= STM32F7_I2C_CR2_RELOAD;
798 } else {
799 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
800 }
801
802 /* Enable NACK, STOP, error and transfer complete interrupts */
803 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
804 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
805
806 /* Clear DMA req and TX/RX interrupt */
807 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
808 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
809
810 /* Configure DMA or enable RX/TX interrupt */
811 i2c_dev->use_dma = false;
812 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
813 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
814 msg->flags & I2C_M_RD,
815 f7_msg->count, f7_msg->buf,
816 stm32f7_i2c_dma_callback,
817 i2c_dev);
818 if (!ret)
819 i2c_dev->use_dma = true;
820 else
821 dev_warn(i2c_dev->dev, "can't use DMA\n");
822 }
823
824 if (!i2c_dev->use_dma) {
825 if (msg->flags & I2C_M_RD)
826 cr1 |= STM32F7_I2C_CR1_RXIE;
827 else
828 cr1 |= STM32F7_I2C_CR1_TXIE;
829 } else {
830 if (msg->flags & I2C_M_RD)
831 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
832 else
833 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
834 }
835
836 /* Configure Start/Repeated Start */
837 cr2 |= STM32F7_I2C_CR2_START;
838
839 i2c_dev->master_mode = true;
840
841 /* Write configurations registers */
842 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
843 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
844 }
845
stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev * i2c_dev,unsigned short flags,u8 command,union i2c_smbus_data * data)846 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
847 unsigned short flags, u8 command,
848 union i2c_smbus_data *data)
849 {
850 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
851 struct device *dev = i2c_dev->dev;
852 void __iomem *base = i2c_dev->base;
853 u32 cr1, cr2;
854 int i, ret;
855
856 f7_msg->result = 0;
857 reinit_completion(&i2c_dev->complete);
858
859 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
860 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
861
862 /* Set transfer direction */
863 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
864 if (f7_msg->read_write)
865 cr2 |= STM32F7_I2C_CR2_RD_WRN;
866
867 /* Set slave address */
868 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
869 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
870
871 f7_msg->smbus_buf[0] = command;
872 switch (f7_msg->size) {
873 case I2C_SMBUS_QUICK:
874 f7_msg->stop = true;
875 f7_msg->count = 0;
876 break;
877 case I2C_SMBUS_BYTE:
878 f7_msg->stop = true;
879 f7_msg->count = 1;
880 break;
881 case I2C_SMBUS_BYTE_DATA:
882 if (f7_msg->read_write) {
883 f7_msg->stop = false;
884 f7_msg->count = 1;
885 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
886 } else {
887 f7_msg->stop = true;
888 f7_msg->count = 2;
889 f7_msg->smbus_buf[1] = data->byte;
890 }
891 break;
892 case I2C_SMBUS_WORD_DATA:
893 if (f7_msg->read_write) {
894 f7_msg->stop = false;
895 f7_msg->count = 1;
896 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
897 } else {
898 f7_msg->stop = true;
899 f7_msg->count = 3;
900 f7_msg->smbus_buf[1] = data->word & 0xff;
901 f7_msg->smbus_buf[2] = data->word >> 8;
902 }
903 break;
904 case I2C_SMBUS_BLOCK_DATA:
905 if (f7_msg->read_write) {
906 f7_msg->stop = false;
907 f7_msg->count = 1;
908 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
909 } else {
910 f7_msg->stop = true;
911 if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
912 !data->block[0]) {
913 dev_err(dev, "Invalid block write size %d\n",
914 data->block[0]);
915 return -EINVAL;
916 }
917 f7_msg->count = data->block[0] + 2;
918 for (i = 1; i < f7_msg->count; i++)
919 f7_msg->smbus_buf[i] = data->block[i - 1];
920 }
921 break;
922 case I2C_SMBUS_PROC_CALL:
923 f7_msg->stop = false;
924 f7_msg->count = 3;
925 f7_msg->smbus_buf[1] = data->word & 0xff;
926 f7_msg->smbus_buf[2] = data->word >> 8;
927 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
928 f7_msg->read_write = I2C_SMBUS_READ;
929 break;
930 case I2C_SMBUS_BLOCK_PROC_CALL:
931 f7_msg->stop = false;
932 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
933 dev_err(dev, "Invalid block write size %d\n",
934 data->block[0]);
935 return -EINVAL;
936 }
937 f7_msg->count = data->block[0] + 2;
938 for (i = 1; i < f7_msg->count; i++)
939 f7_msg->smbus_buf[i] = data->block[i - 1];
940 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
941 f7_msg->read_write = I2C_SMBUS_READ;
942 break;
943 default:
944 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
945 return -EOPNOTSUPP;
946 }
947
948 f7_msg->buf = f7_msg->smbus_buf;
949
950 /* Configure PEC */
951 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
952 cr1 |= STM32F7_I2C_CR1_PECEN;
953 cr2 |= STM32F7_I2C_CR2_PECBYTE;
954 if (!f7_msg->read_write)
955 f7_msg->count++;
956 } else {
957 cr1 &= ~STM32F7_I2C_CR1_PECEN;
958 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
959 }
960
961 /* Set number of bytes to be transferred */
962 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
963 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
964
965 /* Enable NACK, STOP, error and transfer complete interrupts */
966 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
967 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
968
969 /* Clear DMA req and TX/RX interrupt */
970 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
971 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
972
973 /* Configure DMA or enable RX/TX interrupt */
974 i2c_dev->use_dma = false;
975 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
976 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
977 cr2 & STM32F7_I2C_CR2_RD_WRN,
978 f7_msg->count, f7_msg->buf,
979 stm32f7_i2c_dma_callback,
980 i2c_dev);
981 if (!ret)
982 i2c_dev->use_dma = true;
983 else
984 dev_warn(i2c_dev->dev, "can't use DMA\n");
985 }
986
987 if (!i2c_dev->use_dma) {
988 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
989 cr1 |= STM32F7_I2C_CR1_RXIE;
990 else
991 cr1 |= STM32F7_I2C_CR1_TXIE;
992 } else {
993 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
994 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
995 else
996 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
997 }
998
999 /* Set Start bit */
1000 cr2 |= STM32F7_I2C_CR2_START;
1001
1002 i2c_dev->master_mode = true;
1003
1004 /* Write configurations registers */
1005 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1006 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1007
1008 return 0;
1009 }
1010
stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev * i2c_dev)1011 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1012 {
1013 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1014 void __iomem *base = i2c_dev->base;
1015 u32 cr1, cr2;
1016 int ret;
1017
1018 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1019 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1020
1021 /* Set transfer direction */
1022 cr2 |= STM32F7_I2C_CR2_RD_WRN;
1023
1024 switch (f7_msg->size) {
1025 case I2C_SMBUS_BYTE_DATA:
1026 f7_msg->count = 1;
1027 break;
1028 case I2C_SMBUS_WORD_DATA:
1029 case I2C_SMBUS_PROC_CALL:
1030 f7_msg->count = 2;
1031 break;
1032 case I2C_SMBUS_BLOCK_DATA:
1033 case I2C_SMBUS_BLOCK_PROC_CALL:
1034 f7_msg->count = 1;
1035 cr2 |= STM32F7_I2C_CR2_RELOAD;
1036 break;
1037 }
1038
1039 f7_msg->buf = f7_msg->smbus_buf;
1040 f7_msg->stop = true;
1041
1042 /* Add one byte for PEC if needed */
1043 if (cr1 & STM32F7_I2C_CR1_PECEN)
1044 f7_msg->count++;
1045
1046 /* Set number of bytes to be transferred */
1047 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1048 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1049
1050 /*
1051 * Configure RX/TX interrupt:
1052 */
1053 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1054 cr1 |= STM32F7_I2C_CR1_RXIE;
1055
1056 /*
1057 * Configure DMA or enable RX/TX interrupt:
1058 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1059 * dma as we don't know in advance how many data will be received
1060 */
1061 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1062 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1063
1064 i2c_dev->use_dma = false;
1065 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1066 f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1067 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1068 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1069 cr2 & STM32F7_I2C_CR2_RD_WRN,
1070 f7_msg->count, f7_msg->buf,
1071 stm32f7_i2c_dma_callback,
1072 i2c_dev);
1073
1074 if (!ret)
1075 i2c_dev->use_dma = true;
1076 else
1077 dev_warn(i2c_dev->dev, "can't use DMA\n");
1078 }
1079
1080 if (!i2c_dev->use_dma)
1081 cr1 |= STM32F7_I2C_CR1_RXIE;
1082 else
1083 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1084
1085 /* Configure Repeated Start */
1086 cr2 |= STM32F7_I2C_CR2_START;
1087
1088 /* Write configurations registers */
1089 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1090 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1091 }
1092
stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev * i2c_dev)1093 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1094 {
1095 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1096 u8 count, internal_pec, received_pec;
1097
1098 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1099
1100 switch (f7_msg->size) {
1101 case I2C_SMBUS_BYTE:
1102 case I2C_SMBUS_BYTE_DATA:
1103 received_pec = f7_msg->smbus_buf[1];
1104 break;
1105 case I2C_SMBUS_WORD_DATA:
1106 case I2C_SMBUS_PROC_CALL:
1107 received_pec = f7_msg->smbus_buf[2];
1108 break;
1109 case I2C_SMBUS_BLOCK_DATA:
1110 case I2C_SMBUS_BLOCK_PROC_CALL:
1111 count = f7_msg->smbus_buf[0];
1112 received_pec = f7_msg->smbus_buf[count];
1113 break;
1114 default:
1115 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1116 return -EINVAL;
1117 }
1118
1119 if (internal_pec != received_pec) {
1120 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1121 internal_pec, received_pec);
1122 return -EBADMSG;
1123 }
1124
1125 return 0;
1126 }
1127
stm32f7_i2c_is_addr_match(struct i2c_client * slave,u32 addcode)1128 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1129 {
1130 u32 addr;
1131
1132 if (!slave)
1133 return false;
1134
1135 if (slave->flags & I2C_CLIENT_TEN) {
1136 /*
1137 * For 10-bit addr, addcode = 11110XY with
1138 * X = Bit 9 of slave address
1139 * Y = Bit 8 of slave address
1140 */
1141 addr = slave->addr >> 8;
1142 addr |= 0x78;
1143 if (addr == addcode)
1144 return true;
1145 } else {
1146 addr = slave->addr & 0x7f;
1147 if (addr == addcode)
1148 return true;
1149 }
1150
1151 return false;
1152 }
1153
stm32f7_i2c_slave_start(struct stm32f7_i2c_dev * i2c_dev)1154 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1155 {
1156 struct i2c_client *slave = i2c_dev->slave_running;
1157 void __iomem *base = i2c_dev->base;
1158 u32 mask;
1159 u8 value = 0;
1160
1161 if (i2c_dev->slave_dir) {
1162 /* Notify i2c slave that new read transfer is starting */
1163 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1164
1165 /*
1166 * Disable slave TX config in case of I2C combined message
1167 * (I2C Write followed by I2C Read)
1168 */
1169 mask = STM32F7_I2C_CR2_RELOAD;
1170 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1171 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1172 STM32F7_I2C_CR1_TCIE;
1173 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1174
1175 /* Enable TX empty, STOP, NACK interrupts */
1176 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1177 STM32F7_I2C_CR1_TXIE;
1178 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1179
1180 /* Write 1st data byte */
1181 writel_relaxed(value, base + STM32F7_I2C_TXDR);
1182 } else {
1183 /* Notify i2c slave that new write transfer is starting */
1184 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1185
1186 /* Set reload mode to be able to ACK/NACK each received byte */
1187 mask = STM32F7_I2C_CR2_RELOAD;
1188 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1189
1190 /*
1191 * Set STOP, NACK, RX empty and transfer complete interrupts.*
1192 * Set Slave Byte Control to be able to ACK/NACK each data
1193 * byte received
1194 */
1195 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1196 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1197 STM32F7_I2C_CR1_TCIE;
1198 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1199 }
1200 }
1201
stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev * i2c_dev)1202 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1203 {
1204 void __iomem *base = i2c_dev->base;
1205 u32 isr, addcode, dir, mask;
1206 int i;
1207
1208 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1209 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1210 dir = isr & STM32F7_I2C_ISR_DIR;
1211
1212 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1213 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1214 i2c_dev->slave_running = i2c_dev->slave[i];
1215 i2c_dev->slave_dir = dir;
1216
1217 /* Start I2C slave processing */
1218 stm32f7_i2c_slave_start(i2c_dev);
1219
1220 /* Clear ADDR flag */
1221 mask = STM32F7_I2C_ICR_ADDRCF;
1222 writel_relaxed(mask, base + STM32F7_I2C_ICR);
1223 break;
1224 }
1225 }
1226 }
1227
stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev * i2c_dev,struct i2c_client * slave,int * id)1228 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1229 struct i2c_client *slave, int *id)
1230 {
1231 int i;
1232
1233 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1234 if (i2c_dev->slave[i] == slave) {
1235 *id = i;
1236 return 0;
1237 }
1238 }
1239
1240 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1241
1242 return -ENODEV;
1243 }
1244
stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev * i2c_dev,struct i2c_client * slave,int * id)1245 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1246 struct i2c_client *slave, int *id)
1247 {
1248 struct device *dev = i2c_dev->dev;
1249 int i;
1250
1251 /*
1252 * slave[0] supports 7-bit and 10-bit slave address
1253 * slave[1] supports 7-bit slave address only
1254 */
1255 for (i = STM32F7_I2C_MAX_SLAVE - 1; i >= 0; i--) {
1256 if (i == 1 && (slave->flags & I2C_CLIENT_TEN))
1257 continue;
1258 if (!i2c_dev->slave[i]) {
1259 *id = i;
1260 return 0;
1261 }
1262 }
1263
1264 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1265
1266 return -EINVAL;
1267 }
1268
stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev * i2c_dev)1269 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1270 {
1271 int i;
1272
1273 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1274 if (i2c_dev->slave[i])
1275 return true;
1276 }
1277
1278 return false;
1279 }
1280
stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev * i2c_dev)1281 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1282 {
1283 int i, busy;
1284
1285 busy = 0;
1286 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1287 if (i2c_dev->slave[i])
1288 busy++;
1289 }
1290
1291 return i == busy;
1292 }
1293
stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev * i2c_dev)1294 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
1295 {
1296 void __iomem *base = i2c_dev->base;
1297 u32 cr2, status, mask;
1298 u8 val;
1299 int ret;
1300
1301 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1302
1303 /* Slave transmitter mode */
1304 if (status & STM32F7_I2C_ISR_TXIS) {
1305 i2c_slave_event(i2c_dev->slave_running,
1306 I2C_SLAVE_READ_PROCESSED,
1307 &val);
1308
1309 /* Write data byte */
1310 writel_relaxed(val, base + STM32F7_I2C_TXDR);
1311 }
1312
1313 /* Transfer Complete Reload for Slave receiver mode */
1314 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1315 /*
1316 * Read data byte then set NBYTES to receive next byte or NACK
1317 * the current received byte
1318 */
1319 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1320 ret = i2c_slave_event(i2c_dev->slave_running,
1321 I2C_SLAVE_WRITE_RECEIVED,
1322 &val);
1323 if (!ret) {
1324 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1325 cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1326 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1327 } else {
1328 mask = STM32F7_I2C_CR2_NACK;
1329 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1330 }
1331 }
1332
1333 /* NACK received */
1334 if (status & STM32F7_I2C_ISR_NACKF) {
1335 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1336 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1337 }
1338
1339 /* STOP received */
1340 if (status & STM32F7_I2C_ISR_STOPF) {
1341 /* Disable interrupts */
1342 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1343
1344 if (i2c_dev->slave_dir) {
1345 /*
1346 * Flush TX buffer in order to not used the byte in
1347 * TXDR for the next transfer
1348 */
1349 mask = STM32F7_I2C_ISR_TXE;
1350 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1351 }
1352
1353 /* Clear STOP flag */
1354 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1355
1356 /* Notify i2c slave that a STOP flag has been detected */
1357 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1358
1359 i2c_dev->slave_running = NULL;
1360 }
1361
1362 /* Address match received */
1363 if (status & STM32F7_I2C_ISR_ADDR)
1364 stm32f7_i2c_slave_addr(i2c_dev);
1365
1366 return IRQ_HANDLED;
1367 }
1368
stm32f7_i2c_isr_event(int irq,void * data)1369 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1370 {
1371 struct stm32f7_i2c_dev *i2c_dev = data;
1372 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1373 void __iomem *base = i2c_dev->base;
1374 u32 status, mask;
1375 int ret = IRQ_HANDLED;
1376
1377 /* Check if the interrupt if for a slave device */
1378 if (!i2c_dev->master_mode) {
1379 ret = stm32f7_i2c_slave_isr_event(i2c_dev);
1380 return ret;
1381 }
1382
1383 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1384
1385 /* Tx empty */
1386 if (status & STM32F7_I2C_ISR_TXIS)
1387 stm32f7_i2c_write_tx_data(i2c_dev);
1388
1389 /* RX not empty */
1390 if (status & STM32F7_I2C_ISR_RXNE)
1391 stm32f7_i2c_read_rx_data(i2c_dev);
1392
1393 /* NACK received */
1394 if (status & STM32F7_I2C_ISR_NACKF) {
1395 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1396 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1397 f7_msg->result = -ENXIO;
1398 }
1399
1400 /* STOP detection flag */
1401 if (status & STM32F7_I2C_ISR_STOPF) {
1402 /* Disable interrupts */
1403 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1404 mask = STM32F7_I2C_XFER_IRQ_MASK;
1405 else
1406 mask = STM32F7_I2C_ALL_IRQ_MASK;
1407 stm32f7_i2c_disable_irq(i2c_dev, mask);
1408
1409 /* Clear STOP flag */
1410 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1411
1412 if (i2c_dev->use_dma) {
1413 ret = IRQ_WAKE_THREAD;
1414 } else {
1415 i2c_dev->master_mode = false;
1416 complete(&i2c_dev->complete);
1417 }
1418 }
1419
1420 /* Transfer complete */
1421 if (status & STM32F7_I2C_ISR_TC) {
1422 if (f7_msg->stop) {
1423 mask = STM32F7_I2C_CR2_STOP;
1424 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1425 } else if (i2c_dev->use_dma) {
1426 ret = IRQ_WAKE_THREAD;
1427 } else if (f7_msg->smbus) {
1428 stm32f7_i2c_smbus_rep_start(i2c_dev);
1429 } else {
1430 i2c_dev->msg_id++;
1431 i2c_dev->msg++;
1432 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1433 }
1434 }
1435
1436 if (status & STM32F7_I2C_ISR_TCR) {
1437 if (f7_msg->smbus)
1438 stm32f7_i2c_smbus_reload(i2c_dev);
1439 else
1440 stm32f7_i2c_reload(i2c_dev);
1441 }
1442
1443 return ret;
1444 }
1445
stm32f7_i2c_isr_event_thread(int irq,void * data)1446 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1447 {
1448 struct stm32f7_i2c_dev *i2c_dev = data;
1449 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1450 struct stm32_i2c_dma *dma = i2c_dev->dma;
1451 u32 status;
1452 int ret;
1453
1454 /*
1455 * Wait for dma transfer completion before sending next message or
1456 * notity the end of xfer to the client
1457 */
1458 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1459 if (!ret) {
1460 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1461 stm32f7_i2c_disable_dma_req(i2c_dev);
1462 dmaengine_terminate_all(dma->chan_using);
1463 f7_msg->result = -ETIMEDOUT;
1464 }
1465
1466 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1467
1468 if (status & STM32F7_I2C_ISR_TC) {
1469 if (f7_msg->smbus) {
1470 stm32f7_i2c_smbus_rep_start(i2c_dev);
1471 } else {
1472 i2c_dev->msg_id++;
1473 i2c_dev->msg++;
1474 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1475 }
1476 } else {
1477 i2c_dev->master_mode = false;
1478 complete(&i2c_dev->complete);
1479 }
1480
1481 return IRQ_HANDLED;
1482 }
1483
stm32f7_i2c_isr_error(int irq,void * data)1484 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
1485 {
1486 struct stm32f7_i2c_dev *i2c_dev = data;
1487 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1488 void __iomem *base = i2c_dev->base;
1489 struct device *dev = i2c_dev->dev;
1490 struct stm32_i2c_dma *dma = i2c_dev->dma;
1491 u32 status;
1492
1493 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1494
1495 /* Bus error */
1496 if (status & STM32F7_I2C_ISR_BERR) {
1497 dev_err(dev, "<%s>: Bus error\n", __func__);
1498 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1499 stm32f7_i2c_release_bus(&i2c_dev->adap);
1500 f7_msg->result = -EIO;
1501 }
1502
1503 /* Arbitration loss */
1504 if (status & STM32F7_I2C_ISR_ARLO) {
1505 dev_dbg(dev, "<%s>: Arbitration loss\n", __func__);
1506 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1507 f7_msg->result = -EAGAIN;
1508 }
1509
1510 if (status & STM32F7_I2C_ISR_PECERR) {
1511 dev_err(dev, "<%s>: PEC error in reception\n", __func__);
1512 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1513 f7_msg->result = -EINVAL;
1514 }
1515
1516 if (!i2c_dev->slave_running) {
1517 u32 mask;
1518 /* Disable interrupts */
1519 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1520 mask = STM32F7_I2C_XFER_IRQ_MASK;
1521 else
1522 mask = STM32F7_I2C_ALL_IRQ_MASK;
1523 stm32f7_i2c_disable_irq(i2c_dev, mask);
1524 }
1525
1526 /* Disable dma */
1527 if (i2c_dev->use_dma) {
1528 stm32f7_i2c_disable_dma_req(i2c_dev);
1529 dmaengine_terminate_all(dma->chan_using);
1530 }
1531
1532 i2c_dev->master_mode = false;
1533 complete(&i2c_dev->complete);
1534
1535 return IRQ_HANDLED;
1536 }
1537
stm32f7_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg msgs[],int num)1538 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1539 struct i2c_msg msgs[], int num)
1540 {
1541 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1542 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1543 struct stm32_i2c_dma *dma = i2c_dev->dma;
1544 unsigned long time_left;
1545 int ret;
1546
1547 i2c_dev->msg = msgs;
1548 i2c_dev->msg_num = num;
1549 i2c_dev->msg_id = 0;
1550 f7_msg->smbus = false;
1551
1552 ret = clk_enable(i2c_dev->clk);
1553 if (ret) {
1554 dev_err(i2c_dev->dev, "Failed to enable clock\n");
1555 return ret;
1556 }
1557
1558 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1559 if (ret)
1560 goto clk_free;
1561
1562 stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1563
1564 time_left = wait_for_completion_timeout(&i2c_dev->complete,
1565 i2c_dev->adap.timeout);
1566 ret = f7_msg->result;
1567
1568 if (!time_left) {
1569 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1570 i2c_dev->msg->addr);
1571 if (i2c_dev->use_dma)
1572 dmaengine_terminate_all(dma->chan_using);
1573 ret = -ETIMEDOUT;
1574 }
1575
1576 clk_free:
1577 clk_disable(i2c_dev->clk);
1578
1579 return (ret < 0) ? ret : num;
1580 }
1581
stm32f7_i2c_smbus_xfer(struct i2c_adapter * adapter,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)1582 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1583 unsigned short flags, char read_write,
1584 u8 command, int size,
1585 union i2c_smbus_data *data)
1586 {
1587 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1588 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1589 struct stm32_i2c_dma *dma = i2c_dev->dma;
1590 struct device *dev = i2c_dev->dev;
1591 unsigned long timeout;
1592 int i, ret;
1593
1594 f7_msg->addr = addr;
1595 f7_msg->size = size;
1596 f7_msg->read_write = read_write;
1597 f7_msg->smbus = true;
1598
1599 ret = clk_enable(i2c_dev->clk);
1600 if (ret) {
1601 dev_err(i2c_dev->dev, "Failed to enable clock\n");
1602 return ret;
1603 }
1604
1605 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1606 if (ret)
1607 goto clk_free;
1608
1609 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1610 if (ret)
1611 goto clk_free;
1612
1613 timeout = wait_for_completion_timeout(&i2c_dev->complete,
1614 i2c_dev->adap.timeout);
1615 ret = f7_msg->result;
1616 if (ret)
1617 goto clk_free;
1618
1619 if (!timeout) {
1620 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1621 if (i2c_dev->use_dma)
1622 dmaengine_terminate_all(dma->chan_using);
1623 ret = -ETIMEDOUT;
1624 goto clk_free;
1625 }
1626
1627 /* Check PEC */
1628 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1629 ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1630 if (ret)
1631 goto clk_free;
1632 }
1633
1634 if (read_write && size != I2C_SMBUS_QUICK) {
1635 switch (size) {
1636 case I2C_SMBUS_BYTE:
1637 case I2C_SMBUS_BYTE_DATA:
1638 data->byte = f7_msg->smbus_buf[0];
1639 break;
1640 case I2C_SMBUS_WORD_DATA:
1641 case I2C_SMBUS_PROC_CALL:
1642 data->word = f7_msg->smbus_buf[0] |
1643 (f7_msg->smbus_buf[1] << 8);
1644 break;
1645 case I2C_SMBUS_BLOCK_DATA:
1646 case I2C_SMBUS_BLOCK_PROC_CALL:
1647 for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1648 data->block[i] = f7_msg->smbus_buf[i];
1649 break;
1650 default:
1651 dev_err(dev, "Unsupported smbus transaction\n");
1652 ret = -EINVAL;
1653 }
1654 }
1655
1656 clk_free:
1657 clk_disable(i2c_dev->clk);
1658 return ret;
1659 }
1660
stm32f7_i2c_reg_slave(struct i2c_client * slave)1661 static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1662 {
1663 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1664 void __iomem *base = i2c_dev->base;
1665 struct device *dev = i2c_dev->dev;
1666 u32 oar1, oar2, mask;
1667 int id, ret;
1668
1669 if (slave->flags & I2C_CLIENT_PEC) {
1670 dev_err(dev, "SMBus PEC not supported in slave mode\n");
1671 return -EINVAL;
1672 }
1673
1674 if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1675 dev_err(dev, "Too much slave registered\n");
1676 return -EBUSY;
1677 }
1678
1679 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1680 if (ret)
1681 return ret;
1682
1683 if (!(stm32f7_i2c_is_slave_registered(i2c_dev))) {
1684 ret = clk_enable(i2c_dev->clk);
1685 if (ret) {
1686 dev_err(dev, "Failed to enable clock\n");
1687 return ret;
1688 }
1689 }
1690
1691 if (id == 0) {
1692 /* Configure Own Address 1 */
1693 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1694 oar1 &= ~STM32F7_I2C_OAR1_MASK;
1695 if (slave->flags & I2C_CLIENT_TEN) {
1696 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1697 oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1698 } else {
1699 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1700 }
1701 oar1 |= STM32F7_I2C_OAR1_OA1EN;
1702 i2c_dev->slave[id] = slave;
1703 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1704 } else if (id == 1) {
1705 /* Configure Own Address 2 */
1706 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1707 oar2 &= ~STM32F7_I2C_OAR2_MASK;
1708 if (slave->flags & I2C_CLIENT_TEN) {
1709 ret = -EOPNOTSUPP;
1710 goto exit;
1711 }
1712
1713 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1714 oar2 |= STM32F7_I2C_OAR2_OA2EN;
1715 i2c_dev->slave[id] = slave;
1716 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1717 } else {
1718 ret = -ENODEV;
1719 goto exit;
1720 }
1721
1722 /* Enable ACK */
1723 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1724
1725 /* Enable Address match interrupt, error interrupt and enable I2C */
1726 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1727 STM32F7_I2C_CR1_PE;
1728 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1729
1730 return 0;
1731
1732 exit:
1733 if (!(stm32f7_i2c_is_slave_registered(i2c_dev)))
1734 clk_disable(i2c_dev->clk);
1735
1736 return ret;
1737 }
1738
stm32f7_i2c_unreg_slave(struct i2c_client * slave)1739 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1740 {
1741 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1742 void __iomem *base = i2c_dev->base;
1743 u32 mask;
1744 int id, ret;
1745
1746 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1747 if (ret)
1748 return ret;
1749
1750 WARN_ON(!i2c_dev->slave[id]);
1751
1752 if (id == 0) {
1753 mask = STM32F7_I2C_OAR1_OA1EN;
1754 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
1755 } else {
1756 mask = STM32F7_I2C_OAR2_OA2EN;
1757 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
1758 }
1759
1760 i2c_dev->slave[id] = NULL;
1761
1762 if (!(stm32f7_i2c_is_slave_registered(i2c_dev))) {
1763 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
1764 clk_disable(i2c_dev->clk);
1765 }
1766
1767 return 0;
1768 }
1769
stm32f7_i2c_func(struct i2c_adapter * adap)1770 static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
1771 {
1772 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
1773 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
1774 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
1775 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
1776 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC;
1777 }
1778
1779 static struct i2c_algorithm stm32f7_i2c_algo = {
1780 .master_xfer = stm32f7_i2c_xfer,
1781 .smbus_xfer = stm32f7_i2c_smbus_xfer,
1782 .functionality = stm32f7_i2c_func,
1783 .reg_slave = stm32f7_i2c_reg_slave,
1784 .unreg_slave = stm32f7_i2c_unreg_slave,
1785 };
1786
stm32f7_i2c_probe(struct platform_device * pdev)1787 static int stm32f7_i2c_probe(struct platform_device *pdev)
1788 {
1789 struct stm32f7_i2c_dev *i2c_dev;
1790 const struct stm32f7_i2c_setup *setup;
1791 struct resource *res;
1792 u32 clk_rate, rise_time, fall_time;
1793 struct i2c_adapter *adap;
1794 struct reset_control *rst;
1795 dma_addr_t phy_addr;
1796 int irq_error, irq_event, ret;
1797
1798 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1799 if (!i2c_dev)
1800 return -ENOMEM;
1801
1802 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1803 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
1804 if (IS_ERR(i2c_dev->base))
1805 return PTR_ERR(i2c_dev->base);
1806 phy_addr = (dma_addr_t)res->start;
1807
1808 irq_event = platform_get_irq(pdev, 0);
1809 if (irq_event <= 0) {
1810 if (irq_event != -EPROBE_DEFER)
1811 dev_err(&pdev->dev, "Failed to get IRQ event: %d\n",
1812 irq_event);
1813 return irq_event ? : -ENOENT;
1814 }
1815
1816 irq_error = platform_get_irq(pdev, 1);
1817 if (irq_error <= 0) {
1818 if (irq_error != -EPROBE_DEFER)
1819 dev_err(&pdev->dev, "Failed to get IRQ error: %d\n",
1820 irq_error);
1821 return irq_error ? : -ENOENT;
1822 }
1823
1824 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
1825 if (IS_ERR(i2c_dev->clk)) {
1826 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1827 return PTR_ERR(i2c_dev->clk);
1828 }
1829 ret = clk_prepare_enable(i2c_dev->clk);
1830 if (ret) {
1831 dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
1832 return ret;
1833 }
1834
1835 i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
1836 ret = device_property_read_u32(&pdev->dev, "clock-frequency",
1837 &clk_rate);
1838 if (!ret && clk_rate >= 1000000)
1839 i2c_dev->speed = STM32_I2C_SPEED_FAST_PLUS;
1840 else if (!ret && clk_rate >= 400000)
1841 i2c_dev->speed = STM32_I2C_SPEED_FAST;
1842 else if (!ret && clk_rate >= 100000)
1843 i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
1844
1845 rst = devm_reset_control_get(&pdev->dev, NULL);
1846 if (IS_ERR(rst)) {
1847 dev_err(&pdev->dev, "Error: Missing controller reset\n");
1848 ret = PTR_ERR(rst);
1849 goto clk_free;
1850 }
1851 reset_control_assert(rst);
1852 udelay(2);
1853 reset_control_deassert(rst);
1854
1855 i2c_dev->dev = &pdev->dev;
1856
1857 ret = devm_request_threaded_irq(&pdev->dev, irq_event,
1858 stm32f7_i2c_isr_event,
1859 stm32f7_i2c_isr_event_thread,
1860 IRQF_ONESHOT,
1861 pdev->name, i2c_dev);
1862 if (ret) {
1863 dev_err(&pdev->dev, "Failed to request irq event %i\n",
1864 irq_event);
1865 goto clk_free;
1866 }
1867
1868 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
1869 pdev->name, i2c_dev);
1870 if (ret) {
1871 dev_err(&pdev->dev, "Failed to request irq error %i\n",
1872 irq_error);
1873 goto clk_free;
1874 }
1875
1876 setup = of_device_get_match_data(&pdev->dev);
1877 if (!setup) {
1878 dev_err(&pdev->dev, "Can't get device data\n");
1879 ret = -ENODEV;
1880 goto clk_free;
1881 }
1882 i2c_dev->setup = *setup;
1883
1884 ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-rising-time-ns",
1885 &rise_time);
1886 if (!ret)
1887 i2c_dev->setup.rise_time = rise_time;
1888
1889 ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-falling-time-ns",
1890 &fall_time);
1891 if (!ret)
1892 i2c_dev->setup.fall_time = fall_time;
1893
1894 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
1895 if (ret)
1896 goto clk_free;
1897
1898 stm32f7_i2c_hw_config(i2c_dev);
1899
1900 adap = &i2c_dev->adap;
1901 i2c_set_adapdata(adap, i2c_dev);
1902 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
1903 &res->start);
1904 adap->owner = THIS_MODULE;
1905 adap->timeout = 2 * HZ;
1906 adap->retries = 3;
1907 adap->algo = &stm32f7_i2c_algo;
1908 adap->dev.parent = &pdev->dev;
1909 adap->dev.of_node = pdev->dev.of_node;
1910
1911 init_completion(&i2c_dev->complete);
1912
1913 /* Init DMA config if supported */
1914 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
1915 STM32F7_I2C_TXDR,
1916 STM32F7_I2C_RXDR);
1917 if (PTR_ERR(i2c_dev->dma) == -ENODEV)
1918 i2c_dev->dma = NULL;
1919 else if (IS_ERR(i2c_dev->dma)) {
1920 ret = PTR_ERR(i2c_dev->dma);
1921 if (ret != -EPROBE_DEFER)
1922 dev_err(&pdev->dev,
1923 "Failed to request dma error %i\n", ret);
1924 goto clk_free;
1925 }
1926
1927 ret = i2c_add_adapter(adap);
1928 if (ret)
1929 goto clk_free;
1930
1931 platform_set_drvdata(pdev, i2c_dev);
1932
1933 clk_disable(i2c_dev->clk);
1934
1935 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
1936
1937 return 0;
1938
1939 clk_free:
1940 clk_disable_unprepare(i2c_dev->clk);
1941
1942 return ret;
1943 }
1944
stm32f7_i2c_remove(struct platform_device * pdev)1945 static int stm32f7_i2c_remove(struct platform_device *pdev)
1946 {
1947 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1948
1949 if (i2c_dev->dma) {
1950 stm32_i2c_dma_free(i2c_dev->dma);
1951 i2c_dev->dma = NULL;
1952 }
1953
1954 i2c_del_adapter(&i2c_dev->adap);
1955
1956 clk_unprepare(i2c_dev->clk);
1957
1958 return 0;
1959 }
1960
1961 static const struct of_device_id stm32f7_i2c_match[] = {
1962 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
1963 {},
1964 };
1965 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
1966
1967 static struct platform_driver stm32f7_i2c_driver = {
1968 .driver = {
1969 .name = "stm32f7-i2c",
1970 .of_match_table = stm32f7_i2c_match,
1971 },
1972 .probe = stm32f7_i2c_probe,
1973 .remove = stm32f7_i2c_remove,
1974 };
1975
1976 module_platform_driver(stm32f7_i2c_driver);
1977
1978 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
1979 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
1980 MODULE_LICENSE("GPL v2");
1981