Lines Matching +full:clk +full:- +full:phase +full:-
2 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
4 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
26 #include "sdhci-pltfm.h"
114 #define INVALID_TUNING_PHASE -1
129 msm_host->var_ops->msm_readl_relaxed(host, offset)
132 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
244 struct clk *bus_clk; /* SDHC bus voter clock */
245 struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
272 return msm_host->offset; in sdhci_priv_msm_offset()
285 return readl_relaxed(msm_host->core_mem + offset); in sdhci_msm_mci_variant_readl_relaxed()
291 return readl_relaxed(host->ioaddr + offset); in sdhci_msm_v5_variant_readl_relaxed()
300 writel_relaxed(val, msm_host->core_mem + offset); in sdhci_msm_mci_variant_writel_relaxed()
306 writel_relaxed(val, host->ioaddr + offset); in sdhci_msm_v5_variant_writel_relaxed()
312 struct mmc_ios ios = host->mmc->ios; in msm_get_clock_rate_for_bus_mode()
322 host->flags & SDHCI_HS400_TUNING) in msm_get_clock_rate_for_bus_mode()
332 struct mmc_ios curr_ios = host->mmc->ios; in msm_set_clock_rate_for_bus_mode()
333 struct clk *core_clk = msm_host->bulk_clks[0].clk; in msm_set_clock_rate_for_bus_mode()
340 mmc_hostname(host->mmc), clock, in msm_set_clock_rate_for_bus_mode()
344 msm_host->clk_rate = clock; in msm_set_clock_rate_for_bus_mode()
346 mmc_hostname(host->mmc), clk_get_rate(core_clk), in msm_set_clock_rate_for_bus_mode()
355 struct mmc_host *mmc = host->mmc; in msm_dll_poll_ck_out_en()
360 ck_out_en = !!(readl_relaxed(host->ioaddr + in msm_dll_poll_ck_out_en()
361 msm_offset->core_dll_config) & CORE_CK_OUT_EN); in msm_dll_poll_ck_out_en()
364 if (--wait_cnt == 0) { in msm_dll_poll_ck_out_en()
367 return -ETIMEDOUT; in msm_dll_poll_ck_out_en()
371 ck_out_en = !!(readl_relaxed(host->ioaddr + in msm_dll_poll_ck_out_en()
372 msm_offset->core_dll_config) & CORE_CK_OUT_EN); in msm_dll_poll_ck_out_en()
378 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase) in msm_config_cm_dll_phase() argument
387 struct mmc_host *mmc = host->mmc; in msm_config_cm_dll_phase()
391 if (phase > 0xf) in msm_config_cm_dll_phase()
392 return -EINVAL; in msm_config_cm_dll_phase()
394 spin_lock_irqsave(&host->lock, flags); in msm_config_cm_dll_phase()
396 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
399 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
407 * Write the selected DLL clock output phase (0 ... 15) in msm_config_cm_dll_phase()
410 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
412 config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT; in msm_config_cm_dll_phase()
413 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
415 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
417 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
424 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
427 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_config_cm_dll_phase()
431 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n", in msm_config_cm_dll_phase()
432 mmc_hostname(mmc), phase); in msm_config_cm_dll_phase()
434 spin_unlock_irqrestore(&host->lock, flags); in msm_config_cm_dll_phase()
441 * setting for SD3.0 UHS-I card read operation (in SDR104
445 * selected DLL clock output phase.
457 struct mmc_host *mmc = host->mmc; in msm_find_most_appropriate_phase()
462 return -EINVAL; in msm_find_most_appropriate_phase()
472 /* check if next phase in phase_table is consecutive or not */ in msm_find_most_appropriate_phase()
480 return -EINVAL; in msm_find_most_appropriate_phase()
482 /* Check if phase-0 is present in first valid window? */ in msm_find_most_appropriate_phase()
502 /* number of phases in raw where phase 0 is present */ in msm_find_most_appropriate_phase()
504 /* number of phases in raw where phase 15 is present */ in msm_find_most_appropriate_phase()
509 * If there are more than 1 phase windows then total in msm_find_most_appropriate_phase()
513 return -EINVAL; in msm_find_most_appropriate_phase()
537 i--; in msm_find_most_appropriate_phase()
542 ret = -EINVAL; in msm_find_most_appropriate_phase()
543 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n", in msm_find_most_appropriate_phase()
557 if (host->clock <= 112000000) in msm_cm_dll_set_freq()
559 else if (host->clock <= 125000000) in msm_cm_dll_set_freq()
561 else if (host->clock <= 137000000) in msm_cm_dll_set_freq()
563 else if (host->clock <= 150000000) in msm_cm_dll_set_freq()
565 else if (host->clock <= 162000000) in msm_cm_dll_set_freq()
567 else if (host->clock <= 175000000) in msm_cm_dll_set_freq()
569 else if (host->clock <= 187000000) in msm_cm_dll_set_freq()
571 else if (host->clock <= 200000000) in msm_cm_dll_set_freq()
574 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in msm_cm_dll_set_freq()
577 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in msm_cm_dll_set_freq()
583 struct mmc_host *mmc = host->mmc; in msm_init_cm_dll()
590 msm_host->offset; in msm_init_cm_dll()
592 if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk)) in msm_init_cm_dll()
593 xo_clk = clk_get_rate(msm_host->xo_clk); in msm_init_cm_dll()
595 spin_lock_irqsave(&host->lock, flags); in msm_init_cm_dll()
602 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_init_cm_dll()
604 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); in msm_init_cm_dll()
606 if (msm_host->use_14lpp_dll_reset) { in msm_init_cm_dll()
607 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
608 msm_offset->core_dll_config); in msm_init_cm_dll()
610 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
611 msm_offset->core_dll_config); in msm_init_cm_dll()
613 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
614 msm_offset->core_dll_config_2); in msm_init_cm_dll()
616 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
617 msm_offset->core_dll_config_2); in msm_init_cm_dll()
620 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
621 msm_offset->core_dll_config); in msm_init_cm_dll()
623 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
624 msm_offset->core_dll_config); in msm_init_cm_dll()
626 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
627 msm_offset->core_dll_config); in msm_init_cm_dll()
629 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
630 msm_offset->core_dll_config); in msm_init_cm_dll()
633 if (msm_host->use_14lpp_dll_reset && in msm_init_cm_dll()
634 !IS_ERR_OR_NULL(msm_host->xo_clk)) { in msm_init_cm_dll()
637 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
638 msm_offset->core_dll_config_2); in msm_init_cm_dll()
641 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8), in msm_init_cm_dll()
644 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4), in msm_init_cm_dll()
647 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
648 msm_offset->core_dll_config_2); in msm_init_cm_dll()
652 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
653 msm_offset->core_dll_config_2); in msm_init_cm_dll()
658 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
659 msm_offset->core_dll_config); in msm_init_cm_dll()
661 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
662 msm_offset->core_dll_config); in msm_init_cm_dll()
664 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
665 msm_offset->core_dll_config); in msm_init_cm_dll()
667 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
668 msm_offset->core_dll_config); in msm_init_cm_dll()
670 if (msm_host->use_14lpp_dll_reset) { in msm_init_cm_dll()
672 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
673 msm_offset->core_dll_config_2); in msm_init_cm_dll()
675 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
676 msm_offset->core_dll_config_2); in msm_init_cm_dll()
679 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
680 msm_offset->core_dll_config); in msm_init_cm_dll()
682 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
683 msm_offset->core_dll_config); in msm_init_cm_dll()
685 config = readl_relaxed(host->ioaddr + in msm_init_cm_dll()
686 msm_offset->core_dll_config); in msm_init_cm_dll()
688 writel_relaxed(config, host->ioaddr + in msm_init_cm_dll()
689 msm_offset->core_dll_config); in msm_init_cm_dll()
692 while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) & in msm_init_cm_dll()
695 if (--wait_cnt == 0) { in msm_init_cm_dll()
698 spin_unlock_irqrestore(&host->lock, flags); in msm_init_cm_dll()
699 return -ETIMEDOUT; in msm_init_cm_dll()
704 spin_unlock_irqrestore(&host->lock, flags); in msm_init_cm_dll()
714 msm_host->offset; in msm_hc_select_default()
716 if (!msm_host->use_cdclp533) { in msm_hc_select_default()
717 config = readl_relaxed(host->ioaddr + in msm_hc_select_default()
718 msm_offset->core_vendor_spec3); in msm_hc_select_default()
720 writel_relaxed(config, host->ioaddr + in msm_hc_select_default()
721 msm_offset->core_vendor_spec3); in msm_hc_select_default()
724 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_default()
727 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_default()
736 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_default()
739 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_default()
752 struct mmc_ios ios = host->mmc->ios; in msm_hc_select_hs400()
756 msm_host->offset; in msm_hc_select_hs400()
759 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_hs400()
763 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); in msm_hc_select_hs400()
768 if ((msm_host->tuning_done || ios.enhanced_strobe) && in msm_hc_select_hs400()
769 !msm_host->calibration_done) { in msm_hc_select_hs400()
770 config = readl_relaxed(host->ioaddr + in msm_hc_select_hs400()
771 msm_offset->core_vendor_spec); in msm_hc_select_hs400()
774 writel_relaxed(config, host->ioaddr + in msm_hc_select_hs400()
775 msm_offset->core_vendor_spec); in msm_hc_select_hs400()
777 if (!msm_host->clk_rate && !msm_host->use_cdclp533) { in msm_hc_select_hs400()
783 rc = readl_relaxed_poll_timeout(host->ioaddr + in msm_hc_select_hs400()
784 msm_offset->core_dll_status, in msm_hc_select_hs400()
790 if (rc == -ETIMEDOUT) in msm_hc_select_hs400()
792 mmc_hostname(host->mmc), dll_lock); in msm_hc_select_hs400()
802 * sdhci_msm_hc_select_mode :- In general all timing modes are
807 * HS200 - SDR104 (Since they both are equivalent in functionality)
808 * HS400 - This involves multiple configurations
809 * Initially SDR104 - when tuning is required as HS200
816 * HS400 - divided clock (free running MCLK/2)
817 * All other modes - default (free running MCLK)
821 struct mmc_ios ios = host->mmc->ios; in sdhci_msm_hc_select_mode()
824 host->flags & SDHCI_HS400_TUNING) in sdhci_msm_hc_select_mode()
837 msm_host->offset; in sdhci_msm_cdclp533_calibration()
839 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); in sdhci_msm_cdclp533_calibration()
843 * tuning block and restore the saved tuning phase. in sdhci_msm_cdclp533_calibration()
849 /* Set the selected phase in delay line hw block */ in sdhci_msm_cdclp533_calibration()
850 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase); in sdhci_msm_cdclp533_calibration()
854 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); in sdhci_msm_cdclp533_calibration()
856 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); in sdhci_msm_cdclp533_calibration()
858 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
860 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
862 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG); in sdhci_msm_cdclp533_calibration()
864 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG); in sdhci_msm_cdclp533_calibration()
866 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG); in sdhci_msm_cdclp533_calibration()
868 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG); in sdhci_msm_cdclp533_calibration()
870 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
872 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
876 writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
877 writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1); in sdhci_msm_cdclp533_calibration()
878 writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); in sdhci_msm_cdclp533_calibration()
879 writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1); in sdhci_msm_cdclp533_calibration()
880 writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG); in sdhci_msm_cdclp533_calibration()
881 writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG); in sdhci_msm_cdclp533_calibration()
882 writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG); in sdhci_msm_cdclp533_calibration()
883 writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG); in sdhci_msm_cdclp533_calibration()
884 writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG); in sdhci_msm_cdclp533_calibration()
888 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
890 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
892 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
894 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
896 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
898 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); in sdhci_msm_cdclp533_calibration()
900 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); in sdhci_msm_cdclp533_calibration()
902 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); in sdhci_msm_cdclp533_calibration()
904 ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0, in sdhci_msm_cdclp533_calibration()
909 if (ret == -ETIMEDOUT) { in sdhci_msm_cdclp533_calibration()
911 mmc_hostname(host->mmc), __func__); in sdhci_msm_cdclp533_calibration()
915 ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0) in sdhci_msm_cdclp533_calibration()
919 mmc_hostname(host->mmc), __func__, ret); in sdhci_msm_cdclp533_calibration()
920 ret = -EINVAL; in sdhci_msm_cdclp533_calibration()
924 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
926 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg); in sdhci_msm_cdclp533_calibration()
928 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), in sdhci_msm_cdclp533_calibration()
935 struct mmc_host *mmc = host->mmc; in sdhci_msm_cm_dll_sdc4_calibration()
943 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); in sdhci_msm_cm_dll_sdc4_calibration()
952 if (msm_host->updated_ddr_cfg) in sdhci_msm_cm_dll_sdc4_calibration()
953 ddr_cfg_offset = msm_offset->core_ddr_config; in sdhci_msm_cm_dll_sdc4_calibration()
955 ddr_cfg_offset = msm_offset->core_ddr_config_old; in sdhci_msm_cm_dll_sdc4_calibration()
956 writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + ddr_cfg_offset); in sdhci_msm_cm_dll_sdc4_calibration()
958 if (mmc->ios.enhanced_strobe) { in sdhci_msm_cm_dll_sdc4_calibration()
959 config = readl_relaxed(host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
960 msm_offset->core_ddr_200_cfg); in sdhci_msm_cm_dll_sdc4_calibration()
962 writel_relaxed(config, host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
963 msm_offset->core_ddr_200_cfg); in sdhci_msm_cm_dll_sdc4_calibration()
966 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2); in sdhci_msm_cm_dll_sdc4_calibration()
968 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2); in sdhci_msm_cm_dll_sdc4_calibration()
970 ret = readl_relaxed_poll_timeout(host->ioaddr + in sdhci_msm_cm_dll_sdc4_calibration()
971 msm_offset->core_dll_status, in sdhci_msm_cm_dll_sdc4_calibration()
976 if (ret == -ETIMEDOUT) { in sdhci_msm_cm_dll_sdc4_calibration()
978 mmc_hostname(host->mmc), __func__); in sdhci_msm_cm_dll_sdc4_calibration()
982 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3); in sdhci_msm_cm_dll_sdc4_calibration()
984 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec3); in sdhci_msm_cm_dll_sdc4_calibration()
992 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), in sdhci_msm_cm_dll_sdc4_calibration()
1001 struct mmc_host *mmc = host->mmc; in sdhci_msm_hs400_dll_calibration()
1005 msm_host->offset; in sdhci_msm_hs400_dll_calibration()
1007 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); in sdhci_msm_hs400_dll_calibration()
1011 * tuning block and restore the saved tuning phase. in sdhci_msm_hs400_dll_calibration()
1017 if (!mmc->ios.enhanced_strobe) { in sdhci_msm_hs400_dll_calibration()
1018 /* Set the selected phase in delay line hw block */ in sdhci_msm_hs400_dll_calibration()
1020 msm_host->saved_tuning_phase); in sdhci_msm_hs400_dll_calibration()
1023 config = readl_relaxed(host->ioaddr + in sdhci_msm_hs400_dll_calibration()
1024 msm_offset->core_dll_config); in sdhci_msm_hs400_dll_calibration()
1026 writel_relaxed(config, host->ioaddr + in sdhci_msm_hs400_dll_calibration()
1027 msm_offset->core_dll_config); in sdhci_msm_hs400_dll_calibration()
1030 if (msm_host->use_cdclp533) in sdhci_msm_hs400_dll_calibration()
1035 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), in sdhci_msm_hs400_dll_calibration()
1043 u32 config, oldconfig = readl_relaxed(host->ioaddr + in sdhci_msm_set_cdr()
1044 msm_offset->core_dll_config); in sdhci_msm_set_cdr()
1056 writel_relaxed(config, host->ioaddr + in sdhci_msm_set_cdr()
1057 msm_offset->core_dll_config); in sdhci_msm_set_cdr()
1064 u8 phase, tuned_phases[16], tuned_phase_cnt = 0; in sdhci_msm_execute_tuning() local
1066 struct mmc_ios ios = host->mmc->ios; in sdhci_msm_execute_tuning()
1074 if (host->clock <= CORE_FREQ_100MHZ || in sdhci_msm_execute_tuning()
1078 msm_host->use_cdr = false; in sdhci_msm_execute_tuning()
1083 /* Clock-Data-Recovery used to dynamically adjust RX sampling point */ in sdhci_msm_execute_tuning()
1084 msm_host->use_cdr = true; in sdhci_msm_execute_tuning()
1090 msm_host->tuning_done = 0; in sdhci_msm_execute_tuning()
1094 * - select MCLK/2 in VENDOR_SPEC in sdhci_msm_execute_tuning()
1095 * - program MCLK to 400MHz (or nearest supported) in GCC in sdhci_msm_execute_tuning()
1097 if (host->flags & SDHCI_HS400_TUNING) { in sdhci_msm_execute_tuning()
1100 host->flags &= ~SDHCI_HS400_TUNING; in sdhci_msm_execute_tuning()
1109 phase = 0; in sdhci_msm_execute_tuning()
1111 /* Set the phase in delay line hw block */ in sdhci_msm_execute_tuning()
1112 rc = msm_config_cm_dll_phase(host, phase); in sdhci_msm_execute_tuning()
1116 msm_host->saved_tuning_phase = phase; in sdhci_msm_execute_tuning()
1120 tuned_phases[tuned_phase_cnt++] = phase; in sdhci_msm_execute_tuning()
1121 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n", in sdhci_msm_execute_tuning()
1122 mmc_hostname(mmc), phase); in sdhci_msm_execute_tuning()
1124 } while (++phase < ARRAY_SIZE(tuned_phases)); in sdhci_msm_execute_tuning()
1133 * we get a good phase. Better to try a few times. in sdhci_msm_execute_tuning()
1137 if (--tuning_seq_cnt) { in sdhci_msm_execute_tuning()
1148 phase = rc; in sdhci_msm_execute_tuning()
1151 * Finally set the selected phase in delay in sdhci_msm_execute_tuning()
1154 rc = msm_config_cm_dll_phase(host, phase); in sdhci_msm_execute_tuning()
1157 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n", in sdhci_msm_execute_tuning()
1158 mmc_hostname(mmc), phase); in sdhci_msm_execute_tuning()
1160 if (--tuning_seq_cnt) in sdhci_msm_execute_tuning()
1165 rc = -EIO; in sdhci_msm_execute_tuning()
1169 msm_host->tuning_done = true; in sdhci_msm_execute_tuning()
1174 * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
1185 if (host->clock > CORE_FREQ_100MHZ && in sdhci_msm_hs400()
1186 (msm_host->tuning_done || ios->enhanced_strobe) && in sdhci_msm_hs400()
1187 !msm_host->calibration_done) { in sdhci_msm_hs400()
1190 msm_host->calibration_done = true; in sdhci_msm_hs400()
1193 mmc_hostname(host->mmc), ret); in sdhci_msm_hs400()
1200 struct mmc_host *mmc = host->mmc; in sdhci_msm_set_uhs_signaling()
1206 msm_host->offset; in sdhci_msm_set_uhs_signaling()
1238 if (host->clock <= CORE_FREQ_100MHZ) { in sdhci_msm_set_uhs_signaling()
1247 config = readl_relaxed(host->ioaddr + in sdhci_msm_set_uhs_signaling()
1248 msm_offset->core_dll_config); in sdhci_msm_set_uhs_signaling()
1250 writel_relaxed(config, host->ioaddr + in sdhci_msm_set_uhs_signaling()
1251 msm_offset->core_dll_config); in sdhci_msm_set_uhs_signaling()
1253 config = readl_relaxed(host->ioaddr + in sdhci_msm_set_uhs_signaling()
1254 msm_offset->core_dll_config); in sdhci_msm_set_uhs_signaling()
1256 writel_relaxed(config, host->ioaddr + in sdhci_msm_set_uhs_signaling()
1257 msm_offset->core_dll_config); in sdhci_msm_set_uhs_signaling()
1263 msm_host->calibration_done = false; in sdhci_msm_set_uhs_signaling()
1267 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2); in sdhci_msm_set_uhs_signaling()
1270 if (mmc->ios.timing == MMC_TIMING_MMC_HS400) in sdhci_msm_set_uhs_signaling()
1271 sdhci_msm_hs400(host, &mmc->ios); in sdhci_msm_set_uhs_signaling()
1276 init_waitqueue_head(&msm_host->pwr_irq_wait); in sdhci_msm_init_pwr_irq_wait()
1282 wake_up(&msm_host->pwr_irq_wait); in sdhci_msm_complete_pwr_irq_wait()
1301 msm_host->offset; in sdhci_msm_check_power_status()
1304 mmc_hostname(host->mmc), __func__, req_type, in sdhci_msm_check_power_status()
1305 msm_host->curr_pwr_state, msm_host->curr_io_level); in sdhci_msm_check_power_status()
1310 * Since sdhci-msm-v5, this bit has been removed and SW must consider in sdhci_msm_check_power_status()
1313 if (!msm_host->mci_removed) in sdhci_msm_check_power_status()
1315 msm_offset->core_generics); in sdhci_msm_check_power_status()
1322 * The IRQ for request type IO High/LOW will be generated when - in sdhci_msm_check_power_status()
1330 * for host->pwr to handle a case where IO voltage high request is in sdhci_msm_check_power_status()
1333 if ((req_type & REQ_IO_HIGH) && !host->pwr) { in sdhci_msm_check_power_status()
1335 mmc_hostname(host->mmc), req_type); in sdhci_msm_check_power_status()
1338 if ((req_type & msm_host->curr_pwr_state) || in sdhci_msm_check_power_status()
1339 (req_type & msm_host->curr_io_level)) in sdhci_msm_check_power_status()
1348 if (!wait_event_timeout(msm_host->pwr_irq_wait, in sdhci_msm_check_power_status()
1349 msm_host->pwr_irq_flag, in sdhci_msm_check_power_status()
1351 dev_warn(&msm_host->pdev->dev, in sdhci_msm_check_power_status()
1353 mmc_hostname(host->mmc), req_type); in sdhci_msm_check_power_status()
1355 pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc), in sdhci_msm_check_power_status()
1364 msm_host->offset; in sdhci_msm_dump_pwr_ctrl_regs()
1367 mmc_hostname(host->mmc), in sdhci_msm_dump_pwr_ctrl_regs()
1368 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status), in sdhci_msm_dump_pwr_ctrl_regs()
1369 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask), in sdhci_msm_dump_pwr_ctrl_regs()
1370 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl)); in sdhci_msm_dump_pwr_ctrl_regs()
1381 const struct sdhci_msm_offset *msm_offset = msm_host->offset; in sdhci_msm_handle_pwr_irq()
1384 msm_offset->core_pwrctl_status); in sdhci_msm_handle_pwr_irq()
1388 msm_offset->core_pwrctl_clear); in sdhci_msm_handle_pwr_irq()
1398 msm_offset->core_pwrctl_status)) { in sdhci_msm_handle_pwr_irq()
1401 mmc_hostname(host->mmc), irq_status); in sdhci_msm_handle_pwr_irq()
1407 msm_offset->core_pwrctl_clear); in sdhci_msm_handle_pwr_irq()
1408 retry--; in sdhci_msm_handle_pwr_irq()
1439 msm_offset->core_pwrctl_ctl); in sdhci_msm_handle_pwr_irq()
1445 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) { in sdhci_msm_handle_pwr_irq()
1458 config = readl_relaxed(host->ioaddr + in sdhci_msm_handle_pwr_irq()
1459 msm_offset->core_vendor_spec); in sdhci_msm_handle_pwr_irq()
1463 (msm_host->caps_0 & CORE_3_0V_SUPPORT)) in sdhci_msm_handle_pwr_irq()
1466 (msm_host->caps_0 & CORE_1_8V_SUPPORT)) in sdhci_msm_handle_pwr_irq()
1470 writel_relaxed(new_config, host->ioaddr + in sdhci_msm_handle_pwr_irq()
1471 msm_offset->core_vendor_spec); in sdhci_msm_handle_pwr_irq()
1475 msm_host->curr_pwr_state = pwr_state; in sdhci_msm_handle_pwr_irq()
1477 msm_host->curr_io_level = io_level; in sdhci_msm_handle_pwr_irq()
1480 mmc_hostname(msm_host->mmc), __func__, irq, irq_status, in sdhci_msm_handle_pwr_irq()
1491 msm_host->pwr_irq_flag = 1; in sdhci_msm_pwr_irq()
1502 struct clk *core_clk = msm_host->bulk_clks[0].clk; in sdhci_msm_get_max_clock()
1513 * __sdhci_msm_set_clock - sdhci_msm clock control.
1522 u16 clk; in __sdhci_msm_set_clock() local
1524 * Keep actual_clock as zero - in __sdhci_msm_set_clock()
1525 * - since there is no divider used so no need of having actual_clock. in __sdhci_msm_set_clock()
1526 * - MSM controller uses SDCLK for data timeout calculation. If in __sdhci_msm_set_clock()
1527 * actual_clock is zero, host->clock is taken for calculation. in __sdhci_msm_set_clock()
1529 host->mmc->actual_clock = 0; in __sdhci_msm_set_clock()
1541 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); in __sdhci_msm_set_clock()
1542 sdhci_enable_clk(host, clk); in __sdhci_msm_set_clock()
1545 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1552 msm_host->clk_rate = clock; in sdhci_msm_set_clock()
1582 if (host->pwr && (val & SDHCI_RESET_ALL)) in __sdhci_msm_check_write()
1589 msm_host->transfer_mode = val; in __sdhci_msm_check_write()
1592 if (!msm_host->use_cdr) in __sdhci_msm_check_write()
1594 if ((msm_host->transfer_mode & SDHCI_TRNS_READ) && in __sdhci_msm_check_write()
1604 msm_host->pwr_irq_flag = 0; in __sdhci_msm_check_write()
1620 writew_relaxed(val, host->ioaddr + reg); in sdhci_msm_writew()
1633 writeb_relaxed(val, host->ioaddr + reg); in sdhci_msm_writeb()
1641 struct mmc_host *mmc = msm_host->mmc; in sdhci_msm_set_regulator_caps()
1642 struct regulator *supply = mmc->supply.vqmmc; in sdhci_msm_set_regulator_caps()
1645 const struct sdhci_msm_offset *msm_offset = msm_host->offset; in sdhci_msm_set_regulator_caps()
1647 if (!IS_ERR(mmc->supply.vqmmc)) { in sdhci_msm_set_regulator_caps()
1663 u32 io_level = msm_host->curr_io_level; in sdhci_msm_set_regulator_caps()
1665 config = readl_relaxed(host->ioaddr + in sdhci_msm_set_regulator_caps()
1666 msm_offset->core_vendor_spec); in sdhci_msm_set_regulator_caps()
1675 host->ioaddr + msm_offset->core_vendor_spec); in sdhci_msm_set_regulator_caps()
1677 msm_host->caps_0 |= caps; in sdhci_msm_set_regulator_caps()
1704 {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var},
1705 {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var},
1738 struct clk *clk; in sdhci_msm_probe() local
1750 host->sdma_boundary = 0; in sdhci_msm_probe()
1753 msm_host->mmc = host->mmc; in sdhci_msm_probe()
1754 msm_host->pdev = pdev; in sdhci_msm_probe()
1756 ret = mmc_of_parse(host->mmc); in sdhci_msm_probe()
1764 var_info = of_device_get_match_data(&pdev->dev); in sdhci_msm_probe()
1766 msm_host->mci_removed = var_info->mci_removed; in sdhci_msm_probe()
1767 msm_host->var_ops = var_info->var_ops; in sdhci_msm_probe()
1768 msm_host->offset = var_info->offset; in sdhci_msm_probe()
1770 msm_offset = msm_host->offset; in sdhci_msm_probe()
1774 msm_host->saved_tuning_phase = INVALID_TUNING_PHASE; in sdhci_msm_probe()
1777 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus"); in sdhci_msm_probe()
1778 if (!IS_ERR(msm_host->bus_clk)) { in sdhci_msm_probe()
1779 /* Vote for max. clk rate for max. performance */ in sdhci_msm_probe()
1780 ret = clk_set_rate(msm_host->bus_clk, INT_MAX); in sdhci_msm_probe()
1783 ret = clk_prepare_enable(msm_host->bus_clk); in sdhci_msm_probe()
1789 clk = devm_clk_get(&pdev->dev, "iface"); in sdhci_msm_probe()
1790 if (IS_ERR(clk)) { in sdhci_msm_probe()
1791 ret = PTR_ERR(clk); in sdhci_msm_probe()
1792 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret); in sdhci_msm_probe()
1795 msm_host->bulk_clks[1].clk = clk; in sdhci_msm_probe()
1798 clk = devm_clk_get(&pdev->dev, "core"); in sdhci_msm_probe()
1799 if (IS_ERR(clk)) { in sdhci_msm_probe()
1800 ret = PTR_ERR(clk); in sdhci_msm_probe()
1801 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret); in sdhci_msm_probe()
1804 msm_host->bulk_clks[0].clk = clk; in sdhci_msm_probe()
1807 ret = clk_set_rate(clk, INT_MAX); in sdhci_msm_probe()
1809 dev_warn(&pdev->dev, "core clock boost failed\n"); in sdhci_msm_probe()
1811 clk = devm_clk_get(&pdev->dev, "cal"); in sdhci_msm_probe()
1812 if (IS_ERR(clk)) in sdhci_msm_probe()
1813 clk = NULL; in sdhci_msm_probe()
1814 msm_host->bulk_clks[2].clk = clk; in sdhci_msm_probe()
1816 clk = devm_clk_get(&pdev->dev, "sleep"); in sdhci_msm_probe()
1817 if (IS_ERR(clk)) in sdhci_msm_probe()
1818 clk = NULL; in sdhci_msm_probe()
1819 msm_host->bulk_clks[3].clk = clk; in sdhci_msm_probe()
1821 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_probe()
1822 msm_host->bulk_clks); in sdhci_msm_probe()
1830 msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo"); in sdhci_msm_probe()
1831 if (IS_ERR(msm_host->xo_clk)) { in sdhci_msm_probe()
1832 ret = PTR_ERR(msm_host->xo_clk); in sdhci_msm_probe()
1833 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret); in sdhci_msm_probe()
1836 if (!msm_host->mci_removed) { in sdhci_msm_probe()
1838 msm_host->core_mem = devm_ioremap_resource(&pdev->dev, in sdhci_msm_probe()
1841 if (IS_ERR(msm_host->core_mem)) { in sdhci_msm_probe()
1842 ret = PTR_ERR(msm_host->core_mem); in sdhci_msm_probe()
1849 host->ioaddr + msm_offset->core_vendor_spec); in sdhci_msm_probe()
1851 if (!msm_host->mci_removed) { in sdhci_msm_probe()
1854 msm_offset->core_hc_mode); in sdhci_msm_probe()
1856 msm_offset->core_hc_mode); in sdhci_msm_probe()
1859 msm_offset->core_hc_mode); in sdhci_msm_probe()
1862 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION)); in sdhci_msm_probe()
1863 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n", in sdhci_msm_probe()
1868 msm_offset->core_mci_version); in sdhci_msm_probe()
1872 dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n", in sdhci_msm_probe()
1876 msm_host->use_14lpp_dll_reset = true; in sdhci_msm_probe()
1883 msm_host->use_cdclp533 = true; in sdhci_msm_probe()
1890 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES); in sdhci_msm_probe()
1892 writel_relaxed(config, host->ioaddr + in sdhci_msm_probe()
1893 msm_offset->core_vendor_spec_capabilities0); in sdhci_msm_probe()
1897 msm_host->updated_ddr_cfg = true; in sdhci_msm_probe()
1915 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); in sdhci_msm_probe()
1916 if (msm_host->pwr_irq < 0) { in sdhci_msm_probe()
1917 dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n", in sdhci_msm_probe()
1918 msm_host->pwr_irq); in sdhci_msm_probe()
1919 ret = msm_host->pwr_irq; in sdhci_msm_probe()
1926 msm_offset->core_pwrctl_mask); in sdhci_msm_probe()
1928 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL, in sdhci_msm_probe()
1930 dev_name(&pdev->dev), host); in sdhci_msm_probe()
1932 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret); in sdhci_msm_probe()
1936 msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY; in sdhci_msm_probe()
1938 pm_runtime_get_noresume(&pdev->dev); in sdhci_msm_probe()
1939 pm_runtime_set_active(&pdev->dev); in sdhci_msm_probe()
1940 pm_runtime_enable(&pdev->dev); in sdhci_msm_probe()
1941 pm_runtime_set_autosuspend_delay(&pdev->dev, in sdhci_msm_probe()
1943 pm_runtime_use_autosuspend(&pdev->dev); in sdhci_msm_probe()
1945 host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning; in sdhci_msm_probe()
1951 pm_runtime_mark_last_busy(&pdev->dev); in sdhci_msm_probe()
1952 pm_runtime_put_autosuspend(&pdev->dev); in sdhci_msm_probe()
1957 pm_runtime_disable(&pdev->dev); in sdhci_msm_probe()
1958 pm_runtime_set_suspended(&pdev->dev); in sdhci_msm_probe()
1959 pm_runtime_put_noidle(&pdev->dev); in sdhci_msm_probe()
1961 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_probe()
1962 msm_host->bulk_clks); in sdhci_msm_probe()
1964 if (!IS_ERR(msm_host->bus_clk)) in sdhci_msm_probe()
1965 clk_disable_unprepare(msm_host->bus_clk); in sdhci_msm_probe()
1976 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == in sdhci_msm_remove()
1981 pm_runtime_get_sync(&pdev->dev); in sdhci_msm_remove()
1982 pm_runtime_disable(&pdev->dev); in sdhci_msm_remove()
1983 pm_runtime_put_noidle(&pdev->dev); in sdhci_msm_remove()
1985 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_remove()
1986 msm_host->bulk_clks); in sdhci_msm_remove()
1987 if (!IS_ERR(msm_host->bus_clk)) in sdhci_msm_remove()
1988 clk_disable_unprepare(msm_host->bus_clk); in sdhci_msm_remove()
2000 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_runtime_suspend()
2001 msm_host->bulk_clks); in sdhci_msm_runtime_suspend()
2012 return clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_runtime_resume()
2013 msm_host->bulk_clks); in sdhci_msm_runtime_resume()