1 // SPDX-License-Identifier: GPL-2.0
3 // flexcan.c - FLEXCAN CAN controller driver
5 // Copyright (c) 2005-2006 Varma Electronics Oy
7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
10 // Based on code originally by Andrey Volkov <avolkov@varma-el.com>
17 #include <linux/can/rx-offload.h>
28 #define DRV_NAME			"flexcan"
33 /* FLEXCAN module configuration register (CANMCR) bits */
59 /* FLEXCAN control register (CANCTRL) bits */
83 /* FLEXCAN control register 2 (CTRL2) bits */
92 /* FLEXCAN memory error control register (MECR) bits */
104 /* FLEXCAN error and status register (ESR) bits */
136 /* FLEXCAN interrupt flag register (IFLAG) bits */
142 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_LAST	(FLEXCAN_TX_MB - 1)
148 /* FLEXCAN message buffers */
170 /* FLEXCAN hardware feature flags
173  *    SOC   Version   IP-Version  Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
227 	/* FIFO-mode:
230 	 * 0x090...0x0df	1-5	reserverd
231 	 * 0x0e0...0x0ff	6-7	8 entry ID table
233 	 * 0x0e0...0x2df	6-7..37	8..128 entry ID table
240 	u32 gfwr_mx6;		/* 0x9e0 - MX6 */
320 /* FlexCAN module is essentially modelled as a little-endian IP in most
322  * implemented in a little-endian fashion.
324  * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
325  * module in a big-endian fashion (i.e the registers as well as the
326  * message buffer areas are implemented in a big-endian way).
328  * In addition, the FlexCAN module can be found on SoCs having ARM or
355 	struct flexcan_regs __iomem *regs = priv->regs;  in flexcan_error_irq_enable()
356 	u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);  in flexcan_error_irq_enable()
358 	priv->write(reg_ctrl, &regs->ctrl);  in flexcan_error_irq_enable()
363 	struct flexcan_regs __iomem *regs = priv->regs;  in flexcan_error_irq_disable()
364 	u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);  in flexcan_error_irq_disable()
366 	priv->write(reg_ctrl, &regs->ctrl);  in flexcan_error_irq_disable()
371 	if (!priv->reg_xceiver)  in flexcan_transceiver_enable()
374 	return regulator_enable(priv->reg_xceiver);  in flexcan_transceiver_enable()
379 	if (!priv->reg_xceiver)  in flexcan_transceiver_disable()
382 	return regulator_disable(priv->reg_xceiver);  in flexcan_transceiver_disable()
387 	struct flexcan_regs __iomem *regs = priv->regs;  in flexcan_chip_enable()
391 	reg = priv->read(&regs->mcr);  in flexcan_chip_enable()
393 	priv->write(reg, &regs->mcr);  in flexcan_chip_enable()
395 	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))  in flexcan_chip_enable()
398 	if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)  in flexcan_chip_enable()
399 		return -ETIMEDOUT;  in flexcan_chip_enable()
406 	struct flexcan_regs __iomem *regs = priv->regs;  in flexcan_chip_disable()
410 	reg = priv->read(&regs->mcr);  in flexcan_chip_disable()
412 	priv->write(reg, &regs->mcr);  in flexcan_chip_disable()
414 	while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))  in flexcan_chip_disable()
417 	if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))  in flexcan_chip_disable()
418 		return -ETIMEDOUT;  in flexcan_chip_disable()
425 	struct flexcan_regs __iomem *regs = priv->regs;  in flexcan_chip_freeze()
426 	unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;  in flexcan_chip_freeze()
429 	reg = priv->read(&regs->mcr);  in flexcan_chip_freeze()
431 	priv->write(reg, &regs->mcr);  in flexcan_chip_freeze()
433 	while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))  in flexcan_chip_freeze()
436 	if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))  in flexcan_chip_freeze()
437 		return -ETIMEDOUT;  in flexcan_chip_freeze()
444 	struct flexcan_regs __iomem *regs = priv->regs;  in flexcan_chip_unfreeze()
448 	reg = priv->read(&regs->mcr);  in flexcan_chip_unfreeze()
450 	priv->write(reg, &regs->mcr);  in flexcan_chip_unfreeze()
452 	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))  in flexcan_chip_unfreeze()
455 	if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)  in flexcan_chip_unfreeze()
456 		return -ETIMEDOUT;  in flexcan_chip_unfreeze()
463 	struct flexcan_regs __iomem *regs = priv->regs;  in flexcan_chip_softreset()
466 	priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);  in flexcan_chip_softreset()
467 	while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))  in flexcan_chip_softreset()
470 	if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)  in flexcan_chip_softreset()
471 		return -ETIMEDOUT;  in flexcan_chip_softreset()
480 	struct flexcan_regs __iomem *regs = priv->regs;  in __flexcan_get_berr_counter()
481 	u32 reg = priv->read(&regs->ecr);  in __flexcan_get_berr_counter()
483 	bec->txerr = (reg >> 0) & 0xff;  in __flexcan_get_berr_counter()
484 	bec->rxerr = (reg >> 8) & 0xff;  in __flexcan_get_berr_counter()
495 	err = clk_prepare_enable(priv->clk_ipg);  in flexcan_get_berr_counter()
499 	err = clk_prepare_enable(priv->clk_per);  in flexcan_get_berr_counter()
505 	clk_disable_unprepare(priv->clk_per);  in flexcan_get_berr_counter()
507 	clk_disable_unprepare(priv->clk_ipg);  in flexcan_get_berr_counter()
515 	struct flexcan_regs __iomem *regs = priv->regs;  in flexcan_start_xmit()
516 	struct can_frame *cf = (struct can_frame *)skb->data;  in flexcan_start_xmit()
519 	u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);  in flexcan_start_xmit()
526 	if (cf->can_id & CAN_EFF_FLAG) {  in flexcan_start_xmit()
527 		can_id = cf->can_id & CAN_EFF_MASK;  in flexcan_start_xmit()
530 		can_id = (cf->can_id & CAN_SFF_MASK) << 18;  in flexcan_start_xmit()
533 	if (cf->can_id & CAN_RTR_FLAG)  in flexcan_start_xmit()
536 	if (cf->can_dlc > 0) {  in flexcan_start_xmit()
537 		data = be32_to_cpup((__be32 *)&cf->data[0]);  in flexcan_start_xmit()
538 		priv->write(data, &regs->mb[FLEXCAN_TX_MB].data[0]);  in flexcan_start_xmit()
540 	if (cf->can_dlc > 4) {  in flexcan_start_xmit()
541 		data = be32_to_cpup((__be32 *)&cf->data[4]);  in flexcan_start_xmit()
542 		priv->write(data, &regs->mb[FLEXCAN_TX_MB].data[1]);  in flexcan_start_xmit()
547 	priv->write(can_id, &regs->mb[FLEXCAN_TX_MB].can_id);  in flexcan_start_xmit()
548 	priv->write(ctrl, &regs->mb[FLEXCAN_TX_MB].can_ctrl);  in flexcan_start_xmit()
553 	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,  in flexcan_start_xmit()
554 		      &priv->tx_mb_reserved->can_ctrl);  in flexcan_start_xmit()
555 	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,  in flexcan_start_xmit()
556 		      &priv->tx_mb_reserved->can_ctrl);  in flexcan_start_xmit()
564 	struct flexcan_regs __iomem *regs = priv->regs;  in flexcan_irq_bus_err()
571 	timestamp = priv->read(&regs->timer) << 16;  in flexcan_irq_bus_err()
577 	cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;  in flexcan_irq_bus_err()
581 		cf->data[2] |= CAN_ERR_PROT_BIT1;  in flexcan_irq_bus_err()
586 		cf->data[2] |= CAN_ERR_PROT_BIT0;  in flexcan_irq_bus_err()
591 		cf->can_id |= CAN_ERR_ACK;  in flexcan_irq_bus_err()
592 		cf->data[3] = CAN_ERR_PROT_LOC_ACK;  in flexcan_irq_bus_err()
597 		cf->data[2] |= CAN_ERR_PROT_BIT;  in flexcan_irq_bus_err()
598 		cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;  in flexcan_irq_bus_err()
603 		cf->data[2] |= CAN_ERR_PROT_FORM;  in flexcan_irq_bus_err()
608 		cf->data[2] |= CAN_ERR_PROT_STUFF;  in flexcan_irq_bus_err()
612 	priv->can.can_stats.bus_error++;  in flexcan_irq_bus_err()
614 		dev->stats.rx_errors++;  in flexcan_irq_bus_err()
616 		dev->stats.tx_errors++;  in flexcan_irq_bus_err()
618 	err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);  in flexcan_irq_bus_err()
620 		dev->stats.rx_fifo_errors++;  in flexcan_irq_bus_err()
626 	struct flexcan_regs __iomem *regs = priv->regs;  in flexcan_irq_state()
635 	timestamp = priv->read(&regs->timer) << 16;  in flexcan_irq_state()
653 	if (likely(new_state == priv->can.state))  in flexcan_irq_state()
665 	err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);  in flexcan_irq_state()
667 		dev->stats.rx_fifo_errors++;  in flexcan_irq_state()
680 	struct flexcan_regs __iomem *regs = priv->regs;  in flexcan_mailbox_read()
681 	struct flexcan_mb __iomem *mb = &regs->mb[n];  in flexcan_mailbox_read()
684 	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {  in flexcan_mailbox_read()
688 			reg_ctrl = priv->read(&mb->can_ctrl);  in flexcan_mailbox_read()
699 			offload->dev->stats.rx_over_errors++;  in flexcan_mailbox_read()
700 			offload->dev->stats.rx_errors++;  in flexcan_mailbox_read()
703 		reg_iflag1 = priv->read(&regs->iflag1);  in flexcan_mailbox_read()
707 		reg_ctrl = priv->read(&mb->can_ctrl);  in flexcan_mailbox_read()
713 	reg_id = priv->read(&mb->can_id);  in flexcan_mailbox_read()
715 		cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;  in flexcan_mailbox_read()
717 		cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;  in flexcan_mailbox_read()
720 		cf->can_id |= CAN_RTR_FLAG;  in flexcan_mailbox_read()
721 	cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);  in flexcan_mailbox_read()
723 	*(__be32 *)(cf->data + 0) = cpu_to_be32(priv->read(&mb->data[0]));  in flexcan_mailbox_read()
724 	*(__be32 *)(cf->data + 4) = cpu_to_be32(priv->read(&mb->data[1]));  in flexcan_mailbox_read()
727 	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {  in flexcan_mailbox_read()
730 			priv->write(BIT(n), &regs->iflag1);  in flexcan_mailbox_read()
732 			priv->write(BIT(n - 32), &regs->iflag2);  in flexcan_mailbox_read()
734 		priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);  in flexcan_mailbox_read()
741 	priv->read(&regs->timer);  in flexcan_mailbox_read()
749 	struct flexcan_regs __iomem *regs = priv->regs;  in flexcan_read_reg_iflag_rx()
752 	iflag2 = priv->read(&regs->iflag2) & priv->reg_imask2_default &  in flexcan_read_reg_iflag_rx()
754 	iflag1 = priv->read(&regs->iflag1) & priv->reg_imask1_default;  in flexcan_read_reg_iflag_rx()
762 	struct net_device_stats *stats = &dev->stats;  in flexcan_irq()
764 	struct flexcan_regs __iomem *regs = priv->regs;  in flexcan_irq()
767 	enum can_state last_state = priv->can.state;  in flexcan_irq()
770 	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {  in flexcan_irq()
776 			ret = can_rx_offload_irq_offload_timestamp(&priv->offload,  in flexcan_irq()
784 		reg_iflag1 = priv->read(&regs->iflag1);  in flexcan_irq()
787 			can_rx_offload_irq_offload_fifo(&priv->offload);  in flexcan_irq()
793 			priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,  in flexcan_irq()
794 				    &regs->iflag1);  in flexcan_irq()
795 			dev->stats.rx_over_errors++;  in flexcan_irq()
796 			dev->stats.rx_errors++;  in flexcan_irq()
800 	reg_iflag2 = priv->read(&regs->iflag2);  in flexcan_irq()
804 		u32 reg_ctrl = priv->read(&regs->mb[FLEXCAN_TX_MB].can_ctrl);  in flexcan_irq()
807 		stats->tx_bytes += can_rx_offload_get_echo_skb(&priv->offload,  in flexcan_irq()
809 		stats->tx_packets++;  in flexcan_irq()
813 		priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,  in flexcan_irq()
814 			    &regs->mb[FLEXCAN_TX_MB].can_ctrl);  in flexcan_irq()
815 		priv->write(FLEXCAN_IFLAG_MB(FLEXCAN_TX_MB), &regs->iflag2);  in flexcan_irq()
819 	reg_esr = priv->read(&regs->esr);  in flexcan_irq()
824 		priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);  in flexcan_irq()
829 	    (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |  in flexcan_irq()
833 	/* bus error IRQ - handle if bus error reporting is activated */  in flexcan_irq()
835 	    (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))  in flexcan_irq()
839 	 * bus error reporting is de-activated and  in flexcan_irq()
841 	 *  +--------------------------------------------------------------+  in flexcan_irq()
842 	 *  | +----------------------------------------------+ [stopped /  |  in flexcan_irq()
843 	 *  | |                                              |  sleeping] -+  in flexcan_irq()
844 	 *  +-+-> active <-> warning <-> passive -> bus off -+  in flexcan_irq()
850 	if ((last_state != priv->can.state) &&  in flexcan_irq()
851 	    (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&  in flexcan_irq()
852 	    !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {  in flexcan_irq()
853 		switch (priv->can.state) {  in flexcan_irq()
855 			if (priv->devtype_data->quirks &  in flexcan_irq()
882 	const struct can_bittiming *bt = &priv->can.bittiming;  in flexcan_set_bittiming()
883 	struct flexcan_regs __iomem *regs = priv->regs;  in flexcan_set_bittiming()
886 	reg = priv->read(&regs->ctrl);  in flexcan_set_bittiming()
896 	reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |  in flexcan_set_bittiming()
897 		FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |  in flexcan_set_bittiming()
898 		FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |  in flexcan_set_bittiming()
899 		FLEXCAN_CTRL_RJW(bt->sjw - 1) |  in flexcan_set_bittiming()
900 		FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);  in flexcan_set_bittiming()
902 	if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)  in flexcan_set_bittiming()
904 	if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)  in flexcan_set_bittiming()
906 	if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)  in flexcan_set_bittiming()
910 	priv->write(reg, &regs->ctrl);  in flexcan_set_bittiming()
914 		   priv->read(&regs->mcr), priv->read(&regs->ctrl));  in flexcan_set_bittiming()
925 	struct flexcan_regs __iomem *regs = priv->regs;  in flexcan_chip_start()
953 	reg_mcr = priv->read(&regs->mcr);  in flexcan_chip_start()
959 	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)  in flexcan_chip_start()
965 	priv->write(reg_mcr, &regs->mcr);  in flexcan_chip_start()
978 	reg_ctrl = priv->read(&regs->ctrl);  in flexcan_chip_start()
984 	 * on most Flexcan cores, too. Otherwise we don't get  in flexcan_chip_start()
987 	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||  in flexcan_chip_start()
988 	    priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)  in flexcan_chip_start()
994 	priv->reg_ctrl_default = reg_ctrl;  in flexcan_chip_start()
998 	priv->write(reg_ctrl, &regs->ctrl);  in flexcan_chip_start()
1000 	if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {  in flexcan_chip_start()
1001 		reg_ctrl2 = priv->read(&regs->ctrl2);  in flexcan_chip_start()
1003 		priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_chip_start()
1006 	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {  in flexcan_chip_start()
1007 		for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {  in flexcan_chip_start()
1008 			priv->write(FLEXCAN_MB_CODE_RX_EMPTY,  in flexcan_chip_start()
1009 				    &regs->mb[i].can_ctrl);  in flexcan_chip_start()
1013 		for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < ARRAY_SIZE(regs->mb); i++) {  in flexcan_chip_start()
1014 			priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,  in flexcan_chip_start()
1015 				    &regs->mb[i].can_ctrl);  in flexcan_chip_start()
1020 	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,  in flexcan_chip_start()
1021 		    &priv->tx_mb_reserved->can_ctrl);  in flexcan_chip_start()
1024 	priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,  in flexcan_chip_start()
1025 		    &regs->mb[FLEXCAN_TX_MB].can_ctrl);  in flexcan_chip_start()
1028 	priv->write(0x0, &regs->rxgmask);  in flexcan_chip_start()
1029 	priv->write(0x0, &regs->rx14mask);  in flexcan_chip_start()
1030 	priv->write(0x0, &regs->rx15mask);  in flexcan_chip_start()
1032 	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)  in flexcan_chip_start()
1033 		priv->write(0x0, &regs->rxfgmask);  in flexcan_chip_start()
1036 	for (i = 0; i < ARRAY_SIZE(regs->mb); i++)  in flexcan_chip_start()
1037 		priv->write(0, &regs->rximr[i]);  in flexcan_chip_start()
1045 	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {  in flexcan_chip_start()
1050 		reg_ctrl2 = priv->read(&regs->ctrl2);  in flexcan_chip_start()
1052 		priv->write(reg_ctrl2, &regs->ctrl2);  in flexcan_chip_start()
1054 		reg_mecr = priv->read(&regs->mecr);  in flexcan_chip_start()
1056 		priv->write(reg_mecr, &regs->mecr);  in flexcan_chip_start()
1060 		priv->write(reg_mecr, &regs->mecr);  in flexcan_chip_start()
1072 	priv->can.state = CAN_STATE_ERROR_ACTIVE;  in flexcan_chip_start()
1075 	disable_irq(dev->irq);  in flexcan_chip_start()
1076 	priv->write(priv->reg_ctrl_default, &regs->ctrl);  in flexcan_chip_start()
1077 	priv->write(priv->reg_imask1_default, &regs->imask1);  in flexcan_chip_start()
1078 	priv->write(priv->reg_imask2_default, &regs->imask2);  in flexcan_chip_start()
1079 	enable_irq(dev->irq);  in flexcan_chip_start()
1083 		   priv->read(&regs->mcr), priv->read(&regs->ctrl));  in flexcan_chip_start()
1101 	struct flexcan_regs __iomem *regs = priv->regs;  in __flexcan_chip_stop()
1113 	priv->write(0, &regs->imask2);  in __flexcan_chip_stop()
1114 	priv->write(0, &regs->imask1);  in __flexcan_chip_stop()
1115 	priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,  in __flexcan_chip_stop()
1116 		    &regs->ctrl);  in __flexcan_chip_stop()
1119 	priv->can.state = CAN_STATE_STOPPED;  in __flexcan_chip_stop()
1144 	err = clk_prepare_enable(priv->clk_ipg);  in flexcan_open()
1148 	err = clk_prepare_enable(priv->clk_per);  in flexcan_open()
1156 	err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);  in flexcan_open()
1167 	can_rx_offload_enable(&priv->offload);  in flexcan_open()
1173 	free_irq(dev->irq, dev);  in flexcan_open()
1177 	clk_disable_unprepare(priv->clk_per);  in flexcan_open()
1179 	clk_disable_unprepare(priv->clk_ipg);  in flexcan_open()
1189 	can_rx_offload_disable(&priv->offload);  in flexcan_close()
1192 	free_irq(dev->irq, dev);  in flexcan_close()
1193 	clk_disable_unprepare(priv->clk_per);  in flexcan_close()
1194 	clk_disable_unprepare(priv->clk_ipg);  in flexcan_close()
1217 		return -EOPNOTSUPP;  in flexcan_set_mode()
1233 	struct flexcan_regs __iomem *regs = priv->regs;  in register_flexcandev()
1236 	err = clk_prepare_enable(priv->clk_ipg);  in register_flexcandev()
1240 	err = clk_prepare_enable(priv->clk_per);  in register_flexcandev()
1248 	reg = priv->read(&regs->ctrl);  in register_flexcandev()
1250 	priv->write(reg, &regs->ctrl);  in register_flexcandev()
1257 	reg = priv->read(&regs->mcr);  in register_flexcandev()
1260 	priv->write(reg, &regs->mcr);  in register_flexcandev()
1267 	reg = priv->read(&regs->mcr);  in register_flexcandev()
1270 		err = -ENODEV;  in register_flexcandev()
1280 	clk_disable_unprepare(priv->clk_per);  in register_flexcandev()
1282 	clk_disable_unprepare(priv->clk_ipg);  in register_flexcandev()
1293 	{ .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1294 	{ .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1295 	{ .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
1296 	{ .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
1297 	{ .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
1298 	{ .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1299 	{ .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1300 	{ .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
1306 	{ .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1324 	reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");  in flexcan_probe()
1325 	if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)  in flexcan_probe()
1326 		return -EPROBE_DEFER;  in flexcan_probe()
1330 	if (pdev->dev.of_node)  in flexcan_probe()
1331 		of_property_read_u32(pdev->dev.of_node,  in flexcan_probe()
1332 				     "clock-frequency", &clock_freq);  in flexcan_probe()
1335 		clk_ipg = devm_clk_get(&pdev->dev, "ipg");  in flexcan_probe()
1337 			dev_err(&pdev->dev, "no ipg clock defined\n");  in flexcan_probe()
1341 		clk_per = devm_clk_get(&pdev->dev, "per");  in flexcan_probe()
1343 			dev_err(&pdev->dev, "no per clock defined\n");  in flexcan_probe()
1352 		return -ENODEV;  in flexcan_probe()
1354 	regs = devm_ioremap_resource(&pdev->dev, mem);  in flexcan_probe()
1358 	of_id = of_match_device(flexcan_of_match, &pdev->dev);  in flexcan_probe()
1360 		devtype_data = of_id->data;  in flexcan_probe()
1361 	} else if (platform_get_device_id(pdev)->driver_data) {  in flexcan_probe()
1363 			platform_get_device_id(pdev)->driver_data;  in flexcan_probe()
1365 		return -ENODEV;  in flexcan_probe()
1370 		return -ENOMEM;  in flexcan_probe()
1373 	SET_NETDEV_DEV(dev, &pdev->dev);  in flexcan_probe()
1375 	dev->netdev_ops = &flexcan_netdev_ops;  in flexcan_probe()
1376 	dev->irq = irq;  in flexcan_probe()
1377 	dev->flags |= IFF_ECHO;  in flexcan_probe()
1381 	if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||  in flexcan_probe()
1382 	    devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {  in flexcan_probe()
1383 		priv->read = flexcan_read_be;  in flexcan_probe()
1384 		priv->write = flexcan_write_be;  in flexcan_probe()
1386 		priv->read = flexcan_read_le;  in flexcan_probe()
1387 		priv->write = flexcan_write_le;  in flexcan_probe()
1390 	priv->can.clock.freq = clock_freq;  in flexcan_probe()
1391 	priv->can.bittiming_const = &flexcan_bittiming_const;  in flexcan_probe()
1392 	priv->can.do_set_mode = flexcan_set_mode;  in flexcan_probe()
1393 	priv->can.do_get_berr_counter = flexcan_get_berr_counter;  in flexcan_probe()
1394 	priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |  in flexcan_probe()
1397 	priv->regs = regs;  in flexcan_probe()
1398 	priv->clk_ipg = clk_ipg;  in flexcan_probe()
1399 	priv->clk_per = clk_per;  in flexcan_probe()
1400 	priv->devtype_data = devtype_data;  in flexcan_probe()
1401 	priv->reg_xceiver = reg_xceiver;  in flexcan_probe()
1403 	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)  in flexcan_probe()
1404 		priv->tx_mb_reserved = &regs->mb[FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP];  in flexcan_probe()
1406 		priv->tx_mb_reserved = &regs->mb[FLEXCAN_TX_MB_RESERVED_OFF_FIFO];  in flexcan_probe()
1408 	priv->reg_imask1_default = 0;  in flexcan_probe()
1409 	priv->reg_imask2_default = FLEXCAN_IFLAG_MB(FLEXCAN_TX_MB);  in flexcan_probe()
1411 	priv->offload.mailbox_read = flexcan_mailbox_read;  in flexcan_probe()
1413 	if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {  in flexcan_probe()
1416 		priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;  in flexcan_probe()
1417 		priv->offload.mb_last = FLEXCAN_RX_MB_OFF_TIMESTAMP_LAST;  in flexcan_probe()
1419 		imask = GENMASK_ULL(priv->offload.mb_last, priv->offload.mb_first);  in flexcan_probe()
1420 		priv->reg_imask1_default |= imask;  in flexcan_probe()
1421 		priv->reg_imask2_default |= imask >> 32;  in flexcan_probe()
1423 		err = can_rx_offload_add_timestamp(dev, &priv->offload);  in flexcan_probe()
1425 		priv->reg_imask1_default |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |  in flexcan_probe()
1427 		err = can_rx_offload_add_fifo(dev, &priv->offload, FLEXCAN_NAPI_WEIGHT);  in flexcan_probe()
1434 		dev_err(&pdev->dev, "registering netdev failed\n");  in flexcan_probe()
1440 	dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",  in flexcan_probe()
1441 		 priv->regs, dev->irq);  in flexcan_probe()
1457 	can_rx_offload_del(&priv->offload);  in flexcan_remove()
1476 	priv->can.state = CAN_STATE_SLEEPING;  in flexcan_suspend()
1487 	priv->can.state = CAN_STATE_ERROR_ACTIVE;  in flexcan_resume()
1514 	      "Marc Kleine-Budde <kernel@pengutronix.de>");
1516 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");