1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // flexcan.c - FLEXCAN CAN controller driver
4 //
5 // Copyright (c) 2005-2006 Varma Electronics Oy
6 // Copyright (c) 2009 Sascha Hauer, Pengutronix
7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
8 // Copyright (c) 2014 David Jander, Protonic Holland
9 //
10 // Based on code originally by Andrey Volkov <avolkov@varma-el.com>
11
12 #include <linux/netdevice.h>
13 #include <linux/can.h>
14 #include <linux/can/dev.h>
15 #include <linux/can/error.h>
16 #include <linux/can/led.h>
17 #include <linux/can/rx-offload.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/module.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/platform_device.h>
26 #include <linux/regulator/consumer.h>
27
28 #define DRV_NAME "flexcan"
29
30 /* 8 for RX fifo and 2 error handling */
31 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
32
33 /* FLEXCAN module configuration register (CANMCR) bits */
34 #define FLEXCAN_MCR_MDIS BIT(31)
35 #define FLEXCAN_MCR_FRZ BIT(30)
36 #define FLEXCAN_MCR_FEN BIT(29)
37 #define FLEXCAN_MCR_HALT BIT(28)
38 #define FLEXCAN_MCR_NOT_RDY BIT(27)
39 #define FLEXCAN_MCR_WAK_MSK BIT(26)
40 #define FLEXCAN_MCR_SOFTRST BIT(25)
41 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
42 #define FLEXCAN_MCR_SUPV BIT(23)
43 #define FLEXCAN_MCR_SLF_WAK BIT(22)
44 #define FLEXCAN_MCR_WRN_EN BIT(21)
45 #define FLEXCAN_MCR_LPM_ACK BIT(20)
46 #define FLEXCAN_MCR_WAK_SRC BIT(19)
47 #define FLEXCAN_MCR_DOZE BIT(18)
48 #define FLEXCAN_MCR_SRX_DIS BIT(17)
49 #define FLEXCAN_MCR_IRMQ BIT(16)
50 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
51 #define FLEXCAN_MCR_AEN BIT(12)
52 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
53 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
54 #define FLEXCAN_MCR_IDAM_A (0x0 << 8)
55 #define FLEXCAN_MCR_IDAM_B (0x1 << 8)
56 #define FLEXCAN_MCR_IDAM_C (0x2 << 8)
57 #define FLEXCAN_MCR_IDAM_D (0x3 << 8)
58
59 /* FLEXCAN control register (CANCTRL) bits */
60 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
61 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
62 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
63 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
64 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
65 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
66 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
67 #define FLEXCAN_CTRL_LPB BIT(12)
68 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
69 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
70 #define FLEXCAN_CTRL_SMP BIT(7)
71 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
72 #define FLEXCAN_CTRL_TSYN BIT(5)
73 #define FLEXCAN_CTRL_LBUF BIT(4)
74 #define FLEXCAN_CTRL_LOM BIT(3)
75 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
76 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
77 #define FLEXCAN_CTRL_ERR_STATE \
78 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
79 FLEXCAN_CTRL_BOFF_MSK)
80 #define FLEXCAN_CTRL_ERR_ALL \
81 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
82
83 /* FLEXCAN control register 2 (CTRL2) bits */
84 #define FLEXCAN_CTRL2_ECRWRE BIT(29)
85 #define FLEXCAN_CTRL2_WRMFRZ BIT(28)
86 #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
87 #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
88 #define FLEXCAN_CTRL2_MRP BIT(18)
89 #define FLEXCAN_CTRL2_RRS BIT(17)
90 #define FLEXCAN_CTRL2_EACEN BIT(16)
91
92 /* FLEXCAN memory error control register (MECR) bits */
93 #define FLEXCAN_MECR_ECRWRDIS BIT(31)
94 #define FLEXCAN_MECR_HANCEI_MSK BIT(19)
95 #define FLEXCAN_MECR_FANCEI_MSK BIT(18)
96 #define FLEXCAN_MECR_CEI_MSK BIT(16)
97 #define FLEXCAN_MECR_HAERRIE BIT(15)
98 #define FLEXCAN_MECR_FAERRIE BIT(14)
99 #define FLEXCAN_MECR_EXTERRIE BIT(13)
100 #define FLEXCAN_MECR_RERRDIS BIT(9)
101 #define FLEXCAN_MECR_ECCDIS BIT(8)
102 #define FLEXCAN_MECR_NCEFAFRZ BIT(7)
103
104 /* FLEXCAN error and status register (ESR) bits */
105 #define FLEXCAN_ESR_TWRN_INT BIT(17)
106 #define FLEXCAN_ESR_RWRN_INT BIT(16)
107 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
108 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
109 #define FLEXCAN_ESR_ACK_ERR BIT(13)
110 #define FLEXCAN_ESR_CRC_ERR BIT(12)
111 #define FLEXCAN_ESR_FRM_ERR BIT(11)
112 #define FLEXCAN_ESR_STF_ERR BIT(10)
113 #define FLEXCAN_ESR_TX_WRN BIT(9)
114 #define FLEXCAN_ESR_RX_WRN BIT(8)
115 #define FLEXCAN_ESR_IDLE BIT(7)
116 #define FLEXCAN_ESR_TXRX BIT(6)
117 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
118 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
119 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
120 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
121 #define FLEXCAN_ESR_BOFF_INT BIT(2)
122 #define FLEXCAN_ESR_ERR_INT BIT(1)
123 #define FLEXCAN_ESR_WAK_INT BIT(0)
124 #define FLEXCAN_ESR_ERR_BUS \
125 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
126 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
127 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
128 #define FLEXCAN_ESR_ERR_STATE \
129 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
130 #define FLEXCAN_ESR_ERR_ALL \
131 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
132 #define FLEXCAN_ESR_ALL_INT \
133 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
134 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
135
136 /* FLEXCAN interrupt flag register (IFLAG) bits */
137 /* Errata ERR005829 step7: Reserve first valid MB */
138 #define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
139 #define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0
140 #define FLEXCAN_TX_MB 63
141 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
142 #define FLEXCAN_RX_MB_OFF_TIMESTAMP_LAST (FLEXCAN_TX_MB - 1)
143 #define FLEXCAN_IFLAG_MB(x) BIT((x) & 0x1f)
144 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
145 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
146 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
147
148 /* FLEXCAN message buffers */
149 #define FLEXCAN_MB_CODE_MASK (0xf << 24)
150 #define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24)
151 #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
152 #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
153 #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
154 #define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
155 #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
156
157 #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
158 #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
159 #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
160 #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
161
162 #define FLEXCAN_MB_CNT_SRR BIT(22)
163 #define FLEXCAN_MB_CNT_IDE BIT(21)
164 #define FLEXCAN_MB_CNT_RTR BIT(20)
165 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
166 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
167
168 #define FLEXCAN_TIMEOUT_US (250)
169
170 /* FLEXCAN hardware feature flags
171 *
172 * Below is some version info we got:
173 * SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
174 * Filter? connected? Passive detection ception in MB
175 * MX25 FlexCAN2 03.00.00.00 no no no no no
176 * MX28 FlexCAN2 03.00.04.00 yes yes no no no
177 * MX35 FlexCAN2 03.00.00.00 no no no no no
178 * MX53 FlexCAN2 03.00.00.00 yes no no no no
179 * MX6s FlexCAN3 10.00.12.00 yes yes no no yes
180 * VF610 FlexCAN3 ? no yes no yes yes?
181 * LS1021A FlexCAN2 03.00.04.00 no yes no no yes
182 *
183 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
184 */
185 #define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1) /* [TR]WRN_INT not connected */
186 #define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2) /* Disable RX FIFO Global mask */
187 #define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
188 #define FLEXCAN_QUIRK_DISABLE_MECR BIT(4) /* Disable Memory error detection */
189 #define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */
190 #define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6) /* No interrupt for error passive */
191 #define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7) /* default to BE register access */
192
193 /* Structure of the message buffer */
194 struct flexcan_mb {
195 u32 can_ctrl;
196 u32 can_id;
197 u32 data[2];
198 };
199
200 /* Structure of the hardware registers */
201 struct flexcan_regs {
202 u32 mcr; /* 0x00 */
203 u32 ctrl; /* 0x04 */
204 u32 timer; /* 0x08 */
205 u32 _reserved1; /* 0x0c */
206 u32 rxgmask; /* 0x10 */
207 u32 rx14mask; /* 0x14 */
208 u32 rx15mask; /* 0x18 */
209 u32 ecr; /* 0x1c */
210 u32 esr; /* 0x20 */
211 u32 imask2; /* 0x24 */
212 u32 imask1; /* 0x28 */
213 u32 iflag2; /* 0x2c */
214 u32 iflag1; /* 0x30 */
215 union { /* 0x34 */
216 u32 gfwr_mx28; /* MX28, MX53 */
217 u32 ctrl2; /* MX6, VF610 */
218 };
219 u32 esr2; /* 0x38 */
220 u32 imeur; /* 0x3c */
221 u32 lrfr; /* 0x40 */
222 u32 crcr; /* 0x44 */
223 u32 rxfgmask; /* 0x48 */
224 u32 rxfir; /* 0x4c */
225 u32 _reserved3[12]; /* 0x50 */
226 struct flexcan_mb mb[64]; /* 0x80 */
227 /* FIFO-mode:
228 * MB
229 * 0x080...0x08f 0 RX message buffer
230 * 0x090...0x0df 1-5 reserverd
231 * 0x0e0...0x0ff 6-7 8 entry ID table
232 * (mx25, mx28, mx35, mx53)
233 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
234 * size conf'ed via ctrl2::RFFN
235 * (mx6, vf610)
236 */
237 u32 _reserved4[256]; /* 0x480 */
238 u32 rximr[64]; /* 0x880 */
239 u32 _reserved5[24]; /* 0x980 */
240 u32 gfwr_mx6; /* 0x9e0 - MX6 */
241 u32 _reserved6[63]; /* 0x9e4 */
242 u32 mecr; /* 0xae0 */
243 u32 erriar; /* 0xae4 */
244 u32 erridpr; /* 0xae8 */
245 u32 errippr; /* 0xaec */
246 u32 rerrar; /* 0xaf0 */
247 u32 rerrdr; /* 0xaf4 */
248 u32 rerrsynr; /* 0xaf8 */
249 u32 errsr; /* 0xafc */
250 };
251
252 struct flexcan_devtype_data {
253 u32 quirks; /* quirks needed for different IP cores */
254 };
255
256 struct flexcan_priv {
257 struct can_priv can;
258 struct can_rx_offload offload;
259
260 struct flexcan_regs __iomem *regs;
261 struct flexcan_mb __iomem *tx_mb_reserved;
262 u32 reg_ctrl_default;
263 u32 reg_imask1_default;
264 u32 reg_imask2_default;
265
266 struct clk *clk_ipg;
267 struct clk *clk_per;
268 const struct flexcan_devtype_data *devtype_data;
269 struct regulator *reg_xceiver;
270
271 /* Read and Write APIs */
272 u32 (*read)(void __iomem *addr);
273 void (*write)(u32 val, void __iomem *addr);
274 };
275
276 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
277 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
278 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
279 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
280 };
281
282 static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
283 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
284 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
285 };
286
287 static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
288 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
289 };
290
291 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
292 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
293 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE,
294 };
295
296 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
297 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
298 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
299 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
300 };
301
302 static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
303 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
304 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
305 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
306 };
307
308 static const struct can_bittiming_const flexcan_bittiming_const = {
309 .name = DRV_NAME,
310 .tseg1_min = 4,
311 .tseg1_max = 16,
312 .tseg2_min = 2,
313 .tseg2_max = 8,
314 .sjw_max = 4,
315 .brp_min = 1,
316 .brp_max = 256,
317 .brp_inc = 1,
318 };
319
320 /* FlexCAN module is essentially modelled as a little-endian IP in most
321 * SoCs, i.e the registers as well as the message buffer areas are
322 * implemented in a little-endian fashion.
323 *
324 * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
325 * module in a big-endian fashion (i.e the registers as well as the
326 * message buffer areas are implemented in a big-endian way).
327 *
328 * In addition, the FlexCAN module can be found on SoCs having ARM or
329 * PPC cores. So, we need to abstract off the register read/write
330 * functions, ensuring that these cater to all the combinations of module
331 * endianness and underlying CPU endianness.
332 */
flexcan_read_be(void __iomem * addr)333 static inline u32 flexcan_read_be(void __iomem *addr)
334 {
335 return ioread32be(addr);
336 }
337
flexcan_write_be(u32 val,void __iomem * addr)338 static inline void flexcan_write_be(u32 val, void __iomem *addr)
339 {
340 iowrite32be(val, addr);
341 }
342
flexcan_read_le(void __iomem * addr)343 static inline u32 flexcan_read_le(void __iomem *addr)
344 {
345 return ioread32(addr);
346 }
347
flexcan_write_le(u32 val,void __iomem * addr)348 static inline void flexcan_write_le(u32 val, void __iomem *addr)
349 {
350 iowrite32(val, addr);
351 }
352
flexcan_error_irq_enable(const struct flexcan_priv * priv)353 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
354 {
355 struct flexcan_regs __iomem *regs = priv->regs;
356 u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
357
358 priv->write(reg_ctrl, ®s->ctrl);
359 }
360
flexcan_error_irq_disable(const struct flexcan_priv * priv)361 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
362 {
363 struct flexcan_regs __iomem *regs = priv->regs;
364 u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
365
366 priv->write(reg_ctrl, ®s->ctrl);
367 }
368
flexcan_transceiver_enable(const struct flexcan_priv * priv)369 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
370 {
371 if (!priv->reg_xceiver)
372 return 0;
373
374 return regulator_enable(priv->reg_xceiver);
375 }
376
flexcan_transceiver_disable(const struct flexcan_priv * priv)377 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
378 {
379 if (!priv->reg_xceiver)
380 return 0;
381
382 return regulator_disable(priv->reg_xceiver);
383 }
384
flexcan_chip_enable(struct flexcan_priv * priv)385 static int flexcan_chip_enable(struct flexcan_priv *priv)
386 {
387 struct flexcan_regs __iomem *regs = priv->regs;
388 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
389 u32 reg;
390
391 reg = priv->read(®s->mcr);
392 reg &= ~FLEXCAN_MCR_MDIS;
393 priv->write(reg, ®s->mcr);
394
395 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
396 udelay(10);
397
398 if (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
399 return -ETIMEDOUT;
400
401 return 0;
402 }
403
flexcan_chip_disable(struct flexcan_priv * priv)404 static int flexcan_chip_disable(struct flexcan_priv *priv)
405 {
406 struct flexcan_regs __iomem *regs = priv->regs;
407 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
408 u32 reg;
409
410 reg = priv->read(®s->mcr);
411 reg |= FLEXCAN_MCR_MDIS;
412 priv->write(reg, ®s->mcr);
413
414 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
415 udelay(10);
416
417 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
418 return -ETIMEDOUT;
419
420 return 0;
421 }
422
flexcan_chip_freeze(struct flexcan_priv * priv)423 static int flexcan_chip_freeze(struct flexcan_priv *priv)
424 {
425 struct flexcan_regs __iomem *regs = priv->regs;
426 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
427 u32 reg;
428
429 reg = priv->read(®s->mcr);
430 reg |= FLEXCAN_MCR_HALT;
431 priv->write(reg, ®s->mcr);
432
433 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
434 udelay(100);
435
436 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
437 return -ETIMEDOUT;
438
439 return 0;
440 }
441
flexcan_chip_unfreeze(struct flexcan_priv * priv)442 static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
443 {
444 struct flexcan_regs __iomem *regs = priv->regs;
445 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
446 u32 reg;
447
448 reg = priv->read(®s->mcr);
449 reg &= ~FLEXCAN_MCR_HALT;
450 priv->write(reg, ®s->mcr);
451
452 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
453 udelay(10);
454
455 if (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
456 return -ETIMEDOUT;
457
458 return 0;
459 }
460
flexcan_chip_softreset(struct flexcan_priv * priv)461 static int flexcan_chip_softreset(struct flexcan_priv *priv)
462 {
463 struct flexcan_regs __iomem *regs = priv->regs;
464 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
465
466 priv->write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
467 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
468 udelay(10);
469
470 if (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
471 return -ETIMEDOUT;
472
473 return 0;
474 }
475
__flexcan_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)476 static int __flexcan_get_berr_counter(const struct net_device *dev,
477 struct can_berr_counter *bec)
478 {
479 const struct flexcan_priv *priv = netdev_priv(dev);
480 struct flexcan_regs __iomem *regs = priv->regs;
481 u32 reg = priv->read(®s->ecr);
482
483 bec->txerr = (reg >> 0) & 0xff;
484 bec->rxerr = (reg >> 8) & 0xff;
485
486 return 0;
487 }
488
flexcan_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)489 static int flexcan_get_berr_counter(const struct net_device *dev,
490 struct can_berr_counter *bec)
491 {
492 const struct flexcan_priv *priv = netdev_priv(dev);
493 int err;
494
495 err = clk_prepare_enable(priv->clk_ipg);
496 if (err)
497 return err;
498
499 err = clk_prepare_enable(priv->clk_per);
500 if (err)
501 goto out_disable_ipg;
502
503 err = __flexcan_get_berr_counter(dev, bec);
504
505 clk_disable_unprepare(priv->clk_per);
506 out_disable_ipg:
507 clk_disable_unprepare(priv->clk_ipg);
508
509 return err;
510 }
511
flexcan_start_xmit(struct sk_buff * skb,struct net_device * dev)512 static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
513 {
514 const struct flexcan_priv *priv = netdev_priv(dev);
515 struct flexcan_regs __iomem *regs = priv->regs;
516 struct can_frame *cf = (struct can_frame *)skb->data;
517 u32 can_id;
518 u32 data;
519 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
520
521 if (can_dropped_invalid_skb(dev, skb))
522 return NETDEV_TX_OK;
523
524 netif_stop_queue(dev);
525
526 if (cf->can_id & CAN_EFF_FLAG) {
527 can_id = cf->can_id & CAN_EFF_MASK;
528 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
529 } else {
530 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
531 }
532
533 if (cf->can_id & CAN_RTR_FLAG)
534 ctrl |= FLEXCAN_MB_CNT_RTR;
535
536 if (cf->can_dlc > 0) {
537 data = be32_to_cpup((__be32 *)&cf->data[0]);
538 priv->write(data, ®s->mb[FLEXCAN_TX_MB].data[0]);
539 }
540 if (cf->can_dlc > 4) {
541 data = be32_to_cpup((__be32 *)&cf->data[4]);
542 priv->write(data, ®s->mb[FLEXCAN_TX_MB].data[1]);
543 }
544
545 can_put_echo_skb(skb, dev, 0);
546
547 priv->write(can_id, ®s->mb[FLEXCAN_TX_MB].can_id);
548 priv->write(ctrl, ®s->mb[FLEXCAN_TX_MB].can_ctrl);
549
550 /* Errata ERR005829 step8:
551 * Write twice INACTIVE(0x8) code to first MB.
552 */
553 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
554 &priv->tx_mb_reserved->can_ctrl);
555 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
556 &priv->tx_mb_reserved->can_ctrl);
557
558 return NETDEV_TX_OK;
559 }
560
flexcan_irq_bus_err(struct net_device * dev,u32 reg_esr)561 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
562 {
563 struct flexcan_priv *priv = netdev_priv(dev);
564 struct flexcan_regs __iomem *regs = priv->regs;
565 struct sk_buff *skb;
566 struct can_frame *cf;
567 bool rx_errors = false, tx_errors = false;
568 u32 timestamp;
569 int err;
570
571 timestamp = priv->read(®s->timer) << 16;
572
573 skb = alloc_can_err_skb(dev, &cf);
574 if (unlikely(!skb))
575 return;
576
577 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
578
579 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
580 netdev_dbg(dev, "BIT1_ERR irq\n");
581 cf->data[2] |= CAN_ERR_PROT_BIT1;
582 tx_errors = true;
583 }
584 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
585 netdev_dbg(dev, "BIT0_ERR irq\n");
586 cf->data[2] |= CAN_ERR_PROT_BIT0;
587 tx_errors = true;
588 }
589 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
590 netdev_dbg(dev, "ACK_ERR irq\n");
591 cf->can_id |= CAN_ERR_ACK;
592 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
593 tx_errors = true;
594 }
595 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
596 netdev_dbg(dev, "CRC_ERR irq\n");
597 cf->data[2] |= CAN_ERR_PROT_BIT;
598 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
599 rx_errors = true;
600 }
601 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
602 netdev_dbg(dev, "FRM_ERR irq\n");
603 cf->data[2] |= CAN_ERR_PROT_FORM;
604 rx_errors = true;
605 }
606 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
607 netdev_dbg(dev, "STF_ERR irq\n");
608 cf->data[2] |= CAN_ERR_PROT_STUFF;
609 rx_errors = true;
610 }
611
612 priv->can.can_stats.bus_error++;
613 if (rx_errors)
614 dev->stats.rx_errors++;
615 if (tx_errors)
616 dev->stats.tx_errors++;
617
618 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
619 if (err)
620 dev->stats.rx_fifo_errors++;
621 }
622
flexcan_irq_state(struct net_device * dev,u32 reg_esr)623 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
624 {
625 struct flexcan_priv *priv = netdev_priv(dev);
626 struct flexcan_regs __iomem *regs = priv->regs;
627 struct sk_buff *skb;
628 struct can_frame *cf;
629 enum can_state new_state, rx_state, tx_state;
630 int flt;
631 struct can_berr_counter bec;
632 u32 timestamp;
633 int err;
634
635 timestamp = priv->read(®s->timer) << 16;
636
637 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
638 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
639 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
640 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
641 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
642 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
643 new_state = max(tx_state, rx_state);
644 } else {
645 __flexcan_get_berr_counter(dev, &bec);
646 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
647 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
648 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
649 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
650 }
651
652 /* state hasn't changed */
653 if (likely(new_state == priv->can.state))
654 return;
655
656 skb = alloc_can_err_skb(dev, &cf);
657 if (unlikely(!skb))
658 return;
659
660 can_change_state(dev, cf, tx_state, rx_state);
661
662 if (unlikely(new_state == CAN_STATE_BUS_OFF))
663 can_bus_off(dev);
664
665 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
666 if (err)
667 dev->stats.rx_fifo_errors++;
668 }
669
rx_offload_to_priv(struct can_rx_offload * offload)670 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
671 {
672 return container_of(offload, struct flexcan_priv, offload);
673 }
674
flexcan_mailbox_read(struct can_rx_offload * offload,struct can_frame * cf,u32 * timestamp,unsigned int n)675 static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
676 struct can_frame *cf,
677 u32 *timestamp, unsigned int n)
678 {
679 struct flexcan_priv *priv = rx_offload_to_priv(offload);
680 struct flexcan_regs __iomem *regs = priv->regs;
681 struct flexcan_mb __iomem *mb = ®s->mb[n];
682 u32 reg_ctrl, reg_id, reg_iflag1;
683
684 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
685 u32 code;
686
687 do {
688 reg_ctrl = priv->read(&mb->can_ctrl);
689 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
690
691 /* is this MB empty? */
692 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
693 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
694 (code != FLEXCAN_MB_CODE_RX_OVERRUN))
695 return 0;
696
697 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
698 /* This MB was overrun, we lost data */
699 offload->dev->stats.rx_over_errors++;
700 offload->dev->stats.rx_errors++;
701 }
702 } else {
703 reg_iflag1 = priv->read(®s->iflag1);
704 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
705 return 0;
706
707 reg_ctrl = priv->read(&mb->can_ctrl);
708 }
709
710 /* increase timstamp to full 32 bit */
711 *timestamp = reg_ctrl << 16;
712
713 reg_id = priv->read(&mb->can_id);
714 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
715 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
716 else
717 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
718
719 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
720 cf->can_id |= CAN_RTR_FLAG;
721 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
722
723 *(__be32 *)(cf->data + 0) = cpu_to_be32(priv->read(&mb->data[0]));
724 *(__be32 *)(cf->data + 4) = cpu_to_be32(priv->read(&mb->data[1]));
725
726 /* mark as read */
727 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
728 /* Clear IRQ */
729 if (n < 32)
730 priv->write(BIT(n), ®s->iflag1);
731 else
732 priv->write(BIT(n - 32), ®s->iflag2);
733 } else {
734 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
735 }
736
737 /* Read the Free Running Timer. It is optional but recommended
738 * to unlock Mailbox as soon as possible and make it available
739 * for reception.
740 */
741 priv->read(®s->timer);
742
743 return 1;
744 }
745
746
flexcan_read_reg_iflag_rx(struct flexcan_priv * priv)747 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
748 {
749 struct flexcan_regs __iomem *regs = priv->regs;
750 u32 iflag1, iflag2;
751
752 iflag2 = priv->read(®s->iflag2) & priv->reg_imask2_default &
753 ~FLEXCAN_IFLAG_MB(FLEXCAN_TX_MB);
754 iflag1 = priv->read(®s->iflag1) & priv->reg_imask1_default;
755
756 return (u64)iflag2 << 32 | iflag1;
757 }
758
flexcan_irq(int irq,void * dev_id)759 static irqreturn_t flexcan_irq(int irq, void *dev_id)
760 {
761 struct net_device *dev = dev_id;
762 struct net_device_stats *stats = &dev->stats;
763 struct flexcan_priv *priv = netdev_priv(dev);
764 struct flexcan_regs __iomem *regs = priv->regs;
765 irqreturn_t handled = IRQ_NONE;
766 u32 reg_iflag2, reg_esr;
767 enum can_state last_state = priv->can.state;
768
769 /* reception interrupt */
770 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
771 u64 reg_iflag;
772 int ret;
773
774 while ((reg_iflag = flexcan_read_reg_iflag_rx(priv))) {
775 handled = IRQ_HANDLED;
776 ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
777 reg_iflag);
778 if (!ret)
779 break;
780 }
781 } else {
782 u32 reg_iflag1;
783
784 reg_iflag1 = priv->read(®s->iflag1);
785 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
786 handled = IRQ_HANDLED;
787 can_rx_offload_irq_offload_fifo(&priv->offload);
788 }
789
790 /* FIFO overflow interrupt */
791 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
792 handled = IRQ_HANDLED;
793 priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
794 ®s->iflag1);
795 dev->stats.rx_over_errors++;
796 dev->stats.rx_errors++;
797 }
798 }
799
800 reg_iflag2 = priv->read(®s->iflag2);
801
802 /* transmission complete interrupt */
803 if (reg_iflag2 & FLEXCAN_IFLAG_MB(FLEXCAN_TX_MB)) {
804 u32 reg_ctrl = priv->read(®s->mb[FLEXCAN_TX_MB].can_ctrl);
805
806 handled = IRQ_HANDLED;
807 stats->tx_bytes += can_rx_offload_get_echo_skb(&priv->offload,
808 0, reg_ctrl << 16);
809 stats->tx_packets++;
810 can_led_event(dev, CAN_LED_EVENT_TX);
811
812 /* after sending a RTR frame MB is in RX mode */
813 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
814 ®s->mb[FLEXCAN_TX_MB].can_ctrl);
815 priv->write(FLEXCAN_IFLAG_MB(FLEXCAN_TX_MB), ®s->iflag2);
816 netif_wake_queue(dev);
817 }
818
819 reg_esr = priv->read(®s->esr);
820
821 /* ACK all bus error and state change IRQ sources */
822 if (reg_esr & FLEXCAN_ESR_ALL_INT) {
823 handled = IRQ_HANDLED;
824 priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
825 }
826
827 /* state change interrupt or broken error state quirk fix is enabled */
828 if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
829 (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
830 FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
831 flexcan_irq_state(dev, reg_esr);
832
833 /* bus error IRQ - handle if bus error reporting is activated */
834 if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
835 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
836 flexcan_irq_bus_err(dev, reg_esr);
837
838 /* availability of error interrupt among state transitions in case
839 * bus error reporting is de-activated and
840 * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
841 * +--------------------------------------------------------------+
842 * | +----------------------------------------------+ [stopped / |
843 * | | | sleeping] -+
844 * +-+-> active <-> warning <-> passive -> bus off -+
845 * ___________^^^^^^^^^^^^_______________________________
846 * disabled(1) enabled disabled
847 *
848 * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
849 */
850 if ((last_state != priv->can.state) &&
851 (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
852 !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
853 switch (priv->can.state) {
854 case CAN_STATE_ERROR_ACTIVE:
855 if (priv->devtype_data->quirks &
856 FLEXCAN_QUIRK_BROKEN_WERR_STATE)
857 flexcan_error_irq_enable(priv);
858 else
859 flexcan_error_irq_disable(priv);
860 break;
861
862 case CAN_STATE_ERROR_WARNING:
863 flexcan_error_irq_enable(priv);
864 break;
865
866 case CAN_STATE_ERROR_PASSIVE:
867 case CAN_STATE_BUS_OFF:
868 flexcan_error_irq_disable(priv);
869 break;
870
871 default:
872 break;
873 }
874 }
875
876 return handled;
877 }
878
flexcan_set_bittiming(struct net_device * dev)879 static void flexcan_set_bittiming(struct net_device *dev)
880 {
881 const struct flexcan_priv *priv = netdev_priv(dev);
882 const struct can_bittiming *bt = &priv->can.bittiming;
883 struct flexcan_regs __iomem *regs = priv->regs;
884 u32 reg;
885
886 reg = priv->read(®s->ctrl);
887 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
888 FLEXCAN_CTRL_RJW(0x3) |
889 FLEXCAN_CTRL_PSEG1(0x7) |
890 FLEXCAN_CTRL_PSEG2(0x7) |
891 FLEXCAN_CTRL_PROPSEG(0x7) |
892 FLEXCAN_CTRL_LPB |
893 FLEXCAN_CTRL_SMP |
894 FLEXCAN_CTRL_LOM);
895
896 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
897 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
898 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
899 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
900 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
901
902 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
903 reg |= FLEXCAN_CTRL_LPB;
904 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
905 reg |= FLEXCAN_CTRL_LOM;
906 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
907 reg |= FLEXCAN_CTRL_SMP;
908
909 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
910 priv->write(reg, ®s->ctrl);
911
912 /* print chip status */
913 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
914 priv->read(®s->mcr), priv->read(®s->ctrl));
915 }
916
917 /* flexcan_chip_start
918 *
919 * this functions is entered with clocks enabled
920 *
921 */
flexcan_chip_start(struct net_device * dev)922 static int flexcan_chip_start(struct net_device *dev)
923 {
924 struct flexcan_priv *priv = netdev_priv(dev);
925 struct flexcan_regs __iomem *regs = priv->regs;
926 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
927 int err, i;
928
929 /* enable module */
930 err = flexcan_chip_enable(priv);
931 if (err)
932 return err;
933
934 /* soft reset */
935 err = flexcan_chip_softreset(priv);
936 if (err)
937 goto out_chip_disable;
938
939 flexcan_set_bittiming(dev);
940
941 /* MCR
942 *
943 * enable freeze
944 * enable fifo
945 * halt now
946 * only supervisor access
947 * enable warning int
948 * disable local echo
949 * enable individual RX masking
950 * choose format C
951 * set max mailbox number
952 */
953 reg_mcr = priv->read(®s->mcr);
954 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
955 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
956 FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_IRMQ |
957 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(FLEXCAN_TX_MB);
958
959 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
960 reg_mcr &= ~FLEXCAN_MCR_FEN;
961 else
962 reg_mcr |= FLEXCAN_MCR_FEN;
963
964 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
965 priv->write(reg_mcr, ®s->mcr);
966
967 /* CTRL
968 *
969 * disable timer sync feature
970 *
971 * disable auto busoff recovery
972 * transmit lowest buffer first
973 *
974 * enable tx and rx warning interrupt
975 * enable bus off interrupt
976 * (== FLEXCAN_CTRL_ERR_STATE)
977 */
978 reg_ctrl = priv->read(®s->ctrl);
979 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
980 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
981 FLEXCAN_CTRL_ERR_STATE;
982
983 /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
984 * on most Flexcan cores, too. Otherwise we don't get
985 * any error warning or passive interrupts.
986 */
987 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
988 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
989 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
990 else
991 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
992
993 /* save for later use */
994 priv->reg_ctrl_default = reg_ctrl;
995 /* leave interrupts disabled for now */
996 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
997 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
998 priv->write(reg_ctrl, ®s->ctrl);
999
1000 if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1001 reg_ctrl2 = priv->read(®s->ctrl2);
1002 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1003 priv->write(reg_ctrl2, ®s->ctrl2);
1004 }
1005
1006 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1007 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1008 priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1009 ®s->mb[i].can_ctrl);
1010 }
1011 } else {
1012 /* clear and invalidate unused mailboxes first */
1013 for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < ARRAY_SIZE(regs->mb); i++) {
1014 priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1015 ®s->mb[i].can_ctrl);
1016 }
1017 }
1018
1019 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
1020 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1021 &priv->tx_mb_reserved->can_ctrl);
1022
1023 /* mark TX mailbox as INACTIVE */
1024 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1025 ®s->mb[FLEXCAN_TX_MB].can_ctrl);
1026
1027 /* acceptance mask/acceptance code (accept everything) */
1028 priv->write(0x0, ®s->rxgmask);
1029 priv->write(0x0, ®s->rx14mask);
1030 priv->write(0x0, ®s->rx15mask);
1031
1032 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1033 priv->write(0x0, ®s->rxfgmask);
1034
1035 /* clear acceptance filters */
1036 for (i = 0; i < ARRAY_SIZE(regs->mb); i++)
1037 priv->write(0, ®s->rximr[i]);
1038
1039 /* On Vybrid, disable memory error detection interrupts
1040 * and freeze mode.
1041 * This also works around errata e5295 which generates
1042 * false positive memory errors and put the device in
1043 * freeze mode.
1044 */
1045 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1046 /* Follow the protocol as described in "Detection
1047 * and Correction of Memory Errors" to write to
1048 * MECR register
1049 */
1050 reg_ctrl2 = priv->read(®s->ctrl2);
1051 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1052 priv->write(reg_ctrl2, ®s->ctrl2);
1053
1054 reg_mecr = priv->read(®s->mecr);
1055 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1056 priv->write(reg_mecr, ®s->mecr);
1057 reg_mecr |= FLEXCAN_MECR_ECCDIS;
1058 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1059 FLEXCAN_MECR_FANCEI_MSK);
1060 priv->write(reg_mecr, ®s->mecr);
1061 }
1062
1063 err = flexcan_transceiver_enable(priv);
1064 if (err)
1065 goto out_chip_disable;
1066
1067 /* synchronize with the can bus */
1068 err = flexcan_chip_unfreeze(priv);
1069 if (err)
1070 goto out_transceiver_disable;
1071
1072 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1073
1074 /* enable interrupts atomically */
1075 disable_irq(dev->irq);
1076 priv->write(priv->reg_ctrl_default, ®s->ctrl);
1077 priv->write(priv->reg_imask1_default, ®s->imask1);
1078 priv->write(priv->reg_imask2_default, ®s->imask2);
1079 enable_irq(dev->irq);
1080
1081 /* print chip status */
1082 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1083 priv->read(®s->mcr), priv->read(®s->ctrl));
1084
1085 return 0;
1086
1087 out_transceiver_disable:
1088 flexcan_transceiver_disable(priv);
1089 out_chip_disable:
1090 flexcan_chip_disable(priv);
1091 return err;
1092 }
1093
1094 /* __flexcan_chip_stop
1095 *
1096 * this function is entered with clocks enabled
1097 */
__flexcan_chip_stop(struct net_device * dev,bool disable_on_error)1098 static int __flexcan_chip_stop(struct net_device *dev, bool disable_on_error)
1099 {
1100 struct flexcan_priv *priv = netdev_priv(dev);
1101 struct flexcan_regs __iomem *regs = priv->regs;
1102 int err;
1103
1104 /* freeze + disable module */
1105 err = flexcan_chip_freeze(priv);
1106 if (err && !disable_on_error)
1107 return err;
1108 err = flexcan_chip_disable(priv);
1109 if (err && !disable_on_error)
1110 goto out_chip_unfreeze;
1111
1112 /* Disable all interrupts */
1113 priv->write(0, ®s->imask2);
1114 priv->write(0, ®s->imask1);
1115 priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1116 ®s->ctrl);
1117
1118 flexcan_transceiver_disable(priv);
1119 priv->can.state = CAN_STATE_STOPPED;
1120
1121 return 0;
1122
1123 out_chip_unfreeze:
1124 flexcan_chip_unfreeze(priv);
1125
1126 return err;
1127 }
1128
flexcan_chip_stop_disable_on_error(struct net_device * dev)1129 static inline int flexcan_chip_stop_disable_on_error(struct net_device *dev)
1130 {
1131 return __flexcan_chip_stop(dev, true);
1132 }
1133
flexcan_chip_stop(struct net_device * dev)1134 static inline int flexcan_chip_stop(struct net_device *dev)
1135 {
1136 return __flexcan_chip_stop(dev, false);
1137 }
1138
flexcan_open(struct net_device * dev)1139 static int flexcan_open(struct net_device *dev)
1140 {
1141 struct flexcan_priv *priv = netdev_priv(dev);
1142 int err;
1143
1144 err = clk_prepare_enable(priv->clk_ipg);
1145 if (err)
1146 return err;
1147
1148 err = clk_prepare_enable(priv->clk_per);
1149 if (err)
1150 goto out_disable_ipg;
1151
1152 err = open_candev(dev);
1153 if (err)
1154 goto out_disable_per;
1155
1156 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1157 if (err)
1158 goto out_close;
1159
1160 /* start chip and queuing */
1161 err = flexcan_chip_start(dev);
1162 if (err)
1163 goto out_free_irq;
1164
1165 can_led_event(dev, CAN_LED_EVENT_OPEN);
1166
1167 can_rx_offload_enable(&priv->offload);
1168 netif_start_queue(dev);
1169
1170 return 0;
1171
1172 out_free_irq:
1173 free_irq(dev->irq, dev);
1174 out_close:
1175 close_candev(dev);
1176 out_disable_per:
1177 clk_disable_unprepare(priv->clk_per);
1178 out_disable_ipg:
1179 clk_disable_unprepare(priv->clk_ipg);
1180
1181 return err;
1182 }
1183
flexcan_close(struct net_device * dev)1184 static int flexcan_close(struct net_device *dev)
1185 {
1186 struct flexcan_priv *priv = netdev_priv(dev);
1187
1188 netif_stop_queue(dev);
1189 can_rx_offload_disable(&priv->offload);
1190 flexcan_chip_stop_disable_on_error(dev);
1191
1192 free_irq(dev->irq, dev);
1193 clk_disable_unprepare(priv->clk_per);
1194 clk_disable_unprepare(priv->clk_ipg);
1195
1196 close_candev(dev);
1197
1198 can_led_event(dev, CAN_LED_EVENT_STOP);
1199
1200 return 0;
1201 }
1202
flexcan_set_mode(struct net_device * dev,enum can_mode mode)1203 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1204 {
1205 int err;
1206
1207 switch (mode) {
1208 case CAN_MODE_START:
1209 err = flexcan_chip_start(dev);
1210 if (err)
1211 return err;
1212
1213 netif_wake_queue(dev);
1214 break;
1215
1216 default:
1217 return -EOPNOTSUPP;
1218 }
1219
1220 return 0;
1221 }
1222
1223 static const struct net_device_ops flexcan_netdev_ops = {
1224 .ndo_open = flexcan_open,
1225 .ndo_stop = flexcan_close,
1226 .ndo_start_xmit = flexcan_start_xmit,
1227 .ndo_change_mtu = can_change_mtu,
1228 };
1229
register_flexcandev(struct net_device * dev)1230 static int register_flexcandev(struct net_device *dev)
1231 {
1232 struct flexcan_priv *priv = netdev_priv(dev);
1233 struct flexcan_regs __iomem *regs = priv->regs;
1234 u32 reg, err;
1235
1236 err = clk_prepare_enable(priv->clk_ipg);
1237 if (err)
1238 return err;
1239
1240 err = clk_prepare_enable(priv->clk_per);
1241 if (err)
1242 goto out_disable_ipg;
1243
1244 /* select "bus clock", chip must be disabled */
1245 err = flexcan_chip_disable(priv);
1246 if (err)
1247 goto out_disable_per;
1248 reg = priv->read(®s->ctrl);
1249 reg |= FLEXCAN_CTRL_CLK_SRC;
1250 priv->write(reg, ®s->ctrl);
1251
1252 err = flexcan_chip_enable(priv);
1253 if (err)
1254 goto out_chip_disable;
1255
1256 /* set freeze, halt and activate FIFO, restrict register access */
1257 reg = priv->read(®s->mcr);
1258 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1259 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1260 priv->write(reg, ®s->mcr);
1261
1262 /* Currently we only support newer versions of this core
1263 * featuring a RX hardware FIFO (although this driver doesn't
1264 * make use of it on some cores). Older cores, found on some
1265 * Coldfire derivates are not tested.
1266 */
1267 reg = priv->read(®s->mcr);
1268 if (!(reg & FLEXCAN_MCR_FEN)) {
1269 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1270 err = -ENODEV;
1271 goto out_chip_disable;
1272 }
1273
1274 err = register_candev(dev);
1275
1276 /* disable core and turn off clocks */
1277 out_chip_disable:
1278 flexcan_chip_disable(priv);
1279 out_disable_per:
1280 clk_disable_unprepare(priv->clk_per);
1281 out_disable_ipg:
1282 clk_disable_unprepare(priv->clk_ipg);
1283
1284 return err;
1285 }
1286
unregister_flexcandev(struct net_device * dev)1287 static void unregister_flexcandev(struct net_device *dev)
1288 {
1289 unregister_candev(dev);
1290 }
1291
1292 static const struct of_device_id flexcan_of_match[] = {
1293 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1294 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1295 { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
1296 { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
1297 { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
1298 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1299 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1300 { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
1301 { /* sentinel */ },
1302 };
1303 MODULE_DEVICE_TABLE(of, flexcan_of_match);
1304
1305 static const struct platform_device_id flexcan_id_table[] = {
1306 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1307 { /* sentinel */ },
1308 };
1309 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1310
flexcan_probe(struct platform_device * pdev)1311 static int flexcan_probe(struct platform_device *pdev)
1312 {
1313 const struct of_device_id *of_id;
1314 const struct flexcan_devtype_data *devtype_data;
1315 struct net_device *dev;
1316 struct flexcan_priv *priv;
1317 struct regulator *reg_xceiver;
1318 struct resource *mem;
1319 struct clk *clk_ipg = NULL, *clk_per = NULL;
1320 struct flexcan_regs __iomem *regs;
1321 int err, irq;
1322 u32 clock_freq = 0;
1323
1324 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1325 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1326 return -EPROBE_DEFER;
1327 else if (IS_ERR(reg_xceiver))
1328 reg_xceiver = NULL;
1329
1330 if (pdev->dev.of_node)
1331 of_property_read_u32(pdev->dev.of_node,
1332 "clock-frequency", &clock_freq);
1333
1334 if (!clock_freq) {
1335 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1336 if (IS_ERR(clk_ipg)) {
1337 dev_err(&pdev->dev, "no ipg clock defined\n");
1338 return PTR_ERR(clk_ipg);
1339 }
1340
1341 clk_per = devm_clk_get(&pdev->dev, "per");
1342 if (IS_ERR(clk_per)) {
1343 dev_err(&pdev->dev, "no per clock defined\n");
1344 return PTR_ERR(clk_per);
1345 }
1346 clock_freq = clk_get_rate(clk_per);
1347 }
1348
1349 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1350 irq = platform_get_irq(pdev, 0);
1351 if (irq <= 0)
1352 return -ENODEV;
1353
1354 regs = devm_ioremap_resource(&pdev->dev, mem);
1355 if (IS_ERR(regs))
1356 return PTR_ERR(regs);
1357
1358 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1359 if (of_id) {
1360 devtype_data = of_id->data;
1361 } else if (platform_get_device_id(pdev)->driver_data) {
1362 devtype_data = (struct flexcan_devtype_data *)
1363 platform_get_device_id(pdev)->driver_data;
1364 } else {
1365 return -ENODEV;
1366 }
1367
1368 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1369 if (!dev)
1370 return -ENOMEM;
1371
1372 platform_set_drvdata(pdev, dev);
1373 SET_NETDEV_DEV(dev, &pdev->dev);
1374
1375 dev->netdev_ops = &flexcan_netdev_ops;
1376 dev->irq = irq;
1377 dev->flags |= IFF_ECHO;
1378
1379 priv = netdev_priv(dev);
1380
1381 if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
1382 devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
1383 priv->read = flexcan_read_be;
1384 priv->write = flexcan_write_be;
1385 } else {
1386 priv->read = flexcan_read_le;
1387 priv->write = flexcan_write_le;
1388 }
1389
1390 priv->can.clock.freq = clock_freq;
1391 priv->can.bittiming_const = &flexcan_bittiming_const;
1392 priv->can.do_set_mode = flexcan_set_mode;
1393 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1394 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1395 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1396 CAN_CTRLMODE_BERR_REPORTING;
1397 priv->regs = regs;
1398 priv->clk_ipg = clk_ipg;
1399 priv->clk_per = clk_per;
1400 priv->devtype_data = devtype_data;
1401 priv->reg_xceiver = reg_xceiver;
1402
1403 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1404 priv->tx_mb_reserved = ®s->mb[FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP];
1405 else
1406 priv->tx_mb_reserved = ®s->mb[FLEXCAN_TX_MB_RESERVED_OFF_FIFO];
1407
1408 priv->reg_imask1_default = 0;
1409 priv->reg_imask2_default = FLEXCAN_IFLAG_MB(FLEXCAN_TX_MB);
1410
1411 priv->offload.mailbox_read = flexcan_mailbox_read;
1412
1413 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1414 u64 imask;
1415
1416 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1417 priv->offload.mb_last = FLEXCAN_RX_MB_OFF_TIMESTAMP_LAST;
1418
1419 imask = GENMASK_ULL(priv->offload.mb_last, priv->offload.mb_first);
1420 priv->reg_imask1_default |= imask;
1421 priv->reg_imask2_default |= imask >> 32;
1422
1423 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1424 } else {
1425 priv->reg_imask1_default |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1426 FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1427 err = can_rx_offload_add_fifo(dev, &priv->offload, FLEXCAN_NAPI_WEIGHT);
1428 }
1429 if (err)
1430 goto failed_offload;
1431
1432 err = register_flexcandev(dev);
1433 if (err) {
1434 dev_err(&pdev->dev, "registering netdev failed\n");
1435 goto failed_register;
1436 }
1437
1438 devm_can_led_init(dev);
1439
1440 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1441 priv->regs, dev->irq);
1442
1443 return 0;
1444
1445 failed_offload:
1446 failed_register:
1447 free_candev(dev);
1448 return err;
1449 }
1450
flexcan_remove(struct platform_device * pdev)1451 static int flexcan_remove(struct platform_device *pdev)
1452 {
1453 struct net_device *dev = platform_get_drvdata(pdev);
1454 struct flexcan_priv *priv = netdev_priv(dev);
1455
1456 unregister_flexcandev(dev);
1457 can_rx_offload_del(&priv->offload);
1458 free_candev(dev);
1459
1460 return 0;
1461 }
1462
flexcan_suspend(struct device * device)1463 static int __maybe_unused flexcan_suspend(struct device *device)
1464 {
1465 struct net_device *dev = dev_get_drvdata(device);
1466 struct flexcan_priv *priv = netdev_priv(dev);
1467 int err;
1468
1469 if (netif_running(dev)) {
1470 err = flexcan_chip_disable(priv);
1471 if (err)
1472 return err;
1473 netif_stop_queue(dev);
1474 netif_device_detach(dev);
1475 }
1476 priv->can.state = CAN_STATE_SLEEPING;
1477
1478 return 0;
1479 }
1480
flexcan_resume(struct device * device)1481 static int __maybe_unused flexcan_resume(struct device *device)
1482 {
1483 struct net_device *dev = dev_get_drvdata(device);
1484 struct flexcan_priv *priv = netdev_priv(dev);
1485 int err;
1486
1487 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1488 if (netif_running(dev)) {
1489 netif_device_attach(dev);
1490 netif_start_queue(dev);
1491 err = flexcan_chip_enable(priv);
1492 if (err)
1493 return err;
1494 }
1495 return 0;
1496 }
1497
1498 static SIMPLE_DEV_PM_OPS(flexcan_pm_ops, flexcan_suspend, flexcan_resume);
1499
1500 static struct platform_driver flexcan_driver = {
1501 .driver = {
1502 .name = DRV_NAME,
1503 .pm = &flexcan_pm_ops,
1504 .of_match_table = flexcan_of_match,
1505 },
1506 .probe = flexcan_probe,
1507 .remove = flexcan_remove,
1508 .id_table = flexcan_id_table,
1509 };
1510
1511 module_platform_driver(flexcan_driver);
1512
1513 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1514 "Marc Kleine-Budde <kernel@pengutronix.de>");
1515 MODULE_LICENSE("GPL v2");
1516 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
1517