Lines Matching +full:cs +full:- +full:out
24 #include <linux/dma-mapping.h>
40 #include <linux/platform_data/spi-omap2-mcspi.h>
57 /* per-channel banks, 0x14 bytes each, first is: */
64 /* per-register bitmasks: */
100 /* We have 2 DMA channels per CS, one for RX and one for TX */
125 struct list_head cs; member
156 writel_relaxed(val, mcspi->base + idx); in mcspi_write_reg()
163 return readl_relaxed(mcspi->base + idx); in mcspi_read_reg()
169 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_cs_reg() local
171 writel_relaxed(val, cs->base + idx); in mcspi_write_cs_reg()
176 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_read_cs_reg() local
178 return readl_relaxed(cs->base + idx); in mcspi_read_cs_reg()
183 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_cached_chconf0() local
185 return cs->chconf0; in mcspi_cached_chconf0()
190 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_chconf0() local
192 cs->chconf0 = val; in mcspi_write_chconf0()
229 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_set_enable() local
232 l = cs->chctrl0; in omap2_mcspi_set_enable()
237 cs->chctrl0 = l; in omap2_mcspi_set_enable()
238 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); in omap2_mcspi_set_enable()
239 /* Flash post-writes */ in omap2_mcspi_set_enable()
245 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_set_cs()
252 if (spi->mode & SPI_CS_HIGH) in omap2_mcspi_set_cs()
255 if (spi->controller_state) { in omap2_mcspi_set_cs()
256 int err = pm_runtime_get_sync(mcspi->dev); in omap2_mcspi_set_cs()
258 pm_runtime_put_noidle(mcspi->dev); in omap2_mcspi_set_cs()
259 dev_err(mcspi->dev, "failed to get sync: %d\n", err); in omap2_mcspi_set_cs()
272 pm_runtime_mark_last_busy(mcspi->dev); in omap2_mcspi_set_cs()
273 pm_runtime_put_autosuspend(mcspi->dev); in omap2_mcspi_set_cs()
280 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap2_mcspi_set_master_mode()
285 * to single-channel master mode in omap2_mcspi_set_master_mode()
292 ctx->modulctrl = l; in omap2_mcspi_set_master_mode()
298 struct spi_master *master = spi->master; in omap2_mcspi_set_fifo()
299 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_set_fifo() local
309 bytes_per_word = mcspi_bytes_per_word(cs->word_len); in omap2_mcspi_set_fifo()
310 if (t->len % bytes_per_word != 0) in omap2_mcspi_set_fifo()
313 if (t->rx_buf != NULL && t->tx_buf != NULL) in omap2_mcspi_set_fifo()
318 wcnt = t->len / bytes_per_word; in omap2_mcspi_set_fifo()
323 if (t->rx_buf != NULL) { in omap2_mcspi_set_fifo()
325 xferlevel |= (bytes_per_word - 1) << 8; in omap2_mcspi_set_fifo()
328 if (t->tx_buf != NULL) { in omap2_mcspi_set_fifo()
330 xferlevel |= bytes_per_word - 1; in omap2_mcspi_set_fifo()
335 mcspi->fifo_depth = max_fifo_depth; in omap2_mcspi_set_fifo()
341 if (t->rx_buf != NULL) in omap2_mcspi_set_fifo()
344 if (t->tx_buf != NULL) in omap2_mcspi_set_fifo()
348 mcspi->fifo_depth = 0; in omap2_mcspi_set_fifo()
359 return -ETIMEDOUT; in mcspi_wait_for_reg_bit()
371 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_rx_callback()
372 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_rx_callback()
377 complete(&mcspi_dma->dma_rx_completion); in omap2_mcspi_rx_callback()
383 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_tx_callback()
384 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_tx_callback()
389 complete(&mcspi_dma->dma_tx_completion); in omap2_mcspi_tx_callback()
399 mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_tx_dma()
400 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_tx_dma()
402 if (mcspi_dma->dma_tx) { in omap2_mcspi_tx_dma()
405 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); in omap2_mcspi_tx_dma()
407 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl, in omap2_mcspi_tx_dma()
408 xfer->tx_sg.nents, in omap2_mcspi_tx_dma()
412 tx->callback = omap2_mcspi_tx_callback; in omap2_mcspi_tx_dma()
413 tx->callback_param = spi; in omap2_mcspi_tx_dma()
419 dma_async_issue_pending(mcspi_dma->dma_tx); in omap2_mcspi_tx_dma()
438 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_rx_dma() local
439 void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; in omap2_mcspi_rx_dma()
441 mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_rx_dma()
442 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_rx_dma()
443 count = xfer->len; in omap2_mcspi_rx_dma()
446 * In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM in omap2_mcspi_rx_dma()
450 if (mcspi->fifo_depth == 0) in omap2_mcspi_rx_dma()
453 word_len = cs->word_len; in omap2_mcspi_rx_dma()
463 if (mcspi_dma->dma_rx) { in omap2_mcspi_rx_dma()
466 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); in omap2_mcspi_rx_dma()
472 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0) in omap2_mcspi_rx_dma()
477 sizes[0] = count - transfer_reduction; in omap2_mcspi_rx_dma()
489 ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents, in omap2_mcspi_rx_dma()
496 dev_err(&spi->dev, "sg_split failed\n"); in omap2_mcspi_rx_dma()
500 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, in omap2_mcspi_rx_dma()
506 tx->callback = omap2_mcspi_rx_callback; in omap2_mcspi_rx_dma()
507 tx->callback_param = spi; in omap2_mcspi_rx_dma()
514 dma_async_issue_pending(mcspi_dma->dma_rx); in omap2_mcspi_rx_dma()
517 wait_for_completion(&mcspi_dma->dma_rx_completion); in omap2_mcspi_rx_dma()
522 if (mcspi->fifo_depth > 0) in omap2_mcspi_rx_dma()
531 elements = element_count - 1; in omap2_mcspi_rx_dma()
534 elements--; in omap2_mcspi_rx_dma()
542 ((u8 *)xfer->rx_buf)[elements++] = w; in omap2_mcspi_rx_dma()
544 ((u16 *)xfer->rx_buf)[elements++] = w; in omap2_mcspi_rx_dma()
546 ((u32 *)xfer->rx_buf)[elements++] = w; in omap2_mcspi_rx_dma()
549 dev_err(&spi->dev, "DMA RX penultimate word empty\n"); in omap2_mcspi_rx_dma()
550 count -= (bytes_per_word << 1); in omap2_mcspi_rx_dma()
560 ((u8 *)xfer->rx_buf)[elements] = w; in omap2_mcspi_rx_dma()
562 ((u16 *)xfer->rx_buf)[elements] = w; in omap2_mcspi_rx_dma()
564 ((u32 *)xfer->rx_buf)[elements] = w; in omap2_mcspi_rx_dma()
566 dev_err(&spi->dev, "DMA RX last word empty\n"); in omap2_mcspi_rx_dma()
567 count -= mcspi_bytes_per_word(word_len); in omap2_mcspi_rx_dma()
577 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_txrx_dma() local
589 mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_txrx_dma()
590 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_txrx_dma()
592 if (cs->word_len <= 8) { in omap2_mcspi_txrx_dma()
595 } else if (cs->word_len <= 16) { in omap2_mcspi_txrx_dma()
603 count = xfer->len; in omap2_mcspi_txrx_dma()
606 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; in omap2_mcspi_txrx_dma()
607 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; in omap2_mcspi_txrx_dma()
613 rx = xfer->rx_buf; in omap2_mcspi_txrx_dma()
614 tx = xfer->tx_buf; in omap2_mcspi_txrx_dma()
623 wait_for_completion(&mcspi_dma->dma_tx_completion); in omap2_mcspi_txrx_dma()
625 if (mcspi->fifo_depth > 0) { in omap2_mcspi_txrx_dma()
626 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS; in omap2_mcspi_txrx_dma()
630 dev_err(&spi->dev, "EOW timed out\n"); in omap2_mcspi_txrx_dma()
632 mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS, in omap2_mcspi_txrx_dma()
636 /* for TX_ONLY mode, be sure all words have shifted out */ in omap2_mcspi_txrx_dma()
638 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; in omap2_mcspi_txrx_dma()
639 if (mcspi->fifo_depth > 0) { in omap2_mcspi_txrx_dma()
643 dev_err(&spi->dev, "TXFFE timed out\n"); in omap2_mcspi_txrx_dma()
648 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_dma()
653 dev_err(&spi->dev, "EOT timed out\n"); in omap2_mcspi_txrx_dma()
662 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_txrx_pio() local
665 void __iomem *base = cs->base; in omap2_mcspi_txrx_pio()
671 count = xfer->len; in omap2_mcspi_txrx_pio()
673 word_len = cs->word_len; in omap2_mcspi_txrx_pio()
677 /* We store the pre-calculated register addresses on stack to speed in omap2_mcspi_txrx_pio()
690 rx = xfer->rx_buf; in omap2_mcspi_txrx_pio()
691 tx = xfer->tx_buf; in omap2_mcspi_txrx_pio()
694 c -= 1; in omap2_mcspi_txrx_pio()
698 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
699 goto out; in omap2_mcspi_txrx_pio()
701 dev_vdbg(&spi->dev, "write-%d %02x\n", in omap2_mcspi_txrx_pio()
708 dev_err(&spi->dev, "RXS timed out\n"); in omap2_mcspi_txrx_pio()
709 goto out; in omap2_mcspi_txrx_pio()
716 dev_vdbg(&spi->dev, "read-%d %02x\n", in omap2_mcspi_txrx_pio()
717 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
720 dev_err(&spi->dev, in omap2_mcspi_txrx_pio()
721 "RXS timed out\n"); in omap2_mcspi_txrx_pio()
722 goto out; in omap2_mcspi_txrx_pio()
730 dev_vdbg(&spi->dev, "read-%d %02x\n", in omap2_mcspi_txrx_pio()
731 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
738 rx = xfer->rx_buf; in omap2_mcspi_txrx_pio()
739 tx = xfer->tx_buf; in omap2_mcspi_txrx_pio()
741 c -= 2; in omap2_mcspi_txrx_pio()
745 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
746 goto out; in omap2_mcspi_txrx_pio()
748 dev_vdbg(&spi->dev, "write-%d %04x\n", in omap2_mcspi_txrx_pio()
755 dev_err(&spi->dev, "RXS timed out\n"); in omap2_mcspi_txrx_pio()
756 goto out; in omap2_mcspi_txrx_pio()
763 dev_vdbg(&spi->dev, "read-%d %04x\n", in omap2_mcspi_txrx_pio()
764 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
767 dev_err(&spi->dev, in omap2_mcspi_txrx_pio()
768 "RXS timed out\n"); in omap2_mcspi_txrx_pio()
769 goto out; in omap2_mcspi_txrx_pio()
777 dev_vdbg(&spi->dev, "read-%d %04x\n", in omap2_mcspi_txrx_pio()
778 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
785 rx = xfer->rx_buf; in omap2_mcspi_txrx_pio()
786 tx = xfer->tx_buf; in omap2_mcspi_txrx_pio()
788 c -= 4; in omap2_mcspi_txrx_pio()
792 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
793 goto out; in omap2_mcspi_txrx_pio()
795 dev_vdbg(&spi->dev, "write-%d %08x\n", in omap2_mcspi_txrx_pio()
802 dev_err(&spi->dev, "RXS timed out\n"); in omap2_mcspi_txrx_pio()
803 goto out; in omap2_mcspi_txrx_pio()
810 dev_vdbg(&spi->dev, "read-%d %08x\n", in omap2_mcspi_txrx_pio()
811 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
814 dev_err(&spi->dev, in omap2_mcspi_txrx_pio()
815 "RXS timed out\n"); in omap2_mcspi_txrx_pio()
816 goto out; in omap2_mcspi_txrx_pio()
824 dev_vdbg(&spi->dev, "read-%d %08x\n", in omap2_mcspi_txrx_pio()
825 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
830 /* for TX_ONLY mode, be sure all words have shifted out */ in omap2_mcspi_txrx_pio()
831 if (xfer->rx_buf == NULL) { in omap2_mcspi_txrx_pio()
834 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
837 dev_err(&spi->dev, "EOT timed out\n"); in omap2_mcspi_txrx_pio()
845 out: in omap2_mcspi_txrx_pio()
847 return count - c; in omap2_mcspi_txrx_pio()
865 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_setup_transfer() local
868 u8 word_len = spi->bits_per_word; in omap2_mcspi_setup_transfer()
869 u32 speed_hz = spi->max_speed_hz; in omap2_mcspi_setup_transfer()
871 mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_setup_transfer()
873 if (t != NULL && t->bits_per_word) in omap2_mcspi_setup_transfer()
874 word_len = t->bits_per_word; in omap2_mcspi_setup_transfer()
876 cs->word_len = word_len; in omap2_mcspi_setup_transfer()
878 if (t && t->speed_hz) in omap2_mcspi_setup_transfer()
879 speed_hz = t->speed_hz; in omap2_mcspi_setup_transfer()
887 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz; in omap2_mcspi_setup_transfer()
889 clkd = (div - 1) & 0xf; in omap2_mcspi_setup_transfer()
890 extclk = (div - 1) >> 4; in omap2_mcspi_setup_transfer()
896 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS in omap2_mcspi_setup_transfer()
899 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { in omap2_mcspi_setup_transfer()
911 l |= (word_len - 1) << 7; in omap2_mcspi_setup_transfer()
914 if (!(spi->mode & SPI_CS_HIGH)) in omap2_mcspi_setup_transfer()
915 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ in omap2_mcspi_setup_transfer()
927 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK; in omap2_mcspi_setup_transfer()
928 cs->chctrl0 |= extclk << 8; in omap2_mcspi_setup_transfer()
929 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); in omap2_mcspi_setup_transfer()
933 if (spi->mode & SPI_CPOL) in omap2_mcspi_setup_transfer()
937 if (spi->mode & SPI_CPHA) in omap2_mcspi_setup_transfer()
944 cs->mode = spi->mode; in omap2_mcspi_setup_transfer()
946 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", in omap2_mcspi_setup_transfer()
948 (spi->mode & SPI_CPHA) ? "trailing" : "leading", in omap2_mcspi_setup_transfer()
949 (spi->mode & SPI_CPOL) ? "inverted" : "normal"); in omap2_mcspi_setup_transfer()
960 struct spi_master *master = spi->master; in omap2_mcspi_request_dma()
966 mcspi_dma = mcspi->dma_channels + spi->chip_select; in omap2_mcspi_request_dma()
968 init_completion(&mcspi_dma->dma_rx_completion); in omap2_mcspi_request_dma()
969 init_completion(&mcspi_dma->dma_tx_completion); in omap2_mcspi_request_dma()
971 mcspi_dma->dma_rx = dma_request_chan(&master->dev, in omap2_mcspi_request_dma()
972 mcspi_dma->dma_rx_ch_name); in omap2_mcspi_request_dma()
973 if (IS_ERR(mcspi_dma->dma_rx)) { in omap2_mcspi_request_dma()
974 ret = PTR_ERR(mcspi_dma->dma_rx); in omap2_mcspi_request_dma()
975 mcspi_dma->dma_rx = NULL; in omap2_mcspi_request_dma()
979 mcspi_dma->dma_tx = dma_request_chan(&master->dev, in omap2_mcspi_request_dma()
980 mcspi_dma->dma_tx_ch_name); in omap2_mcspi_request_dma()
981 if (IS_ERR(mcspi_dma->dma_tx)) { in omap2_mcspi_request_dma()
982 ret = PTR_ERR(mcspi_dma->dma_tx); in omap2_mcspi_request_dma()
983 mcspi_dma->dma_tx = NULL; in omap2_mcspi_request_dma()
984 dma_release_channel(mcspi_dma->dma_rx); in omap2_mcspi_request_dma()
985 mcspi_dma->dma_rx = NULL; in omap2_mcspi_request_dma()
995 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_setup()
996 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap2_mcspi_setup()
998 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_setup() local
1000 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_setup()
1002 if (!cs) { in omap2_mcspi_setup()
1003 cs = kzalloc(sizeof *cs, GFP_KERNEL); in omap2_mcspi_setup()
1004 if (!cs) in omap2_mcspi_setup()
1005 return -ENOMEM; in omap2_mcspi_setup()
1006 cs->base = mcspi->base + spi->chip_select * 0x14; in omap2_mcspi_setup()
1007 cs->phys = mcspi->phys + spi->chip_select * 0x14; in omap2_mcspi_setup()
1008 cs->mode = 0; in omap2_mcspi_setup()
1009 cs->chconf0 = 0; in omap2_mcspi_setup()
1010 cs->chctrl0 = 0; in omap2_mcspi_setup()
1011 spi->controller_state = cs; in omap2_mcspi_setup()
1013 list_add_tail(&cs->node, &ctx->cs); in omap2_mcspi_setup()
1015 if (gpio_is_valid(spi->cs_gpio)) { in omap2_mcspi_setup()
1016 ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev)); in omap2_mcspi_setup()
1018 dev_err(&spi->dev, "failed to request gpio\n"); in omap2_mcspi_setup()
1021 gpio_direction_output(spi->cs_gpio, in omap2_mcspi_setup()
1022 !(spi->mode & SPI_CS_HIGH)); in omap2_mcspi_setup()
1026 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) { in omap2_mcspi_setup()
1029 dev_warn(&spi->dev, "not using DMA for McSPI (%d)\n", in omap2_mcspi_setup()
1033 ret = pm_runtime_get_sync(mcspi->dev); in omap2_mcspi_setup()
1035 pm_runtime_put_noidle(mcspi->dev); in omap2_mcspi_setup()
1041 pm_runtime_mark_last_busy(mcspi->dev); in omap2_mcspi_setup()
1042 pm_runtime_put_autosuspend(mcspi->dev); in omap2_mcspi_setup()
1051 struct omap2_mcspi_cs *cs; in omap2_mcspi_cleanup() local
1053 mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_cleanup()
1055 if (spi->controller_state) { in omap2_mcspi_cleanup()
1057 cs = spi->controller_state; in omap2_mcspi_cleanup()
1058 list_del(&cs->node); in omap2_mcspi_cleanup()
1060 kfree(cs); in omap2_mcspi_cleanup()
1063 if (spi->chip_select < spi->master->num_chipselect) { in omap2_mcspi_cleanup()
1064 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_cleanup()
1066 if (mcspi_dma->dma_rx) { in omap2_mcspi_cleanup()
1067 dma_release_channel(mcspi_dma->dma_rx); in omap2_mcspi_cleanup()
1068 mcspi_dma->dma_rx = NULL; in omap2_mcspi_cleanup()
1070 if (mcspi_dma->dma_tx) { in omap2_mcspi_cleanup()
1071 dma_release_channel(mcspi_dma->dma_tx); in omap2_mcspi_cleanup()
1072 mcspi_dma->dma_tx = NULL; in omap2_mcspi_cleanup()
1076 if (gpio_is_valid(spi->cs_gpio)) in omap2_mcspi_cleanup()
1077 gpio_free(spi->cs_gpio); in omap2_mcspi_cleanup()
1085 /* We only enable one channel at a time -- the one whose message is in omap2_mcspi_transfer_one()
1086 * -- although this controller would gladly in omap2_mcspi_transfer_one()
1089 * chipselect with the FORCE bit ... CS != channel enable. in omap2_mcspi_transfer_one()
1094 struct omap2_mcspi_cs *cs; in omap2_mcspi_transfer_one() local
1101 mcspi_dma = mcspi->dma_channels + spi->chip_select; in omap2_mcspi_transfer_one()
1102 cs = spi->controller_state; in omap2_mcspi_transfer_one()
1103 cd = spi->controller_data; in omap2_mcspi_transfer_one()
1106 * The slave driver could have changed spi->mode in which case in omap2_mcspi_transfer_one()
1107 * it will be different from cs->mode (the current hardware setup). in omap2_mcspi_transfer_one()
1112 if (spi->mode != cs->mode) in omap2_mcspi_transfer_one()
1117 if (gpio_is_valid(spi->cs_gpio)) in omap2_mcspi_transfer_one()
1118 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH); in omap2_mcspi_transfer_one()
1121 (t->speed_hz != spi->max_speed_hz) || in omap2_mcspi_transfer_one()
1122 (t->bits_per_word != spi->bits_per_word)) { in omap2_mcspi_transfer_one()
1126 goto out; in omap2_mcspi_transfer_one()
1127 if (t->speed_hz == spi->max_speed_hz && in omap2_mcspi_transfer_one()
1128 t->bits_per_word == spi->bits_per_word) in omap2_mcspi_transfer_one()
1131 if (cd && cd->cs_per_word) { in omap2_mcspi_transfer_one()
1132 chconf = mcspi->ctx.modulctrl; in omap2_mcspi_transfer_one()
1135 mcspi->ctx.modulctrl = in omap2_mcspi_transfer_one()
1143 if (t->tx_buf == NULL) in omap2_mcspi_transfer_one()
1145 else if (t->rx_buf == NULL) in omap2_mcspi_transfer_one()
1148 if (cd && cd->turbo_mode && t->tx_buf == NULL) { in omap2_mcspi_transfer_one()
1150 if (t->len > ((cs->word_len + 7) >> 3)) in omap2_mcspi_transfer_one()
1156 if (t->len) { in omap2_mcspi_transfer_one()
1159 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && in omap2_mcspi_transfer_one()
1160 master->cur_msg_mapped && in omap2_mcspi_transfer_one()
1161 master->can_dma(master, spi, t)) in omap2_mcspi_transfer_one()
1167 if (t->tx_buf == NULL) in omap2_mcspi_transfer_one()
1168 writel_relaxed(0, cs->base in omap2_mcspi_transfer_one()
1171 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && in omap2_mcspi_transfer_one()
1172 master->cur_msg_mapped && in omap2_mcspi_transfer_one()
1173 master->can_dma(master, spi, t)) in omap2_mcspi_transfer_one()
1178 if (count != t->len) { in omap2_mcspi_transfer_one()
1179 status = -EIO; in omap2_mcspi_transfer_one()
1180 goto out; in omap2_mcspi_transfer_one()
1186 if (mcspi->fifo_depth > 0) in omap2_mcspi_transfer_one()
1189 out: in omap2_mcspi_transfer_one()
1196 if (cd && cd->cs_per_word) { in omap2_mcspi_transfer_one()
1197 chconf = mcspi->ctx.modulctrl; in omap2_mcspi_transfer_one()
1200 mcspi->ctx.modulctrl = in omap2_mcspi_transfer_one()
1206 if (gpio_is_valid(spi->cs_gpio)) in omap2_mcspi_transfer_one()
1207 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH)); in omap2_mcspi_transfer_one()
1209 if (mcspi->fifo_depth > 0 && t) in omap2_mcspi_transfer_one()
1219 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap2_mcspi_prepare_message()
1220 struct omap2_mcspi_cs *cs; in omap2_mcspi_prepare_message() local
1227 list_for_each_entry(cs, &ctx->cs, node) { in omap2_mcspi_prepare_message()
1228 if (msg->spi->controller_state == cs) in omap2_mcspi_prepare_message()
1231 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) { in omap2_mcspi_prepare_message()
1232 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; in omap2_mcspi_prepare_message()
1233 writel_relaxed(cs->chconf0, in omap2_mcspi_prepare_message()
1234 cs->base + OMAP2_MCSPI_CHCONF0); in omap2_mcspi_prepare_message()
1235 readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0); in omap2_mcspi_prepare_message()
1246 return (xfer->len >= DMA_MIN_BYTES); in omap2_mcspi_can_dma()
1251 struct spi_master *master = mcspi->master; in omap2_mcspi_master_setup()
1252 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap2_mcspi_master_setup()
1255 ret = pm_runtime_get_sync(mcspi->dev); in omap2_mcspi_master_setup()
1257 pm_runtime_put_noidle(mcspi->dev); in omap2_mcspi_master_setup()
1264 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; in omap2_mcspi_master_setup()
1267 pm_runtime_mark_last_busy(mcspi->dev); in omap2_mcspi_master_setup()
1268 pm_runtime_put_autosuspend(mcspi->dev); in omap2_mcspi_master_setup()
1273 * When SPI wake up from off-mode, CS is in activate state. If it was in
1281 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap_mcspi_runtime_resume()
1282 struct omap2_mcspi_cs *cs; in omap_mcspi_runtime_resume() local
1285 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); in omap_mcspi_runtime_resume()
1286 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); in omap_mcspi_runtime_resume()
1288 list_for_each_entry(cs, &ctx->cs, node) { in omap_mcspi_runtime_resume()
1290 * We need to toggle CS state for OMAP take this in omap_mcspi_runtime_resume()
1293 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { in omap_mcspi_runtime_resume()
1294 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; in omap_mcspi_runtime_resume()
1295 writel_relaxed(cs->chconf0, in omap_mcspi_runtime_resume()
1296 cs->base + OMAP2_MCSPI_CHCONF0); in omap_mcspi_runtime_resume()
1297 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; in omap_mcspi_runtime_resume()
1298 writel_relaxed(cs->chconf0, in omap_mcspi_runtime_resume()
1299 cs->base + OMAP2_MCSPI_CHCONF0); in omap_mcspi_runtime_resume()
1301 writel_relaxed(cs->chconf0, in omap_mcspi_runtime_resume()
1302 cs->base + OMAP2_MCSPI_CHCONF0); in omap_mcspi_runtime_resume()
1319 .compatible = "ti,omap2-mcspi",
1323 .compatible = "ti,omap4-mcspi",
1338 struct device_node *node = pdev->dev.of_node; in omap2_mcspi_probe()
1341 master = spi_alloc_master(&pdev->dev, sizeof *mcspi); in omap2_mcspi_probe()
1343 dev_dbg(&pdev->dev, "master allocation failed\n"); in omap2_mcspi_probe()
1344 return -ENOMEM; in omap2_mcspi_probe()
1347 /* the spi->mode bits understood by this driver: */ in omap2_mcspi_probe()
1348 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; in omap2_mcspi_probe()
1349 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in omap2_mcspi_probe()
1350 master->setup = omap2_mcspi_setup; in omap2_mcspi_probe()
1351 master->auto_runtime_pm = true; in omap2_mcspi_probe()
1352 master->prepare_message = omap2_mcspi_prepare_message; in omap2_mcspi_probe()
1353 master->can_dma = omap2_mcspi_can_dma; in omap2_mcspi_probe()
1354 master->transfer_one = omap2_mcspi_transfer_one; in omap2_mcspi_probe()
1355 master->set_cs = omap2_mcspi_set_cs; in omap2_mcspi_probe()
1356 master->cleanup = omap2_mcspi_cleanup; in omap2_mcspi_probe()
1357 master->dev.of_node = node; in omap2_mcspi_probe()
1358 master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ; in omap2_mcspi_probe()
1359 master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15; in omap2_mcspi_probe()
1364 mcspi->master = master; in omap2_mcspi_probe()
1366 match = of_match_device(omap_mcspi_of_match, &pdev->dev); in omap2_mcspi_probe()
1369 pdata = match->data; in omap2_mcspi_probe()
1371 of_property_read_u32(node, "ti,spi-num-cs", &num_cs); in omap2_mcspi_probe()
1372 master->num_chipselect = num_cs; in omap2_mcspi_probe()
1373 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL)) in omap2_mcspi_probe()
1374 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; in omap2_mcspi_probe()
1376 pdata = dev_get_platdata(&pdev->dev); in omap2_mcspi_probe()
1377 master->num_chipselect = pdata->num_cs; in omap2_mcspi_probe()
1378 mcspi->pin_dir = pdata->pin_dir; in omap2_mcspi_probe()
1380 regs_offset = pdata->regs_offset; in omap2_mcspi_probe()
1383 mcspi->base = devm_ioremap_resource(&pdev->dev, r); in omap2_mcspi_probe()
1384 if (IS_ERR(mcspi->base)) { in omap2_mcspi_probe()
1385 status = PTR_ERR(mcspi->base); in omap2_mcspi_probe()
1388 mcspi->phys = r->start + regs_offset; in omap2_mcspi_probe()
1389 mcspi->base += regs_offset; in omap2_mcspi_probe()
1391 mcspi->dev = &pdev->dev; in omap2_mcspi_probe()
1393 INIT_LIST_HEAD(&mcspi->ctx.cs); in omap2_mcspi_probe()
1395 mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect, in omap2_mcspi_probe()
1398 if (mcspi->dma_channels == NULL) { in omap2_mcspi_probe()
1399 status = -ENOMEM; in omap2_mcspi_probe()
1403 for (i = 0; i < master->num_chipselect; i++) { in omap2_mcspi_probe()
1404 sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i); in omap2_mcspi_probe()
1405 sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i); in omap2_mcspi_probe()
1408 pm_runtime_use_autosuspend(&pdev->dev); in omap2_mcspi_probe()
1409 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); in omap2_mcspi_probe()
1410 pm_runtime_enable(&pdev->dev); in omap2_mcspi_probe()
1416 status = devm_spi_register_master(&pdev->dev, master); in omap2_mcspi_probe()
1423 pm_runtime_dont_use_autosuspend(&pdev->dev); in omap2_mcspi_probe()
1424 pm_runtime_put_sync(&pdev->dev); in omap2_mcspi_probe()
1425 pm_runtime_disable(&pdev->dev); in omap2_mcspi_probe()
1436 pm_runtime_dont_use_autosuspend(mcspi->dev); in omap2_mcspi_remove()
1437 pm_runtime_put_sync(mcspi->dev); in omap2_mcspi_remove()
1438 pm_runtime_disable(&pdev->dev); in omap2_mcspi_remove()
1454 dev_warn(mcspi->dev, "%s: failed to set pins: %i\n", in omap2_mcspi_suspend()
1459 dev_warn(mcspi->dev, "%s: master suspend failed: %i\n", in omap2_mcspi_suspend()
1473 dev_warn(mcspi->dev, "%s: failed to set pins: %i\n", in omap2_mcspi_resume()
1478 dev_warn(mcspi->dev, "%s: master resume failed: %i\n", in omap2_mcspi_resume()