1 /*
2 * OMAP2 McSPI controller driver
3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrj�l� <juha.yrjola@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/interrupt.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/platform_device.h>
28 #include <linux/err.h>
29 #include <linux/clk.h>
30 #include <linux/io.h>
31 #include <linux/slab.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/of.h>
34 #include <linux/of_device.h>
35 #include <linux/gcd.h>
36
37 #include <linux/spi/spi.h>
38 #include <linux/gpio.h>
39
40 #include <linux/platform_data/spi-omap2-mcspi.h>
41
42 #define OMAP2_MCSPI_MAX_FREQ 48000000
43 #define OMAP2_MCSPI_MAX_DIVIDER 4096
44 #define OMAP2_MCSPI_MAX_FIFODEPTH 64
45 #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF
46 #define SPI_AUTOSUSPEND_TIMEOUT 2000
47
48 #define OMAP2_MCSPI_REVISION 0x00
49 #define OMAP2_MCSPI_SYSSTATUS 0x14
50 #define OMAP2_MCSPI_IRQSTATUS 0x18
51 #define OMAP2_MCSPI_IRQENABLE 0x1c
52 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
53 #define OMAP2_MCSPI_SYST 0x24
54 #define OMAP2_MCSPI_MODULCTRL 0x28
55 #define OMAP2_MCSPI_XFERLEVEL 0x7c
56
57 /* per-channel banks, 0x14 bytes each, first is: */
58 #define OMAP2_MCSPI_CHCONF0 0x2c
59 #define OMAP2_MCSPI_CHSTAT0 0x30
60 #define OMAP2_MCSPI_CHCTRL0 0x34
61 #define OMAP2_MCSPI_TX0 0x38
62 #define OMAP2_MCSPI_RX0 0x3c
63
64 /* per-register bitmasks: */
65 #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17)
66
67 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
68 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
69 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
70
71 #define OMAP2_MCSPI_CHCONF_PHA BIT(0)
72 #define OMAP2_MCSPI_CHCONF_POL BIT(1)
73 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
74 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
75 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
76 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
77 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
78 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
79 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
80 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
81 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
82 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
83 #define OMAP2_MCSPI_CHCONF_IS BIT(18)
84 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
85 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
86 #define OMAP2_MCSPI_CHCONF_FFET BIT(27)
87 #define OMAP2_MCSPI_CHCONF_FFER BIT(28)
88 #define OMAP2_MCSPI_CHCONF_CLKG BIT(29)
89
90 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
91 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
92 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
93 #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3)
94
95 #define OMAP2_MCSPI_CHCTRL_EN BIT(0)
96 #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8)
97
98 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
99
100 /* We have 2 DMA channels per CS, one for RX and one for TX */
101 struct omap2_mcspi_dma {
102 struct dma_chan *dma_tx;
103 struct dma_chan *dma_rx;
104
105 struct completion dma_tx_completion;
106 struct completion dma_rx_completion;
107
108 char dma_rx_ch_name[14];
109 char dma_tx_ch_name[14];
110 };
111
112 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
113 * cache operations; better heuristics consider wordsize and bitrate.
114 */
115 #define DMA_MIN_BYTES 160
116
117
118 /*
119 * Used for context save and restore, structure members to be updated whenever
120 * corresponding registers are modified.
121 */
122 struct omap2_mcspi_regs {
123 u32 modulctrl;
124 u32 wakeupenable;
125 struct list_head cs;
126 };
127
128 struct omap2_mcspi {
129 struct spi_master *master;
130 /* Virtual base address of the controller */
131 void __iomem *base;
132 unsigned long phys;
133 /* SPI1 has 4 channels, while SPI2 has 2 */
134 struct omap2_mcspi_dma *dma_channels;
135 struct device *dev;
136 struct omap2_mcspi_regs ctx;
137 int fifo_depth;
138 unsigned int pin_dir:1;
139 };
140
141 struct omap2_mcspi_cs {
142 void __iomem *base;
143 unsigned long phys;
144 int word_len;
145 u16 mode;
146 struct list_head node;
147 /* Context save and restore shadow register */
148 u32 chconf0, chctrl0;
149 };
150
mcspi_write_reg(struct spi_master * master,int idx,u32 val)151 static inline void mcspi_write_reg(struct spi_master *master,
152 int idx, u32 val)
153 {
154 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
155
156 writel_relaxed(val, mcspi->base + idx);
157 }
158
mcspi_read_reg(struct spi_master * master,int idx)159 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
160 {
161 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
162
163 return readl_relaxed(mcspi->base + idx);
164 }
165
mcspi_write_cs_reg(const struct spi_device * spi,int idx,u32 val)166 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
167 int idx, u32 val)
168 {
169 struct omap2_mcspi_cs *cs = spi->controller_state;
170
171 writel_relaxed(val, cs->base + idx);
172 }
173
mcspi_read_cs_reg(const struct spi_device * spi,int idx)174 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
175 {
176 struct omap2_mcspi_cs *cs = spi->controller_state;
177
178 return readl_relaxed(cs->base + idx);
179 }
180
mcspi_cached_chconf0(const struct spi_device * spi)181 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
182 {
183 struct omap2_mcspi_cs *cs = spi->controller_state;
184
185 return cs->chconf0;
186 }
187
mcspi_write_chconf0(const struct spi_device * spi,u32 val)188 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
189 {
190 struct omap2_mcspi_cs *cs = spi->controller_state;
191
192 cs->chconf0 = val;
193 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
194 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
195 }
196
mcspi_bytes_per_word(int word_len)197 static inline int mcspi_bytes_per_word(int word_len)
198 {
199 if (word_len <= 8)
200 return 1;
201 else if (word_len <= 16)
202 return 2;
203 else /* word_len <= 32 */
204 return 4;
205 }
206
omap2_mcspi_set_dma_req(const struct spi_device * spi,int is_read,int enable)207 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
208 int is_read, int enable)
209 {
210 u32 l, rw;
211
212 l = mcspi_cached_chconf0(spi);
213
214 if (is_read) /* 1 is read, 0 write */
215 rw = OMAP2_MCSPI_CHCONF_DMAR;
216 else
217 rw = OMAP2_MCSPI_CHCONF_DMAW;
218
219 if (enable)
220 l |= rw;
221 else
222 l &= ~rw;
223
224 mcspi_write_chconf0(spi, l);
225 }
226
omap2_mcspi_set_enable(const struct spi_device * spi,int enable)227 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
228 {
229 struct omap2_mcspi_cs *cs = spi->controller_state;
230 u32 l;
231
232 l = cs->chctrl0;
233 if (enable)
234 l |= OMAP2_MCSPI_CHCTRL_EN;
235 else
236 l &= ~OMAP2_MCSPI_CHCTRL_EN;
237 cs->chctrl0 = l;
238 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
239 /* Flash post-writes */
240 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
241 }
242
omap2_mcspi_set_cs(struct spi_device * spi,bool enable)243 static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
244 {
245 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
246 u32 l;
247
248 /* The controller handles the inverted chip selects
249 * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert
250 * the inversion from the core spi_set_cs function.
251 */
252 if (spi->mode & SPI_CS_HIGH)
253 enable = !enable;
254
255 if (spi->controller_state) {
256 int err = pm_runtime_get_sync(mcspi->dev);
257 if (err < 0) {
258 pm_runtime_put_noidle(mcspi->dev);
259 dev_err(mcspi->dev, "failed to get sync: %d\n", err);
260 return;
261 }
262
263 l = mcspi_cached_chconf0(spi);
264
265 if (enable)
266 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
267 else
268 l |= OMAP2_MCSPI_CHCONF_FORCE;
269
270 mcspi_write_chconf0(spi, l);
271
272 pm_runtime_mark_last_busy(mcspi->dev);
273 pm_runtime_put_autosuspend(mcspi->dev);
274 }
275 }
276
omap2_mcspi_set_master_mode(struct spi_master * master)277 static void omap2_mcspi_set_master_mode(struct spi_master *master)
278 {
279 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
280 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
281 u32 l;
282
283 /*
284 * Setup when switching from (reset default) slave mode
285 * to single-channel master mode
286 */
287 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
288 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
289 l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
290 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
291
292 ctx->modulctrl = l;
293 }
294
omap2_mcspi_set_fifo(const struct spi_device * spi,struct spi_transfer * t,int enable)295 static void omap2_mcspi_set_fifo(const struct spi_device *spi,
296 struct spi_transfer *t, int enable)
297 {
298 struct spi_master *master = spi->master;
299 struct omap2_mcspi_cs *cs = spi->controller_state;
300 struct omap2_mcspi *mcspi;
301 unsigned int wcnt;
302 int max_fifo_depth, bytes_per_word;
303 u32 chconf, xferlevel;
304
305 mcspi = spi_master_get_devdata(master);
306
307 chconf = mcspi_cached_chconf0(spi);
308 if (enable) {
309 bytes_per_word = mcspi_bytes_per_word(cs->word_len);
310 if (t->len % bytes_per_word != 0)
311 goto disable_fifo;
312
313 if (t->rx_buf != NULL && t->tx_buf != NULL)
314 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
315 else
316 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;
317
318 wcnt = t->len / bytes_per_word;
319 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
320 goto disable_fifo;
321
322 xferlevel = wcnt << 16;
323 if (t->rx_buf != NULL) {
324 chconf |= OMAP2_MCSPI_CHCONF_FFER;
325 xferlevel |= (bytes_per_word - 1) << 8;
326 }
327
328 if (t->tx_buf != NULL) {
329 chconf |= OMAP2_MCSPI_CHCONF_FFET;
330 xferlevel |= bytes_per_word - 1;
331 }
332
333 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
334 mcspi_write_chconf0(spi, chconf);
335 mcspi->fifo_depth = max_fifo_depth;
336
337 return;
338 }
339
340 disable_fifo:
341 if (t->rx_buf != NULL)
342 chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
343
344 if (t->tx_buf != NULL)
345 chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
346
347 mcspi_write_chconf0(spi, chconf);
348 mcspi->fifo_depth = 0;
349 }
350
mcspi_wait_for_reg_bit(void __iomem * reg,unsigned long bit)351 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
352 {
353 unsigned long timeout;
354
355 timeout = jiffies + msecs_to_jiffies(1000);
356 while (!(readl_relaxed(reg) & bit)) {
357 if (time_after(jiffies, timeout)) {
358 if (!(readl_relaxed(reg) & bit))
359 return -ETIMEDOUT;
360 else
361 return 0;
362 }
363 cpu_relax();
364 }
365 return 0;
366 }
367
omap2_mcspi_rx_callback(void * data)368 static void omap2_mcspi_rx_callback(void *data)
369 {
370 struct spi_device *spi = data;
371 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
372 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
373
374 /* We must disable the DMA RX request */
375 omap2_mcspi_set_dma_req(spi, 1, 0);
376
377 complete(&mcspi_dma->dma_rx_completion);
378 }
379
omap2_mcspi_tx_callback(void * data)380 static void omap2_mcspi_tx_callback(void *data)
381 {
382 struct spi_device *spi = data;
383 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
384 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
385
386 /* We must disable the DMA TX request */
387 omap2_mcspi_set_dma_req(spi, 0, 0);
388
389 complete(&mcspi_dma->dma_tx_completion);
390 }
391
omap2_mcspi_tx_dma(struct spi_device * spi,struct spi_transfer * xfer,struct dma_slave_config cfg)392 static void omap2_mcspi_tx_dma(struct spi_device *spi,
393 struct spi_transfer *xfer,
394 struct dma_slave_config cfg)
395 {
396 struct omap2_mcspi *mcspi;
397 struct omap2_mcspi_dma *mcspi_dma;
398
399 mcspi = spi_master_get_devdata(spi->master);
400 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
401
402 if (mcspi_dma->dma_tx) {
403 struct dma_async_tx_descriptor *tx;
404
405 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
406
407 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl,
408 xfer->tx_sg.nents,
409 DMA_MEM_TO_DEV,
410 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
411 if (tx) {
412 tx->callback = omap2_mcspi_tx_callback;
413 tx->callback_param = spi;
414 dmaengine_submit(tx);
415 } else {
416 /* FIXME: fall back to PIO? */
417 }
418 }
419 dma_async_issue_pending(mcspi_dma->dma_tx);
420 omap2_mcspi_set_dma_req(spi, 0, 1);
421
422 }
423
424 static unsigned
omap2_mcspi_rx_dma(struct spi_device * spi,struct spi_transfer * xfer,struct dma_slave_config cfg,unsigned es)425 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
426 struct dma_slave_config cfg,
427 unsigned es)
428 {
429 struct omap2_mcspi *mcspi;
430 struct omap2_mcspi_dma *mcspi_dma;
431 unsigned int count, transfer_reduction = 0;
432 struct scatterlist *sg_out[2];
433 int nb_sizes = 0, out_mapped_nents[2], ret, x;
434 size_t sizes[2];
435 u32 l;
436 int elements = 0;
437 int word_len, element_count;
438 struct omap2_mcspi_cs *cs = spi->controller_state;
439 void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
440
441 mcspi = spi_master_get_devdata(spi->master);
442 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
443 count = xfer->len;
444
445 /*
446 * In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM
447 * it mentions reducing DMA transfer length by one element in master
448 * normal mode.
449 */
450 if (mcspi->fifo_depth == 0)
451 transfer_reduction = es;
452
453 word_len = cs->word_len;
454 l = mcspi_cached_chconf0(spi);
455
456 if (word_len <= 8)
457 element_count = count;
458 else if (word_len <= 16)
459 element_count = count >> 1;
460 else /* word_len <= 32 */
461 element_count = count >> 2;
462
463 if (mcspi_dma->dma_rx) {
464 struct dma_async_tx_descriptor *tx;
465
466 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
467
468 /*
469 * Reduce DMA transfer length by one more if McSPI is
470 * configured in turbo mode.
471 */
472 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
473 transfer_reduction += es;
474
475 if (transfer_reduction) {
476 /* Split sgl into two. The second sgl won't be used. */
477 sizes[0] = count - transfer_reduction;
478 sizes[1] = transfer_reduction;
479 nb_sizes = 2;
480 } else {
481 /*
482 * Don't bother splitting the sgl. This essentially
483 * clones the original sgl.
484 */
485 sizes[0] = count;
486 nb_sizes = 1;
487 }
488
489 ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents,
490 0, nb_sizes,
491 sizes,
492 sg_out, out_mapped_nents,
493 GFP_KERNEL);
494
495 if (ret < 0) {
496 dev_err(&spi->dev, "sg_split failed\n");
497 return 0;
498 }
499
500 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx,
501 sg_out[0],
502 out_mapped_nents[0],
503 DMA_DEV_TO_MEM,
504 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
505 if (tx) {
506 tx->callback = omap2_mcspi_rx_callback;
507 tx->callback_param = spi;
508 dmaengine_submit(tx);
509 } else {
510 /* FIXME: fall back to PIO? */
511 }
512 }
513
514 dma_async_issue_pending(mcspi_dma->dma_rx);
515 omap2_mcspi_set_dma_req(spi, 1, 1);
516
517 wait_for_completion(&mcspi_dma->dma_rx_completion);
518
519 for (x = 0; x < nb_sizes; x++)
520 kfree(sg_out[x]);
521
522 if (mcspi->fifo_depth > 0)
523 return count;
524
525 /*
526 * Due to the DMA transfer length reduction the missing bytes must
527 * be read manually to receive all of the expected data.
528 */
529 omap2_mcspi_set_enable(spi, 0);
530
531 elements = element_count - 1;
532
533 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
534 elements--;
535
536 if (!mcspi_wait_for_reg_bit(chstat_reg,
537 OMAP2_MCSPI_CHSTAT_RXS)) {
538 u32 w;
539
540 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
541 if (word_len <= 8)
542 ((u8 *)xfer->rx_buf)[elements++] = w;
543 else if (word_len <= 16)
544 ((u16 *)xfer->rx_buf)[elements++] = w;
545 else /* word_len <= 32 */
546 ((u32 *)xfer->rx_buf)[elements++] = w;
547 } else {
548 int bytes_per_word = mcspi_bytes_per_word(word_len);
549 dev_err(&spi->dev, "DMA RX penultimate word empty\n");
550 count -= (bytes_per_word << 1);
551 omap2_mcspi_set_enable(spi, 1);
552 return count;
553 }
554 }
555 if (!mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_RXS)) {
556 u32 w;
557
558 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
559 if (word_len <= 8)
560 ((u8 *)xfer->rx_buf)[elements] = w;
561 else if (word_len <= 16)
562 ((u16 *)xfer->rx_buf)[elements] = w;
563 else /* word_len <= 32 */
564 ((u32 *)xfer->rx_buf)[elements] = w;
565 } else {
566 dev_err(&spi->dev, "DMA RX last word empty\n");
567 count -= mcspi_bytes_per_word(word_len);
568 }
569 omap2_mcspi_set_enable(spi, 1);
570 return count;
571 }
572
573 static unsigned
omap2_mcspi_txrx_dma(struct spi_device * spi,struct spi_transfer * xfer)574 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
575 {
576 struct omap2_mcspi *mcspi;
577 struct omap2_mcspi_cs *cs = spi->controller_state;
578 struct omap2_mcspi_dma *mcspi_dma;
579 unsigned int count;
580 u8 *rx;
581 const u8 *tx;
582 struct dma_slave_config cfg;
583 enum dma_slave_buswidth width;
584 unsigned es;
585 void __iomem *chstat_reg;
586 void __iomem *irqstat_reg;
587 int wait_res;
588
589 mcspi = spi_master_get_devdata(spi->master);
590 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
591
592 if (cs->word_len <= 8) {
593 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
594 es = 1;
595 } else if (cs->word_len <= 16) {
596 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
597 es = 2;
598 } else {
599 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
600 es = 4;
601 }
602
603 count = xfer->len;
604
605 memset(&cfg, 0, sizeof(cfg));
606 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
607 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
608 cfg.src_addr_width = width;
609 cfg.dst_addr_width = width;
610 cfg.src_maxburst = 1;
611 cfg.dst_maxburst = 1;
612
613 rx = xfer->rx_buf;
614 tx = xfer->tx_buf;
615
616 if (tx != NULL)
617 omap2_mcspi_tx_dma(spi, xfer, cfg);
618
619 if (rx != NULL)
620 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
621
622 if (tx != NULL) {
623 wait_for_completion(&mcspi_dma->dma_tx_completion);
624
625 if (mcspi->fifo_depth > 0) {
626 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
627
628 if (mcspi_wait_for_reg_bit(irqstat_reg,
629 OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
630 dev_err(&spi->dev, "EOW timed out\n");
631
632 mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
633 OMAP2_MCSPI_IRQSTATUS_EOW);
634 }
635
636 /* for TX_ONLY mode, be sure all words have shifted out */
637 if (rx == NULL) {
638 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
639 if (mcspi->fifo_depth > 0) {
640 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
641 OMAP2_MCSPI_CHSTAT_TXFFE);
642 if (wait_res < 0)
643 dev_err(&spi->dev, "TXFFE timed out\n");
644 } else {
645 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
646 OMAP2_MCSPI_CHSTAT_TXS);
647 if (wait_res < 0)
648 dev_err(&spi->dev, "TXS timed out\n");
649 }
650 if (wait_res >= 0 &&
651 (mcspi_wait_for_reg_bit(chstat_reg,
652 OMAP2_MCSPI_CHSTAT_EOT) < 0))
653 dev_err(&spi->dev, "EOT timed out\n");
654 }
655 }
656 return count;
657 }
658
659 static unsigned
omap2_mcspi_txrx_pio(struct spi_device * spi,struct spi_transfer * xfer)660 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
661 {
662 struct omap2_mcspi_cs *cs = spi->controller_state;
663 unsigned int count, c;
664 u32 l;
665 void __iomem *base = cs->base;
666 void __iomem *tx_reg;
667 void __iomem *rx_reg;
668 void __iomem *chstat_reg;
669 int word_len;
670
671 count = xfer->len;
672 c = count;
673 word_len = cs->word_len;
674
675 l = mcspi_cached_chconf0(spi);
676
677 /* We store the pre-calculated register addresses on stack to speed
678 * up the transfer loop. */
679 tx_reg = base + OMAP2_MCSPI_TX0;
680 rx_reg = base + OMAP2_MCSPI_RX0;
681 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
682
683 if (c < (word_len>>3))
684 return 0;
685
686 if (word_len <= 8) {
687 u8 *rx;
688 const u8 *tx;
689
690 rx = xfer->rx_buf;
691 tx = xfer->tx_buf;
692
693 do {
694 c -= 1;
695 if (tx != NULL) {
696 if (mcspi_wait_for_reg_bit(chstat_reg,
697 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
698 dev_err(&spi->dev, "TXS timed out\n");
699 goto out;
700 }
701 dev_vdbg(&spi->dev, "write-%d %02x\n",
702 word_len, *tx);
703 writel_relaxed(*tx++, tx_reg);
704 }
705 if (rx != NULL) {
706 if (mcspi_wait_for_reg_bit(chstat_reg,
707 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
708 dev_err(&spi->dev, "RXS timed out\n");
709 goto out;
710 }
711
712 if (c == 1 && tx == NULL &&
713 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
714 omap2_mcspi_set_enable(spi, 0);
715 *rx++ = readl_relaxed(rx_reg);
716 dev_vdbg(&spi->dev, "read-%d %02x\n",
717 word_len, *(rx - 1));
718 if (mcspi_wait_for_reg_bit(chstat_reg,
719 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
720 dev_err(&spi->dev,
721 "RXS timed out\n");
722 goto out;
723 }
724 c = 0;
725 } else if (c == 0 && tx == NULL) {
726 omap2_mcspi_set_enable(spi, 0);
727 }
728
729 *rx++ = readl_relaxed(rx_reg);
730 dev_vdbg(&spi->dev, "read-%d %02x\n",
731 word_len, *(rx - 1));
732 }
733 } while (c);
734 } else if (word_len <= 16) {
735 u16 *rx;
736 const u16 *tx;
737
738 rx = xfer->rx_buf;
739 tx = xfer->tx_buf;
740 do {
741 c -= 2;
742 if (tx != NULL) {
743 if (mcspi_wait_for_reg_bit(chstat_reg,
744 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
745 dev_err(&spi->dev, "TXS timed out\n");
746 goto out;
747 }
748 dev_vdbg(&spi->dev, "write-%d %04x\n",
749 word_len, *tx);
750 writel_relaxed(*tx++, tx_reg);
751 }
752 if (rx != NULL) {
753 if (mcspi_wait_for_reg_bit(chstat_reg,
754 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
755 dev_err(&spi->dev, "RXS timed out\n");
756 goto out;
757 }
758
759 if (c == 2 && tx == NULL &&
760 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
761 omap2_mcspi_set_enable(spi, 0);
762 *rx++ = readl_relaxed(rx_reg);
763 dev_vdbg(&spi->dev, "read-%d %04x\n",
764 word_len, *(rx - 1));
765 if (mcspi_wait_for_reg_bit(chstat_reg,
766 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
767 dev_err(&spi->dev,
768 "RXS timed out\n");
769 goto out;
770 }
771 c = 0;
772 } else if (c == 0 && tx == NULL) {
773 omap2_mcspi_set_enable(spi, 0);
774 }
775
776 *rx++ = readl_relaxed(rx_reg);
777 dev_vdbg(&spi->dev, "read-%d %04x\n",
778 word_len, *(rx - 1));
779 }
780 } while (c >= 2);
781 } else if (word_len <= 32) {
782 u32 *rx;
783 const u32 *tx;
784
785 rx = xfer->rx_buf;
786 tx = xfer->tx_buf;
787 do {
788 c -= 4;
789 if (tx != NULL) {
790 if (mcspi_wait_for_reg_bit(chstat_reg,
791 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
792 dev_err(&spi->dev, "TXS timed out\n");
793 goto out;
794 }
795 dev_vdbg(&spi->dev, "write-%d %08x\n",
796 word_len, *tx);
797 writel_relaxed(*tx++, tx_reg);
798 }
799 if (rx != NULL) {
800 if (mcspi_wait_for_reg_bit(chstat_reg,
801 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
802 dev_err(&spi->dev, "RXS timed out\n");
803 goto out;
804 }
805
806 if (c == 4 && tx == NULL &&
807 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
808 omap2_mcspi_set_enable(spi, 0);
809 *rx++ = readl_relaxed(rx_reg);
810 dev_vdbg(&spi->dev, "read-%d %08x\n",
811 word_len, *(rx - 1));
812 if (mcspi_wait_for_reg_bit(chstat_reg,
813 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
814 dev_err(&spi->dev,
815 "RXS timed out\n");
816 goto out;
817 }
818 c = 0;
819 } else if (c == 0 && tx == NULL) {
820 omap2_mcspi_set_enable(spi, 0);
821 }
822
823 *rx++ = readl_relaxed(rx_reg);
824 dev_vdbg(&spi->dev, "read-%d %08x\n",
825 word_len, *(rx - 1));
826 }
827 } while (c >= 4);
828 }
829
830 /* for TX_ONLY mode, be sure all words have shifted out */
831 if (xfer->rx_buf == NULL) {
832 if (mcspi_wait_for_reg_bit(chstat_reg,
833 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
834 dev_err(&spi->dev, "TXS timed out\n");
835 } else if (mcspi_wait_for_reg_bit(chstat_reg,
836 OMAP2_MCSPI_CHSTAT_EOT) < 0)
837 dev_err(&spi->dev, "EOT timed out\n");
838
839 /* disable chan to purge rx datas received in TX_ONLY transfer,
840 * otherwise these rx datas will affect the direct following
841 * RX_ONLY transfer.
842 */
843 omap2_mcspi_set_enable(spi, 0);
844 }
845 out:
846 omap2_mcspi_set_enable(spi, 1);
847 return count - c;
848 }
849
omap2_mcspi_calc_divisor(u32 speed_hz)850 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
851 {
852 u32 div;
853
854 for (div = 0; div < 15; div++)
855 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
856 return div;
857
858 return 15;
859 }
860
861 /* called only when no transfer is active to this device */
omap2_mcspi_setup_transfer(struct spi_device * spi,struct spi_transfer * t)862 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
863 struct spi_transfer *t)
864 {
865 struct omap2_mcspi_cs *cs = spi->controller_state;
866 struct omap2_mcspi *mcspi;
867 u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
868 u8 word_len = spi->bits_per_word;
869 u32 speed_hz = spi->max_speed_hz;
870
871 mcspi = spi_master_get_devdata(spi->master);
872
873 if (t != NULL && t->bits_per_word)
874 word_len = t->bits_per_word;
875
876 cs->word_len = word_len;
877
878 if (t && t->speed_hz)
879 speed_hz = t->speed_hz;
880
881 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
882 if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
883 clkd = omap2_mcspi_calc_divisor(speed_hz);
884 speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
885 clkg = 0;
886 } else {
887 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
888 speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
889 clkd = (div - 1) & 0xf;
890 extclk = (div - 1) >> 4;
891 clkg = OMAP2_MCSPI_CHCONF_CLKG;
892 }
893
894 l = mcspi_cached_chconf0(spi);
895
896 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
897 * REVISIT: this controller could support SPI_3WIRE mode.
898 */
899 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
900 l &= ~OMAP2_MCSPI_CHCONF_IS;
901 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
902 l |= OMAP2_MCSPI_CHCONF_DPE0;
903 } else {
904 l |= OMAP2_MCSPI_CHCONF_IS;
905 l |= OMAP2_MCSPI_CHCONF_DPE1;
906 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
907 }
908
909 /* wordlength */
910 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
911 l |= (word_len - 1) << 7;
912
913 /* set chipselect polarity; manage with FORCE */
914 if (!(spi->mode & SPI_CS_HIGH))
915 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
916 else
917 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
918
919 /* set clock divisor */
920 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
921 l |= clkd << 2;
922
923 /* set clock granularity */
924 l &= ~OMAP2_MCSPI_CHCONF_CLKG;
925 l |= clkg;
926 if (clkg) {
927 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
928 cs->chctrl0 |= extclk << 8;
929 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
930 }
931
932 /* set SPI mode 0..3 */
933 if (spi->mode & SPI_CPOL)
934 l |= OMAP2_MCSPI_CHCONF_POL;
935 else
936 l &= ~OMAP2_MCSPI_CHCONF_POL;
937 if (spi->mode & SPI_CPHA)
938 l |= OMAP2_MCSPI_CHCONF_PHA;
939 else
940 l &= ~OMAP2_MCSPI_CHCONF_PHA;
941
942 mcspi_write_chconf0(spi, l);
943
944 cs->mode = spi->mode;
945
946 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
947 speed_hz,
948 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
949 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
950
951 return 0;
952 }
953
954 /*
955 * Note that we currently allow DMA only if we get a channel
956 * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
957 */
omap2_mcspi_request_dma(struct spi_device * spi)958 static int omap2_mcspi_request_dma(struct spi_device *spi)
959 {
960 struct spi_master *master = spi->master;
961 struct omap2_mcspi *mcspi;
962 struct omap2_mcspi_dma *mcspi_dma;
963 int ret = 0;
964
965 mcspi = spi_master_get_devdata(master);
966 mcspi_dma = mcspi->dma_channels + spi->chip_select;
967
968 init_completion(&mcspi_dma->dma_rx_completion);
969 init_completion(&mcspi_dma->dma_tx_completion);
970
971 mcspi_dma->dma_rx = dma_request_chan(&master->dev,
972 mcspi_dma->dma_rx_ch_name);
973 if (IS_ERR(mcspi_dma->dma_rx)) {
974 ret = PTR_ERR(mcspi_dma->dma_rx);
975 mcspi_dma->dma_rx = NULL;
976 goto no_dma;
977 }
978
979 mcspi_dma->dma_tx = dma_request_chan(&master->dev,
980 mcspi_dma->dma_tx_ch_name);
981 if (IS_ERR(mcspi_dma->dma_tx)) {
982 ret = PTR_ERR(mcspi_dma->dma_tx);
983 mcspi_dma->dma_tx = NULL;
984 dma_release_channel(mcspi_dma->dma_rx);
985 mcspi_dma->dma_rx = NULL;
986 }
987
988 no_dma:
989 return ret;
990 }
991
omap2_mcspi_setup(struct spi_device * spi)992 static int omap2_mcspi_setup(struct spi_device *spi)
993 {
994 int ret;
995 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
996 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
997 struct omap2_mcspi_dma *mcspi_dma;
998 struct omap2_mcspi_cs *cs = spi->controller_state;
999
1000 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1001
1002 if (!cs) {
1003 cs = kzalloc(sizeof *cs, GFP_KERNEL);
1004 if (!cs)
1005 return -ENOMEM;
1006 cs->base = mcspi->base + spi->chip_select * 0x14;
1007 cs->phys = mcspi->phys + spi->chip_select * 0x14;
1008 cs->mode = 0;
1009 cs->chconf0 = 0;
1010 cs->chctrl0 = 0;
1011 spi->controller_state = cs;
1012 /* Link this to context save list */
1013 list_add_tail(&cs->node, &ctx->cs);
1014
1015 if (gpio_is_valid(spi->cs_gpio)) {
1016 ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
1017 if (ret) {
1018 dev_err(&spi->dev, "failed to request gpio\n");
1019 return ret;
1020 }
1021 gpio_direction_output(spi->cs_gpio,
1022 !(spi->mode & SPI_CS_HIGH));
1023 }
1024 }
1025
1026 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
1027 ret = omap2_mcspi_request_dma(spi);
1028 if (ret)
1029 dev_warn(&spi->dev, "not using DMA for McSPI (%d)\n",
1030 ret);
1031 }
1032
1033 ret = pm_runtime_get_sync(mcspi->dev);
1034 if (ret < 0) {
1035 pm_runtime_put_noidle(mcspi->dev);
1036
1037 return ret;
1038 }
1039
1040 ret = omap2_mcspi_setup_transfer(spi, NULL);
1041 pm_runtime_mark_last_busy(mcspi->dev);
1042 pm_runtime_put_autosuspend(mcspi->dev);
1043
1044 return ret;
1045 }
1046
omap2_mcspi_cleanup(struct spi_device * spi)1047 static void omap2_mcspi_cleanup(struct spi_device *spi)
1048 {
1049 struct omap2_mcspi *mcspi;
1050 struct omap2_mcspi_dma *mcspi_dma;
1051 struct omap2_mcspi_cs *cs;
1052
1053 mcspi = spi_master_get_devdata(spi->master);
1054
1055 if (spi->controller_state) {
1056 /* Unlink controller state from context save list */
1057 cs = spi->controller_state;
1058 list_del(&cs->node);
1059
1060 kfree(cs);
1061 }
1062
1063 if (spi->chip_select < spi->master->num_chipselect) {
1064 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1065
1066 if (mcspi_dma->dma_rx) {
1067 dma_release_channel(mcspi_dma->dma_rx);
1068 mcspi_dma->dma_rx = NULL;
1069 }
1070 if (mcspi_dma->dma_tx) {
1071 dma_release_channel(mcspi_dma->dma_tx);
1072 mcspi_dma->dma_tx = NULL;
1073 }
1074 }
1075
1076 if (gpio_is_valid(spi->cs_gpio))
1077 gpio_free(spi->cs_gpio);
1078 }
1079
omap2_mcspi_transfer_one(struct spi_master * master,struct spi_device * spi,struct spi_transfer * t)1080 static int omap2_mcspi_transfer_one(struct spi_master *master,
1081 struct spi_device *spi,
1082 struct spi_transfer *t)
1083 {
1084
1085 /* We only enable one channel at a time -- the one whose message is
1086 * -- although this controller would gladly
1087 * arbitrate among multiple channels. This corresponds to "single
1088 * channel" master mode. As a side effect, we need to manage the
1089 * chipselect with the FORCE bit ... CS != channel enable.
1090 */
1091
1092 struct omap2_mcspi *mcspi;
1093 struct omap2_mcspi_dma *mcspi_dma;
1094 struct omap2_mcspi_cs *cs;
1095 struct omap2_mcspi_device_config *cd;
1096 int par_override = 0;
1097 int status = 0;
1098 u32 chconf;
1099
1100 mcspi = spi_master_get_devdata(master);
1101 mcspi_dma = mcspi->dma_channels + spi->chip_select;
1102 cs = spi->controller_state;
1103 cd = spi->controller_data;
1104
1105 /*
1106 * The slave driver could have changed spi->mode in which case
1107 * it will be different from cs->mode (the current hardware setup).
1108 * If so, set par_override (even though its not a parity issue) so
1109 * omap2_mcspi_setup_transfer will be called to configure the hardware
1110 * with the correct mode on the first iteration of the loop below.
1111 */
1112 if (spi->mode != cs->mode)
1113 par_override = 1;
1114
1115 omap2_mcspi_set_enable(spi, 0);
1116
1117 if (gpio_is_valid(spi->cs_gpio))
1118 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
1119
1120 if (par_override ||
1121 (t->speed_hz != spi->max_speed_hz) ||
1122 (t->bits_per_word != spi->bits_per_word)) {
1123 par_override = 1;
1124 status = omap2_mcspi_setup_transfer(spi, t);
1125 if (status < 0)
1126 goto out;
1127 if (t->speed_hz == spi->max_speed_hz &&
1128 t->bits_per_word == spi->bits_per_word)
1129 par_override = 0;
1130 }
1131 if (cd && cd->cs_per_word) {
1132 chconf = mcspi->ctx.modulctrl;
1133 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
1134 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1135 mcspi->ctx.modulctrl =
1136 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1137 }
1138
1139 chconf = mcspi_cached_chconf0(spi);
1140 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1141 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1142
1143 if (t->tx_buf == NULL)
1144 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1145 else if (t->rx_buf == NULL)
1146 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1147
1148 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1149 /* Turbo mode is for more than one word */
1150 if (t->len > ((cs->word_len + 7) >> 3))
1151 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1152 }
1153
1154 mcspi_write_chconf0(spi, chconf);
1155
1156 if (t->len) {
1157 unsigned count;
1158
1159 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1160 master->cur_msg_mapped &&
1161 master->can_dma(master, spi, t))
1162 omap2_mcspi_set_fifo(spi, t, 1);
1163
1164 omap2_mcspi_set_enable(spi, 1);
1165
1166 /* RX_ONLY mode needs dummy data in TX reg */
1167 if (t->tx_buf == NULL)
1168 writel_relaxed(0, cs->base
1169 + OMAP2_MCSPI_TX0);
1170
1171 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1172 master->cur_msg_mapped &&
1173 master->can_dma(master, spi, t))
1174 count = omap2_mcspi_txrx_dma(spi, t);
1175 else
1176 count = omap2_mcspi_txrx_pio(spi, t);
1177
1178 if (count != t->len) {
1179 status = -EIO;
1180 goto out;
1181 }
1182 }
1183
1184 omap2_mcspi_set_enable(spi, 0);
1185
1186 if (mcspi->fifo_depth > 0)
1187 omap2_mcspi_set_fifo(spi, t, 0);
1188
1189 out:
1190 /* Restore defaults if they were overriden */
1191 if (par_override) {
1192 par_override = 0;
1193 status = omap2_mcspi_setup_transfer(spi, NULL);
1194 }
1195
1196 if (cd && cd->cs_per_word) {
1197 chconf = mcspi->ctx.modulctrl;
1198 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1199 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1200 mcspi->ctx.modulctrl =
1201 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1202 }
1203
1204 omap2_mcspi_set_enable(spi, 0);
1205
1206 if (gpio_is_valid(spi->cs_gpio))
1207 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
1208
1209 if (mcspi->fifo_depth > 0 && t)
1210 omap2_mcspi_set_fifo(spi, t, 0);
1211
1212 return status;
1213 }
1214
omap2_mcspi_prepare_message(struct spi_master * master,struct spi_message * msg)1215 static int omap2_mcspi_prepare_message(struct spi_master *master,
1216 struct spi_message *msg)
1217 {
1218 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1219 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1220 struct omap2_mcspi_cs *cs;
1221
1222 /* Only a single channel can have the FORCE bit enabled
1223 * in its chconf0 register.
1224 * Scan all channels and disable them except the current one.
1225 * A FORCE can remain from a last transfer having cs_change enabled
1226 */
1227 list_for_each_entry(cs, &ctx->cs, node) {
1228 if (msg->spi->controller_state == cs)
1229 continue;
1230
1231 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) {
1232 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1233 writel_relaxed(cs->chconf0,
1234 cs->base + OMAP2_MCSPI_CHCONF0);
1235 readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0);
1236 }
1237 }
1238
1239 return 0;
1240 }
1241
omap2_mcspi_can_dma(struct spi_master * master,struct spi_device * spi,struct spi_transfer * xfer)1242 static bool omap2_mcspi_can_dma(struct spi_master *master,
1243 struct spi_device *spi,
1244 struct spi_transfer *xfer)
1245 {
1246 return (xfer->len >= DMA_MIN_BYTES);
1247 }
1248
omap2_mcspi_master_setup(struct omap2_mcspi * mcspi)1249 static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1250 {
1251 struct spi_master *master = mcspi->master;
1252 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1253 int ret = 0;
1254
1255 ret = pm_runtime_get_sync(mcspi->dev);
1256 if (ret < 0) {
1257 pm_runtime_put_noidle(mcspi->dev);
1258
1259 return ret;
1260 }
1261
1262 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1263 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1264 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1265
1266 omap2_mcspi_set_master_mode(master);
1267 pm_runtime_mark_last_busy(mcspi->dev);
1268 pm_runtime_put_autosuspend(mcspi->dev);
1269 return 0;
1270 }
1271
1272 /*
1273 * When SPI wake up from off-mode, CS is in activate state. If it was in
1274 * inactive state when driver was suspend, then force it to inactive state at
1275 * wake up.
1276 */
omap_mcspi_runtime_resume(struct device * dev)1277 static int omap_mcspi_runtime_resume(struct device *dev)
1278 {
1279 struct spi_master *master = dev_get_drvdata(dev);
1280 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1281 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1282 struct omap2_mcspi_cs *cs;
1283
1284 /* McSPI: context restore */
1285 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
1286 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
1287
1288 list_for_each_entry(cs, &ctx->cs, node) {
1289 /*
1290 * We need to toggle CS state for OMAP take this
1291 * change in account.
1292 */
1293 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1294 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1295 writel_relaxed(cs->chconf0,
1296 cs->base + OMAP2_MCSPI_CHCONF0);
1297 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1298 writel_relaxed(cs->chconf0,
1299 cs->base + OMAP2_MCSPI_CHCONF0);
1300 } else {
1301 writel_relaxed(cs->chconf0,
1302 cs->base + OMAP2_MCSPI_CHCONF0);
1303 }
1304 }
1305
1306 return 0;
1307 }
1308
1309 static struct omap2_mcspi_platform_config omap2_pdata = {
1310 .regs_offset = 0,
1311 };
1312
1313 static struct omap2_mcspi_platform_config omap4_pdata = {
1314 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1315 };
1316
1317 static const struct of_device_id omap_mcspi_of_match[] = {
1318 {
1319 .compatible = "ti,omap2-mcspi",
1320 .data = &omap2_pdata,
1321 },
1322 {
1323 .compatible = "ti,omap4-mcspi",
1324 .data = &omap4_pdata,
1325 },
1326 { },
1327 };
1328 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1329
omap2_mcspi_probe(struct platform_device * pdev)1330 static int omap2_mcspi_probe(struct platform_device *pdev)
1331 {
1332 struct spi_master *master;
1333 const struct omap2_mcspi_platform_config *pdata;
1334 struct omap2_mcspi *mcspi;
1335 struct resource *r;
1336 int status = 0, i;
1337 u32 regs_offset = 0;
1338 struct device_node *node = pdev->dev.of_node;
1339 const struct of_device_id *match;
1340
1341 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1342 if (master == NULL) {
1343 dev_dbg(&pdev->dev, "master allocation failed\n");
1344 return -ENOMEM;
1345 }
1346
1347 /* the spi->mode bits understood by this driver: */
1348 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1349 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1350 master->setup = omap2_mcspi_setup;
1351 master->auto_runtime_pm = true;
1352 master->prepare_message = omap2_mcspi_prepare_message;
1353 master->can_dma = omap2_mcspi_can_dma;
1354 master->transfer_one = omap2_mcspi_transfer_one;
1355 master->set_cs = omap2_mcspi_set_cs;
1356 master->cleanup = omap2_mcspi_cleanup;
1357 master->dev.of_node = node;
1358 master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
1359 master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
1360
1361 platform_set_drvdata(pdev, master);
1362
1363 mcspi = spi_master_get_devdata(master);
1364 mcspi->master = master;
1365
1366 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1367 if (match) {
1368 u32 num_cs = 1; /* default number of chipselect */
1369 pdata = match->data;
1370
1371 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1372 master->num_chipselect = num_cs;
1373 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1374 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1375 } else {
1376 pdata = dev_get_platdata(&pdev->dev);
1377 master->num_chipselect = pdata->num_cs;
1378 mcspi->pin_dir = pdata->pin_dir;
1379 }
1380 regs_offset = pdata->regs_offset;
1381
1382 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1383 mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1384 if (IS_ERR(mcspi->base)) {
1385 status = PTR_ERR(mcspi->base);
1386 goto free_master;
1387 }
1388 mcspi->phys = r->start + regs_offset;
1389 mcspi->base += regs_offset;
1390
1391 mcspi->dev = &pdev->dev;
1392
1393 INIT_LIST_HEAD(&mcspi->ctx.cs);
1394
1395 mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect,
1396 sizeof(struct omap2_mcspi_dma),
1397 GFP_KERNEL);
1398 if (mcspi->dma_channels == NULL) {
1399 status = -ENOMEM;
1400 goto free_master;
1401 }
1402
1403 for (i = 0; i < master->num_chipselect; i++) {
1404 sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i);
1405 sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i);
1406 }
1407
1408 pm_runtime_use_autosuspend(&pdev->dev);
1409 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1410 pm_runtime_enable(&pdev->dev);
1411
1412 status = omap2_mcspi_master_setup(mcspi);
1413 if (status < 0)
1414 goto disable_pm;
1415
1416 status = devm_spi_register_master(&pdev->dev, master);
1417 if (status < 0)
1418 goto disable_pm;
1419
1420 return status;
1421
1422 disable_pm:
1423 pm_runtime_dont_use_autosuspend(&pdev->dev);
1424 pm_runtime_put_sync(&pdev->dev);
1425 pm_runtime_disable(&pdev->dev);
1426 free_master:
1427 spi_master_put(master);
1428 return status;
1429 }
1430
omap2_mcspi_remove(struct platform_device * pdev)1431 static int omap2_mcspi_remove(struct platform_device *pdev)
1432 {
1433 struct spi_master *master = platform_get_drvdata(pdev);
1434 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1435
1436 pm_runtime_dont_use_autosuspend(mcspi->dev);
1437 pm_runtime_put_sync(mcspi->dev);
1438 pm_runtime_disable(&pdev->dev);
1439
1440 return 0;
1441 }
1442
1443 /* work with hotplug and coldplug */
1444 MODULE_ALIAS("platform:omap2_mcspi");
1445
omap2_mcspi_suspend(struct device * dev)1446 static int __maybe_unused omap2_mcspi_suspend(struct device *dev)
1447 {
1448 struct spi_master *master = dev_get_drvdata(dev);
1449 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1450 int error;
1451
1452 error = pinctrl_pm_select_sleep_state(dev);
1453 if (error)
1454 dev_warn(mcspi->dev, "%s: failed to set pins: %i\n",
1455 __func__, error);
1456
1457 error = spi_master_suspend(master);
1458 if (error)
1459 dev_warn(mcspi->dev, "%s: master suspend failed: %i\n",
1460 __func__, error);
1461
1462 return pm_runtime_force_suspend(dev);
1463 }
1464
omap2_mcspi_resume(struct device * dev)1465 static int __maybe_unused omap2_mcspi_resume(struct device *dev)
1466 {
1467 struct spi_master *master = dev_get_drvdata(dev);
1468 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1469 int error;
1470
1471 error = pinctrl_pm_select_default_state(dev);
1472 if (error)
1473 dev_warn(mcspi->dev, "%s: failed to set pins: %i\n",
1474 __func__, error);
1475
1476 error = spi_master_resume(master);
1477 if (error)
1478 dev_warn(mcspi->dev, "%s: master resume failed: %i\n",
1479 __func__, error);
1480
1481 return pm_runtime_force_resume(dev);
1482 }
1483
1484 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1485 SET_SYSTEM_SLEEP_PM_OPS(omap2_mcspi_suspend,
1486 omap2_mcspi_resume)
1487 .runtime_resume = omap_mcspi_runtime_resume,
1488 };
1489
1490 static struct platform_driver omap2_mcspi_driver = {
1491 .driver = {
1492 .name = "omap2_mcspi",
1493 .pm = &omap2_mcspi_pm_ops,
1494 .of_match_table = omap_mcspi_of_match,
1495 },
1496 .probe = omap2_mcspi_probe,
1497 .remove = omap2_mcspi_remove,
1498 };
1499
1500 module_platform_driver(omap2_mcspi_driver);
1501 MODULE_LICENSE("GPL");
1502