Lines Matching +full:sun6i +full:- +full:a31 +full:- +full:spi
2 * Copyright (C) 2012 - 2014 Allwinner Tech
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
25 #include <linux/spi/spi.h>
108 return readl(sspi->base_addr + reg); in sun6i_spi_read()
113 writel(value, sspi->base_addr + reg); in sun6i_spi_write()
154 while (len--) { in sun6i_spi_drain_fifo()
155 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG); in sun6i_spi_drain_fifo()
156 if (sspi->rx_buf) in sun6i_spi_drain_fifo()
157 *sspi->rx_buf++ = byte; in sun6i_spi_drain_fifo()
167 cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi); in sun6i_spi_fill_fifo()
169 len = min3(len, (int)cnt, sspi->len); in sun6i_spi_fill_fifo()
171 while (len--) { in sun6i_spi_fill_fifo()
172 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; in sun6i_spi_fill_fifo()
173 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG); in sun6i_spi_fill_fifo()
174 sspi->len--; in sun6i_spi_fill_fifo()
178 static void sun6i_spi_set_cs(struct spi_device *spi, bool enable) in sun6i_spi_set_cs() argument
180 struct sun6i_spi *sspi = spi_master_get_devdata(spi->master); in sun6i_spi_set_cs()
185 reg |= SUN6I_TFR_CTL_CS(spi->chip_select); in sun6i_spi_set_cs()
195 static size_t sun6i_spi_max_transfer_size(struct spi_device *spi) in sun6i_spi_max_transfer_size() argument
197 return SUN6I_MAX_XFER_SIZE - 1; in sun6i_spi_max_transfer_size()
201 struct spi_device *spi, in sun6i_spi_transfer_one() argument
212 if (tfr->len > SUN6I_MAX_XFER_SIZE) in sun6i_spi_transfer_one()
213 return -EINVAL; in sun6i_spi_transfer_one()
215 reinit_completion(&sspi->done); in sun6i_spi_transfer_one()
216 sspi->tx_buf = tfr->tx_buf; in sun6i_spi_transfer_one()
217 sspi->rx_buf = tfr->rx_buf; in sun6i_spi_transfer_one()
218 sspi->len = tfr->len; in sun6i_spi_transfer_one()
230 * value used in old generation of Allwinner SPI controller. in sun6i_spi_transfer_one()
231 * (See spi-sun4i.c) in sun6i_spi_transfer_one()
233 trig_level = sspi->fifo_depth / 4 * 3; in sun6i_spi_transfer_one()
244 if (spi->mode & SPI_CPOL) in sun6i_spi_transfer_one()
249 if (spi->mode & SPI_CPHA) in sun6i_spi_transfer_one()
254 if (spi->mode & SPI_LSB_FIRST) in sun6i_spi_transfer_one()
263 if (sspi->rx_buf) in sun6i_spi_transfer_one()
274 mclk_rate = clk_get_rate(sspi->mclk); in sun6i_spi_transfer_one()
275 if (mclk_rate < (2 * tfr->speed_hz)) { in sun6i_spi_transfer_one()
276 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); in sun6i_spi_transfer_one()
277 mclk_rate = clk_get_rate(sspi->mclk); in sun6i_spi_transfer_one()
294 div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz); in sun6i_spi_transfer_one()
297 reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS; in sun6i_spi_transfer_one()
306 if (sspi->tx_buf) in sun6i_spi_transfer_one()
307 tx_len = tfr->len; in sun6i_spi_transfer_one()
310 sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len)); in sun6i_spi_transfer_one()
316 sun6i_spi_fill_fifo(sspi, sspi->fifo_depth); in sun6i_spi_transfer_one()
322 if (tx_len > sspi->fifo_depth) in sun6i_spi_transfer_one()
329 tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U); in sun6i_spi_transfer_one()
331 timeout = wait_for_completion_timeout(&sspi->done, in sun6i_spi_transfer_one()
335 dev_warn(&master->dev, in sun6i_spi_transfer_one()
337 dev_name(&spi->dev), tfr->len, tfr->speed_hz, in sun6i_spi_transfer_one()
338 jiffies_to_msecs(end - start), tx_time); in sun6i_spi_transfer_one()
339 ret = -ETIMEDOUT; in sun6i_spi_transfer_one()
357 sun6i_spi_drain_fifo(sspi, sspi->fifo_depth); in sun6i_spi_handler()
358 complete(&sspi->done); in sun6i_spi_handler()
374 if (!sspi->len) in sun6i_spi_handler()
378 /* Only clear the interrupt _after_ re-seeding the FIFO */ in sun6i_spi_handler()
393 ret = clk_prepare_enable(sspi->hclk); in sun6i_spi_runtime_resume()
399 ret = clk_prepare_enable(sspi->mclk); in sun6i_spi_runtime_resume()
405 ret = reset_control_deassert(sspi->rstc); in sun6i_spi_runtime_resume()
417 clk_disable_unprepare(sspi->mclk); in sun6i_spi_runtime_resume()
419 clk_disable_unprepare(sspi->hclk); in sun6i_spi_runtime_resume()
429 reset_control_assert(sspi->rstc); in sun6i_spi_runtime_suspend()
430 clk_disable_unprepare(sspi->mclk); in sun6i_spi_runtime_suspend()
431 clk_disable_unprepare(sspi->hclk); in sun6i_spi_runtime_suspend()
443 master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi)); in sun6i_spi_probe()
445 dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); in sun6i_spi_probe()
446 return -ENOMEM; in sun6i_spi_probe()
453 sspi->base_addr = devm_ioremap_resource(&pdev->dev, res); in sun6i_spi_probe()
454 if (IS_ERR(sspi->base_addr)) { in sun6i_spi_probe()
455 ret = PTR_ERR(sspi->base_addr); in sun6i_spi_probe()
461 dev_err(&pdev->dev, "No spi IRQ specified\n"); in sun6i_spi_probe()
462 ret = -ENXIO; in sun6i_spi_probe()
466 ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler, in sun6i_spi_probe()
467 0, "sun6i-spi", sspi); in sun6i_spi_probe()
469 dev_err(&pdev->dev, "Cannot request IRQ\n"); in sun6i_spi_probe()
473 sspi->master = master; in sun6i_spi_probe()
474 sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev); in sun6i_spi_probe()
476 master->max_speed_hz = 100 * 1000 * 1000; in sun6i_spi_probe()
477 master->min_speed_hz = 3 * 1000; in sun6i_spi_probe()
478 master->set_cs = sun6i_spi_set_cs; in sun6i_spi_probe()
479 master->transfer_one = sun6i_spi_transfer_one; in sun6i_spi_probe()
480 master->num_chipselect = 4; in sun6i_spi_probe()
481 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; in sun6i_spi_probe()
482 master->bits_per_word_mask = SPI_BPW_MASK(8); in sun6i_spi_probe()
483 master->dev.of_node = pdev->dev.of_node; in sun6i_spi_probe()
484 master->auto_runtime_pm = true; in sun6i_spi_probe()
485 master->max_transfer_size = sun6i_spi_max_transfer_size; in sun6i_spi_probe()
487 sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); in sun6i_spi_probe()
488 if (IS_ERR(sspi->hclk)) { in sun6i_spi_probe()
489 dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); in sun6i_spi_probe()
490 ret = PTR_ERR(sspi->hclk); in sun6i_spi_probe()
494 sspi->mclk = devm_clk_get(&pdev->dev, "mod"); in sun6i_spi_probe()
495 if (IS_ERR(sspi->mclk)) { in sun6i_spi_probe()
496 dev_err(&pdev->dev, "Unable to acquire module clock\n"); in sun6i_spi_probe()
497 ret = PTR_ERR(sspi->mclk); in sun6i_spi_probe()
501 init_completion(&sspi->done); in sun6i_spi_probe()
503 sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); in sun6i_spi_probe()
504 if (IS_ERR(sspi->rstc)) { in sun6i_spi_probe()
505 dev_err(&pdev->dev, "Couldn't get reset controller\n"); in sun6i_spi_probe()
506 ret = PTR_ERR(sspi->rstc); in sun6i_spi_probe()
511 * This wake-up/shutdown pattern is to be able to have the in sun6i_spi_probe()
514 ret = sun6i_spi_runtime_resume(&pdev->dev); in sun6i_spi_probe()
516 dev_err(&pdev->dev, "Couldn't resume the device\n"); in sun6i_spi_probe()
520 pm_runtime_set_active(&pdev->dev); in sun6i_spi_probe()
521 pm_runtime_enable(&pdev->dev); in sun6i_spi_probe()
522 pm_runtime_idle(&pdev->dev); in sun6i_spi_probe()
524 ret = devm_spi_register_master(&pdev->dev, master); in sun6i_spi_probe()
526 dev_err(&pdev->dev, "cannot register SPI master\n"); in sun6i_spi_probe()
533 pm_runtime_disable(&pdev->dev); in sun6i_spi_probe()
534 sun6i_spi_runtime_suspend(&pdev->dev); in sun6i_spi_probe()
542 pm_runtime_force_suspend(&pdev->dev); in sun6i_spi_remove()
548 { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },
549 { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH },
563 .name = "sun6i-spi",
571 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
572 MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");