1 /*
2 * Copyright (C) 2012 - 2014 Allwinner Tech
3 * Pan Nan <pannan@allwinnertech.com>
4 *
5 * Copyright (C) 2014 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 */
13
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/device.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/reset.h>
24
25 #include <linux/spi/spi.h>
26
27 #define SUN6I_FIFO_DEPTH 128
28 #define SUN8I_FIFO_DEPTH 64
29
30 #define SUN6I_GBL_CTL_REG 0x04
31 #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
32 #define SUN6I_GBL_CTL_MASTER BIT(1)
33 #define SUN6I_GBL_CTL_TP BIT(7)
34 #define SUN6I_GBL_CTL_RST BIT(31)
35
36 #define SUN6I_TFR_CTL_REG 0x08
37 #define SUN6I_TFR_CTL_CPHA BIT(0)
38 #define SUN6I_TFR_CTL_CPOL BIT(1)
39 #define SUN6I_TFR_CTL_SPOL BIT(2)
40 #define SUN6I_TFR_CTL_CS_MASK 0x30
41 #define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK)
42 #define SUN6I_TFR_CTL_CS_MANUAL BIT(6)
43 #define SUN6I_TFR_CTL_CS_LEVEL BIT(7)
44 #define SUN6I_TFR_CTL_DHB BIT(8)
45 #define SUN6I_TFR_CTL_FBS BIT(12)
46 #define SUN6I_TFR_CTL_XCH BIT(31)
47
48 #define SUN6I_INT_CTL_REG 0x10
49 #define SUN6I_INT_CTL_RF_RDY BIT(0)
50 #define SUN6I_INT_CTL_TF_ERQ BIT(4)
51 #define SUN6I_INT_CTL_RF_OVF BIT(8)
52 #define SUN6I_INT_CTL_TC BIT(12)
53
54 #define SUN6I_INT_STA_REG 0x14
55
56 #define SUN6I_FIFO_CTL_REG 0x18
57 #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff
58 #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0
59 #define SUN6I_FIFO_CTL_RF_RST BIT(15)
60 #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff
61 #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16
62 #define SUN6I_FIFO_CTL_TF_RST BIT(31)
63
64 #define SUN6I_FIFO_STA_REG 0x1c
65 #define SUN6I_FIFO_STA_RF_CNT_MASK 0x7f
66 #define SUN6I_FIFO_STA_RF_CNT_BITS 0
67 #define SUN6I_FIFO_STA_TF_CNT_MASK 0x7f
68 #define SUN6I_FIFO_STA_TF_CNT_BITS 16
69
70 #define SUN6I_CLK_CTL_REG 0x24
71 #define SUN6I_CLK_CTL_CDR2_MASK 0xff
72 #define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
73 #define SUN6I_CLK_CTL_CDR1_MASK 0xf
74 #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
75 #define SUN6I_CLK_CTL_DRS BIT(12)
76
77 #define SUN6I_MAX_XFER_SIZE 0xffffff
78
79 #define SUN6I_BURST_CNT_REG 0x30
80 #define SUN6I_BURST_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE)
81
82 #define SUN6I_XMIT_CNT_REG 0x34
83 #define SUN6I_XMIT_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE)
84
85 #define SUN6I_BURST_CTL_CNT_REG 0x38
86 #define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE)
87
88 #define SUN6I_TXDATA_REG 0x200
89 #define SUN6I_RXDATA_REG 0x300
90
91 struct sun6i_spi {
92 struct spi_master *master;
93 void __iomem *base_addr;
94 struct clk *hclk;
95 struct clk *mclk;
96 struct reset_control *rstc;
97
98 struct completion done;
99
100 const u8 *tx_buf;
101 u8 *rx_buf;
102 int len;
103 unsigned long fifo_depth;
104 };
105
sun6i_spi_read(struct sun6i_spi * sspi,u32 reg)106 static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
107 {
108 return readl(sspi->base_addr + reg);
109 }
110
sun6i_spi_write(struct sun6i_spi * sspi,u32 reg,u32 value)111 static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
112 {
113 writel(value, sspi->base_addr + reg);
114 }
115
sun6i_spi_get_tx_fifo_count(struct sun6i_spi * sspi)116 static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
117 {
118 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
119
120 reg >>= SUN6I_FIFO_STA_TF_CNT_BITS;
121
122 return reg & SUN6I_FIFO_STA_TF_CNT_MASK;
123 }
124
sun6i_spi_enable_interrupt(struct sun6i_spi * sspi,u32 mask)125 static inline void sun6i_spi_enable_interrupt(struct sun6i_spi *sspi, u32 mask)
126 {
127 u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
128
129 reg |= mask;
130 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
131 }
132
sun6i_spi_disable_interrupt(struct sun6i_spi * sspi,u32 mask)133 static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
134 {
135 u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
136
137 reg &= ~mask;
138 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
139 }
140
sun6i_spi_drain_fifo(struct sun6i_spi * sspi,int len)141 static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
142 {
143 u32 reg, cnt;
144 u8 byte;
145
146 /* See how much data is available */
147 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
148 reg &= SUN6I_FIFO_STA_RF_CNT_MASK;
149 cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS;
150
151 if (len > cnt)
152 len = cnt;
153
154 while (len--) {
155 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
156 if (sspi->rx_buf)
157 *sspi->rx_buf++ = byte;
158 }
159 }
160
sun6i_spi_fill_fifo(struct sun6i_spi * sspi,int len)161 static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
162 {
163 u32 cnt;
164 u8 byte;
165
166 /* See how much data we can fit */
167 cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
168
169 len = min3(len, (int)cnt, sspi->len);
170
171 while (len--) {
172 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
173 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
174 sspi->len--;
175 }
176 }
177
sun6i_spi_set_cs(struct spi_device * spi,bool enable)178 static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
179 {
180 struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
181 u32 reg;
182
183 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
184 reg &= ~SUN6I_TFR_CTL_CS_MASK;
185 reg |= SUN6I_TFR_CTL_CS(spi->chip_select);
186
187 if (enable)
188 reg |= SUN6I_TFR_CTL_CS_LEVEL;
189 else
190 reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
191
192 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
193 }
194
sun6i_spi_max_transfer_size(struct spi_device * spi)195 static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
196 {
197 return SUN6I_MAX_XFER_SIZE - 1;
198 }
199
sun6i_spi_transfer_one(struct spi_master * master,struct spi_device * spi,struct spi_transfer * tfr)200 static int sun6i_spi_transfer_one(struct spi_master *master,
201 struct spi_device *spi,
202 struct spi_transfer *tfr)
203 {
204 struct sun6i_spi *sspi = spi_master_get_devdata(master);
205 unsigned int mclk_rate, div, div_cdr1, div_cdr2, timeout;
206 unsigned int start, end, tx_time;
207 unsigned int trig_level;
208 unsigned int tx_len = 0;
209 int ret = 0;
210 u32 reg;
211
212 if (tfr->len > SUN6I_MAX_XFER_SIZE)
213 return -EINVAL;
214
215 reinit_completion(&sspi->done);
216 sspi->tx_buf = tfr->tx_buf;
217 sspi->rx_buf = tfr->rx_buf;
218 sspi->len = tfr->len;
219
220 /* Clear pending interrupts */
221 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
222
223 /* Reset FIFO */
224 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
225 SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
226
227 /*
228 * Setup FIFO interrupt trigger level
229 * Here we choose 3/4 of the full fifo depth, as it's the hardcoded
230 * value used in old generation of Allwinner SPI controller.
231 * (See spi-sun4i.c)
232 */
233 trig_level = sspi->fifo_depth / 4 * 3;
234 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
235 (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) |
236 (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS));
237
238 /*
239 * Setup the transfer control register: Chip Select,
240 * polarities, etc.
241 */
242 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
243
244 if (spi->mode & SPI_CPOL)
245 reg |= SUN6I_TFR_CTL_CPOL;
246 else
247 reg &= ~SUN6I_TFR_CTL_CPOL;
248
249 if (spi->mode & SPI_CPHA)
250 reg |= SUN6I_TFR_CTL_CPHA;
251 else
252 reg &= ~SUN6I_TFR_CTL_CPHA;
253
254 if (spi->mode & SPI_LSB_FIRST)
255 reg |= SUN6I_TFR_CTL_FBS;
256 else
257 reg &= ~SUN6I_TFR_CTL_FBS;
258
259 /*
260 * If it's a TX only transfer, we don't want to fill the RX
261 * FIFO with bogus data
262 */
263 if (sspi->rx_buf)
264 reg &= ~SUN6I_TFR_CTL_DHB;
265 else
266 reg |= SUN6I_TFR_CTL_DHB;
267
268 /* We want to control the chip select manually */
269 reg |= SUN6I_TFR_CTL_CS_MANUAL;
270
271 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
272
273 /* Ensure that we have a parent clock fast enough */
274 mclk_rate = clk_get_rate(sspi->mclk);
275 if (mclk_rate < (2 * tfr->speed_hz)) {
276 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
277 mclk_rate = clk_get_rate(sspi->mclk);
278 }
279
280 /*
281 * Setup clock divider.
282 *
283 * We have two choices there. Either we can use the clock
284 * divide rate 1, which is calculated thanks to this formula:
285 * SPI_CLK = MOD_CLK / (2 ^ cdr)
286 * Or we can use CDR2, which is calculated with the formula:
287 * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
288 * Wether we use the former or the latter is set through the
289 * DRS bit.
290 *
291 * First try CDR2, and if we can't reach the expected
292 * frequency, fall back to CDR1.
293 */
294 div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz);
295 div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);
296 if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
297 reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;
298 } else {
299 div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));
300 reg = SUN6I_CLK_CTL_CDR1(div);
301 }
302
303 sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
304
305 /* Setup the transfer now... */
306 if (sspi->tx_buf)
307 tx_len = tfr->len;
308
309 /* Setup the counters */
310 sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len));
311 sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len));
312 sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG,
313 SUN6I_BURST_CTL_CNT_STC(tx_len));
314
315 /* Fill the TX FIFO */
316 sun6i_spi_fill_fifo(sspi, sspi->fifo_depth);
317
318 /* Enable the interrupts */
319 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
320 sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TC |
321 SUN6I_INT_CTL_RF_RDY);
322 if (tx_len > sspi->fifo_depth)
323 sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
324
325 /* Start the transfer */
326 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
327 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
328
329 tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
330 start = jiffies;
331 timeout = wait_for_completion_timeout(&sspi->done,
332 msecs_to_jiffies(tx_time));
333 end = jiffies;
334 if (!timeout) {
335 dev_warn(&master->dev,
336 "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
337 dev_name(&spi->dev), tfr->len, tfr->speed_hz,
338 jiffies_to_msecs(end - start), tx_time);
339 ret = -ETIMEDOUT;
340 goto out;
341 }
342
343 out:
344 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
345
346 return ret;
347 }
348
sun6i_spi_handler(int irq,void * dev_id)349 static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
350 {
351 struct sun6i_spi *sspi = dev_id;
352 u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
353
354 /* Transfer complete */
355 if (status & SUN6I_INT_CTL_TC) {
356 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
357 sun6i_spi_drain_fifo(sspi, sspi->fifo_depth);
358 complete(&sspi->done);
359 return IRQ_HANDLED;
360 }
361
362 /* Receive FIFO 3/4 full */
363 if (status & SUN6I_INT_CTL_RF_RDY) {
364 sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
365 /* Only clear the interrupt _after_ draining the FIFO */
366 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
367 return IRQ_HANDLED;
368 }
369
370 /* Transmit FIFO 3/4 empty */
371 if (status & SUN6I_INT_CTL_TF_ERQ) {
372 sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
373
374 if (!sspi->len)
375 /* nothing left to transmit */
376 sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
377
378 /* Only clear the interrupt _after_ re-seeding the FIFO */
379 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ);
380
381 return IRQ_HANDLED;
382 }
383
384 return IRQ_NONE;
385 }
386
sun6i_spi_runtime_resume(struct device * dev)387 static int sun6i_spi_runtime_resume(struct device *dev)
388 {
389 struct spi_master *master = dev_get_drvdata(dev);
390 struct sun6i_spi *sspi = spi_master_get_devdata(master);
391 int ret;
392
393 ret = clk_prepare_enable(sspi->hclk);
394 if (ret) {
395 dev_err(dev, "Couldn't enable AHB clock\n");
396 goto out;
397 }
398
399 ret = clk_prepare_enable(sspi->mclk);
400 if (ret) {
401 dev_err(dev, "Couldn't enable module clock\n");
402 goto err;
403 }
404
405 ret = reset_control_deassert(sspi->rstc);
406 if (ret) {
407 dev_err(dev, "Couldn't deassert the device from reset\n");
408 goto err2;
409 }
410
411 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
412 SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
413
414 return 0;
415
416 err2:
417 clk_disable_unprepare(sspi->mclk);
418 err:
419 clk_disable_unprepare(sspi->hclk);
420 out:
421 return ret;
422 }
423
sun6i_spi_runtime_suspend(struct device * dev)424 static int sun6i_spi_runtime_suspend(struct device *dev)
425 {
426 struct spi_master *master = dev_get_drvdata(dev);
427 struct sun6i_spi *sspi = spi_master_get_devdata(master);
428
429 reset_control_assert(sspi->rstc);
430 clk_disable_unprepare(sspi->mclk);
431 clk_disable_unprepare(sspi->hclk);
432
433 return 0;
434 }
435
sun6i_spi_probe(struct platform_device * pdev)436 static int sun6i_spi_probe(struct platform_device *pdev)
437 {
438 struct spi_master *master;
439 struct sun6i_spi *sspi;
440 struct resource *res;
441 int ret = 0, irq;
442
443 master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
444 if (!master) {
445 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
446 return -ENOMEM;
447 }
448
449 platform_set_drvdata(pdev, master);
450 sspi = spi_master_get_devdata(master);
451
452 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
453 sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
454 if (IS_ERR(sspi->base_addr)) {
455 ret = PTR_ERR(sspi->base_addr);
456 goto err_free_master;
457 }
458
459 irq = platform_get_irq(pdev, 0);
460 if (irq < 0) {
461 dev_err(&pdev->dev, "No spi IRQ specified\n");
462 ret = -ENXIO;
463 goto err_free_master;
464 }
465
466 ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
467 0, "sun6i-spi", sspi);
468 if (ret) {
469 dev_err(&pdev->dev, "Cannot request IRQ\n");
470 goto err_free_master;
471 }
472
473 sspi->master = master;
474 sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev);
475
476 master->max_speed_hz = 100 * 1000 * 1000;
477 master->min_speed_hz = 3 * 1000;
478 master->set_cs = sun6i_spi_set_cs;
479 master->transfer_one = sun6i_spi_transfer_one;
480 master->num_chipselect = 4;
481 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
482 master->bits_per_word_mask = SPI_BPW_MASK(8);
483 master->dev.of_node = pdev->dev.of_node;
484 master->auto_runtime_pm = true;
485 master->max_transfer_size = sun6i_spi_max_transfer_size;
486
487 sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
488 if (IS_ERR(sspi->hclk)) {
489 dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
490 ret = PTR_ERR(sspi->hclk);
491 goto err_free_master;
492 }
493
494 sspi->mclk = devm_clk_get(&pdev->dev, "mod");
495 if (IS_ERR(sspi->mclk)) {
496 dev_err(&pdev->dev, "Unable to acquire module clock\n");
497 ret = PTR_ERR(sspi->mclk);
498 goto err_free_master;
499 }
500
501 init_completion(&sspi->done);
502
503 sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
504 if (IS_ERR(sspi->rstc)) {
505 dev_err(&pdev->dev, "Couldn't get reset controller\n");
506 ret = PTR_ERR(sspi->rstc);
507 goto err_free_master;
508 }
509
510 /*
511 * This wake-up/shutdown pattern is to be able to have the
512 * device woken up, even if runtime_pm is disabled
513 */
514 ret = sun6i_spi_runtime_resume(&pdev->dev);
515 if (ret) {
516 dev_err(&pdev->dev, "Couldn't resume the device\n");
517 goto err_free_master;
518 }
519
520 pm_runtime_set_active(&pdev->dev);
521 pm_runtime_enable(&pdev->dev);
522 pm_runtime_idle(&pdev->dev);
523
524 ret = devm_spi_register_master(&pdev->dev, master);
525 if (ret) {
526 dev_err(&pdev->dev, "cannot register SPI master\n");
527 goto err_pm_disable;
528 }
529
530 return 0;
531
532 err_pm_disable:
533 pm_runtime_disable(&pdev->dev);
534 sun6i_spi_runtime_suspend(&pdev->dev);
535 err_free_master:
536 spi_master_put(master);
537 return ret;
538 }
539
sun6i_spi_remove(struct platform_device * pdev)540 static int sun6i_spi_remove(struct platform_device *pdev)
541 {
542 pm_runtime_force_suspend(&pdev->dev);
543
544 return 0;
545 }
546
547 static const struct of_device_id sun6i_spi_match[] = {
548 { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },
549 { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH },
550 {}
551 };
552 MODULE_DEVICE_TABLE(of, sun6i_spi_match);
553
554 static const struct dev_pm_ops sun6i_spi_pm_ops = {
555 .runtime_resume = sun6i_spi_runtime_resume,
556 .runtime_suspend = sun6i_spi_runtime_suspend,
557 };
558
559 static struct platform_driver sun6i_spi_driver = {
560 .probe = sun6i_spi_probe,
561 .remove = sun6i_spi_remove,
562 .driver = {
563 .name = "sun6i-spi",
564 .of_match_table = sun6i_spi_match,
565 .pm = &sun6i_spi_pm_ops,
566 },
567 };
568 module_platform_driver(sun6i_spi_driver);
569
570 MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
571 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
572 MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
573 MODULE_LICENSE("GPL");
574