Lines Matching full:qspi
2 * TI QSPI driver
137 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi, in ti_qspi_read() argument
140 return readl(qspi->base + reg); in ti_qspi_read()
143 static inline void ti_qspi_write(struct ti_qspi *qspi, in ti_qspi_write() argument
146 writel(val, qspi->base + reg); in ti_qspi_write()
151 struct ti_qspi *qspi = spi_master_get_devdata(spi->master); in ti_qspi_setup() local
152 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; in ti_qspi_setup()
157 dev_dbg(qspi->dev, "master busy doing other transfers\n"); in ti_qspi_setup()
161 if (!qspi->spi_max_frequency) { in ti_qspi_setup()
162 dev_err(qspi->dev, "spi max frequency not defined\n"); in ti_qspi_setup()
166 clk_rate = clk_get_rate(qspi->fclk); in ti_qspi_setup()
168 clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1; in ti_qspi_setup()
171 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n"); in ti_qspi_setup()
176 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n", in ti_qspi_setup()
181 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n", in ti_qspi_setup()
182 qspi->spi_max_frequency, clk_div); in ti_qspi_setup()
184 ret = pm_runtime_get_sync(qspi->dev); in ti_qspi_setup()
186 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n"); in ti_qspi_setup()
190 clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG); in ti_qspi_setup()
195 ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG); in ti_qspi_setup()
199 ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG); in ti_qspi_setup()
202 pm_runtime_mark_last_busy(qspi->dev); in ti_qspi_setup()
203 ret = pm_runtime_put_autosuspend(qspi->dev); in ti_qspi_setup()
205 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n"); in ti_qspi_setup()
212 static void ti_qspi_restore_ctx(struct ti_qspi *qspi) in ti_qspi_restore_ctx() argument
214 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; in ti_qspi_restore_ctx()
216 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG); in ti_qspi_restore_ctx()
219 static inline u32 qspi_is_busy(struct ti_qspi *qspi) in qspi_is_busy() argument
224 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); in qspi_is_busy()
227 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); in qspi_is_busy()
230 WARN(stat & BUSY, "qspi busy\n"); in qspi_is_busy()
234 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi) in ti_qspi_poll_wc() argument
240 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); in ti_qspi_poll_wc()
246 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); in ti_qspi_poll_wc()
252 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t, in qspi_write_msg() argument
261 cmd = qspi->cmd | QSPI_WR_SNGL; in qspi_write_msg()
266 if (qspi_is_busy(qspi)) in qspi_write_msg()
271 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n", in qspi_write_msg()
272 cmd, qspi->dc, *txbuf); in qspi_write_msg()
277 writel(data, qspi->base + in qspi_write_msg()
280 writel(data, qspi->base + in qspi_write_msg()
283 writel(data, qspi->base + in qspi_write_msg()
286 writel(data, qspi->base + in qspi_write_msg()
291 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG); in qspi_write_msg()
292 cmd = qspi->cmd | QSPI_WR_SNGL; in qspi_write_msg()
298 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n", in qspi_write_msg()
299 cmd, qspi->dc, *txbuf); in qspi_write_msg()
300 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); in qspi_write_msg()
303 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n", in qspi_write_msg()
304 cmd, qspi->dc, *txbuf); in qspi_write_msg()
305 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); in qspi_write_msg()
309 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); in qspi_write_msg()
310 if (ti_qspi_poll_wc(qspi)) { in qspi_write_msg()
311 dev_err(qspi->dev, "write timed out\n"); in qspi_write_msg()
321 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t, in qspi_read_msg() argument
329 cmd = qspi->cmd; in qspi_read_msg()
344 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc); in qspi_read_msg()
345 if (qspi_is_busy(qspi)) in qspi_read_msg()
348 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); in qspi_read_msg()
349 if (ti_qspi_poll_wc(qspi)) { in qspi_read_msg()
350 dev_err(qspi->dev, "read timed out\n"); in qspi_read_msg()
355 *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG); in qspi_read_msg()
358 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG); in qspi_read_msg()
361 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG); in qspi_read_msg()
371 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t, in qspi_transfer_msg() argument
377 ret = qspi_write_msg(qspi, t, count); in qspi_transfer_msg()
379 dev_dbg(qspi->dev, "Error while writing\n"); in qspi_transfer_msg()
385 ret = qspi_read_msg(qspi, t, count); in qspi_transfer_msg()
387 dev_dbg(qspi->dev, "Error while reading\n"); in qspi_transfer_msg()
397 struct ti_qspi *qspi = param; in ti_qspi_dma_callback() local
399 complete(&qspi->transfer_complete); in ti_qspi_dma_callback()
402 static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst, in ti_qspi_dma_xfer() argument
405 struct dma_chan *chan = qspi->rx_chan; in ti_qspi_dma_xfer()
413 dev_err(qspi->dev, "device_prep_dma_memcpy error\n"); in ti_qspi_dma_xfer()
418 tx->callback_param = qspi; in ti_qspi_dma_xfer()
420 reinit_completion(&qspi->transfer_complete); in ti_qspi_dma_xfer()
424 dev_err(qspi->dev, "dma_submit_error %d\n", cookie); in ti_qspi_dma_xfer()
429 ret = wait_for_completion_timeout(&qspi->transfer_complete, in ti_qspi_dma_xfer()
433 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n"); in ti_qspi_dma_xfer()
440 static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi, loff_t offs, in ti_qspi_dma_bounce_buffer() argument
443 dma_addr_t dma_src = qspi->mmap_phys_base + offs; in ti_qspi_dma_bounce_buffer()
454 ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr, in ti_qspi_dma_bounce_buffer()
458 memcpy(to, qspi->rx_bb_addr, xfer_len); in ti_qspi_dma_bounce_buffer()
467 static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg, in ti_qspi_dma_xfer_sg() argument
471 dma_addr_t dma_src = qspi->mmap_phys_base + from; in ti_qspi_dma_xfer_sg()
478 ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len); in ti_qspi_dma_xfer_sg()
489 struct ti_qspi *qspi = spi_master_get_devdata(spi->master); in ti_qspi_enable_memory_map() local
491 ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG); in ti_qspi_enable_memory_map()
492 if (qspi->ctrl_base) { in ti_qspi_enable_memory_map()
493 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, in ti_qspi_enable_memory_map()
497 qspi->mmap_enabled = true; in ti_qspi_enable_memory_map()
498 qspi->current_cs = spi->chip_select; in ti_qspi_enable_memory_map()
503 struct ti_qspi *qspi = spi_master_get_devdata(spi->master); in ti_qspi_disable_memory_map() local
505 ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG); in ti_qspi_disable_memory_map()
506 if (qspi->ctrl_base) in ti_qspi_disable_memory_map()
507 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, in ti_qspi_disable_memory_map()
509 qspi->mmap_enabled = false; in ti_qspi_disable_memory_map()
510 qspi->current_cs = -1; in ti_qspi_disable_memory_map()
517 struct ti_qspi *qspi = spi_master_get_devdata(spi->master); in ti_qspi_setup_mmap_read() local
533 ti_qspi_write(qspi, memval, in ti_qspi_setup_mmap_read()
540 struct ti_qspi *qspi = spi_master_get_devdata(mem->spi->master); in ti_qspi_exec_mem_op() local
551 if (from + op->data.nbytes > qspi->mmap_size) in ti_qspi_exec_mem_op()
554 mutex_lock(&qspi->list_lock); in ti_qspi_exec_mem_op()
556 if (!qspi->mmap_enabled || qspi->current_cs != mem->spi->chip_select) in ti_qspi_exec_mem_op()
561 if (qspi->rx_chan) { in ti_qspi_exec_mem_op()
567 ret = ti_qspi_dma_xfer_sg(qspi, sgt, from); in ti_qspi_exec_mem_op()
571 ret = ti_qspi_dma_bounce_buffer(qspi, from, in ti_qspi_exec_mem_op()
576 memcpy_fromio(op->data.buf.in, qspi->mmap_base + from, in ti_qspi_exec_mem_op()
580 mutex_unlock(&qspi->list_lock); in ti_qspi_exec_mem_op()
592 struct ti_qspi *qspi = spi_master_get_devdata(master); in ti_qspi_start_transfer_one() local
600 qspi->dc = 0; in ti_qspi_start_transfer_one()
603 qspi->dc |= QSPI_CKPHA(spi->chip_select); in ti_qspi_start_transfer_one()
605 qspi->dc |= QSPI_CKPOL(spi->chip_select); in ti_qspi_start_transfer_one()
607 qspi->dc |= QSPI_CSPOL(spi->chip_select); in ti_qspi_start_transfer_one()
615 qspi->cmd = 0; in ti_qspi_start_transfer_one()
616 qspi->cmd |= QSPI_EN_CS(spi->chip_select); in ti_qspi_start_transfer_one()
617 qspi->cmd |= QSPI_FLEN(frame_len_words); in ti_qspi_start_transfer_one()
619 ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG); in ti_qspi_start_transfer_one()
621 mutex_lock(&qspi->list_lock); in ti_qspi_start_transfer_one()
623 if (qspi->mmap_enabled) in ti_qspi_start_transfer_one()
627 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) | in ti_qspi_start_transfer_one()
633 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen); in ti_qspi_start_transfer_one()
635 dev_dbg(qspi->dev, "transfer message failed\n"); in ti_qspi_start_transfer_one()
636 mutex_unlock(&qspi->list_lock); in ti_qspi_start_transfer_one()
646 mutex_unlock(&qspi->list_lock); in ti_qspi_start_transfer_one()
648 ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG); in ti_qspi_start_transfer_one()
657 struct ti_qspi *qspi; in ti_qspi_runtime_resume() local
659 qspi = dev_get_drvdata(dev); in ti_qspi_runtime_resume()
660 ti_qspi_restore_ctx(qspi); in ti_qspi_runtime_resume()
666 {.compatible = "ti,dra7xxx-qspi" },
667 {.compatible = "ti,am4372-qspi" },
674 struct ti_qspi *qspi; in ti_qspi_probe() local
682 master = spi_alloc_master(&pdev->dev, sizeof(*qspi)); in ti_qspi_probe()
700 qspi = spi_master_get_devdata(master); in ti_qspi_probe()
701 qspi->master = master; in ti_qspi_probe()
702 qspi->dev = &pdev->dev; in ti_qspi_probe()
703 platform_set_drvdata(pdev, qspi); in ti_qspi_probe()
726 qspi->mmap_size = resource_size(res_mmap); in ti_qspi_probe()
735 mutex_init(&qspi->list_lock); in ti_qspi_probe()
737 qspi->base = devm_ioremap_resource(&pdev->dev, r); in ti_qspi_probe()
738 if (IS_ERR(qspi->base)) { in ti_qspi_probe()
739 ret = PTR_ERR(qspi->base); in ti_qspi_probe()
745 qspi->ctrl_base = in ti_qspi_probe()
748 if (IS_ERR(qspi->ctrl_base)) { in ti_qspi_probe()
749 ret = PTR_ERR(qspi->ctrl_base); in ti_qspi_probe()
754 1, &qspi->ctrl_reg); in ti_qspi_probe()
762 qspi->fclk = devm_clk_get(&pdev->dev, "fck"); in ti_qspi_probe()
763 if (IS_ERR(qspi->fclk)) { in ti_qspi_probe()
764 ret = PTR_ERR(qspi->fclk); in ti_qspi_probe()
773 qspi->spi_max_frequency = max_freq; in ti_qspi_probe()
778 qspi->rx_chan = dma_request_chan_by_mask(&mask); in ti_qspi_probe()
779 if (IS_ERR(qspi->rx_chan)) { in ti_qspi_probe()
780 dev_err(qspi->dev, in ti_qspi_probe()
782 qspi->rx_chan = NULL; in ti_qspi_probe()
786 qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev, in ti_qspi_probe()
788 &qspi->rx_bb_dma_addr, in ti_qspi_probe()
790 if (!qspi->rx_bb_addr) { in ti_qspi_probe()
791 dev_err(qspi->dev, in ti_qspi_probe()
793 dma_release_channel(qspi->rx_chan); in ti_qspi_probe()
796 master->dma_rx = qspi->rx_chan; in ti_qspi_probe()
797 init_completion(&qspi->transfer_complete); in ti_qspi_probe()
799 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start; in ti_qspi_probe()
802 if (!qspi->rx_chan && res_mmap) { in ti_qspi_probe()
803 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap); in ti_qspi_probe()
804 if (IS_ERR(qspi->mmap_base)) { in ti_qspi_probe()
807 PTR_ERR(qspi->mmap_base)); in ti_qspi_probe()
808 qspi->mmap_base = NULL; in ti_qspi_probe()
812 qspi->mmap_enabled = false; in ti_qspi_probe()
813 qspi->current_cs = -1; in ti_qspi_probe()
827 struct ti_qspi *qspi = platform_get_drvdata(pdev); in ti_qspi_remove() local
830 rc = spi_master_suspend(qspi->master); in ti_qspi_remove()
837 if (qspi->rx_bb_addr) in ti_qspi_remove()
838 dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE, in ti_qspi_remove()
839 qspi->rx_bb_addr, in ti_qspi_remove()
840 qspi->rx_bb_dma_addr); in ti_qspi_remove()
841 if (qspi->rx_chan) in ti_qspi_remove()
842 dma_release_channel(qspi->rx_chan); in ti_qspi_remove()
855 .name = "ti-qspi",
865 MODULE_DESCRIPTION("TI QSPI controller driver");
866 MODULE_ALIAS("platform:ti-qspi");