1 /*
2 * TI QSPI driver
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Sourav Poddar <sourav.poddar@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GPLv2.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/delay.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/omap-dma.h>
25 #include <linux/platform_device.h>
26 #include <linux/err.h>
27 #include <linux/clk.h>
28 #include <linux/io.h>
29 #include <linux/slab.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/of.h>
32 #include <linux/of_device.h>
33 #include <linux/pinctrl/consumer.h>
34 #include <linux/mfd/syscon.h>
35 #include <linux/regmap.h>
36 #include <linux/sizes.h>
37
38 #include <linux/spi/spi.h>
39 #include <linux/spi/spi-mem.h>
40
41 struct ti_qspi_regs {
42 u32 clkctrl;
43 };
44
45 struct ti_qspi {
46 struct completion transfer_complete;
47
48 /* list synchronization */
49 struct mutex list_lock;
50
51 struct spi_master *master;
52 void __iomem *base;
53 void __iomem *mmap_base;
54 size_t mmap_size;
55 struct regmap *ctrl_base;
56 unsigned int ctrl_reg;
57 struct clk *fclk;
58 struct device *dev;
59
60 struct ti_qspi_regs ctx_reg;
61
62 dma_addr_t mmap_phys_base;
63 dma_addr_t rx_bb_dma_addr;
64 void *rx_bb_addr;
65 struct dma_chan *rx_chan;
66
67 u32 spi_max_frequency;
68 u32 cmd;
69 u32 dc;
70
71 bool mmap_enabled;
72 int current_cs;
73 };
74
75 #define QSPI_PID (0x0)
76 #define QSPI_SYSCONFIG (0x10)
77 #define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
78 #define QSPI_SPI_DC_REG (0x44)
79 #define QSPI_SPI_CMD_REG (0x48)
80 #define QSPI_SPI_STATUS_REG (0x4c)
81 #define QSPI_SPI_DATA_REG (0x50)
82 #define QSPI_SPI_SETUP_REG(n) ((0x54 + 4 * n))
83 #define QSPI_SPI_SWITCH_REG (0x64)
84 #define QSPI_SPI_DATA_REG_1 (0x68)
85 #define QSPI_SPI_DATA_REG_2 (0x6c)
86 #define QSPI_SPI_DATA_REG_3 (0x70)
87
88 #define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
89
90 #define QSPI_FCLK 192000000
91
92 /* Clock Control */
93 #define QSPI_CLK_EN (1 << 31)
94 #define QSPI_CLK_DIV_MAX 0xffff
95
96 /* Command */
97 #define QSPI_EN_CS(n) (n << 28)
98 #define QSPI_WLEN(n) ((n - 1) << 19)
99 #define QSPI_3_PIN (1 << 18)
100 #define QSPI_RD_SNGL (1 << 16)
101 #define QSPI_WR_SNGL (2 << 16)
102 #define QSPI_RD_DUAL (3 << 16)
103 #define QSPI_RD_QUAD (7 << 16)
104 #define QSPI_INVAL (4 << 16)
105 #define QSPI_FLEN(n) ((n - 1) << 0)
106 #define QSPI_WLEN_MAX_BITS 128
107 #define QSPI_WLEN_MAX_BYTES 16
108 #define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
109
110 /* STATUS REGISTER */
111 #define BUSY 0x01
112 #define WC 0x02
113
114 /* Device Control */
115 #define QSPI_DD(m, n) (m << (3 + n * 8))
116 #define QSPI_CKPHA(n) (1 << (2 + n * 8))
117 #define QSPI_CSPOL(n) (1 << (1 + n * 8))
118 #define QSPI_CKPOL(n) (1 << (n * 8))
119
120 #define QSPI_FRAME 4096
121
122 #define QSPI_AUTOSUSPEND_TIMEOUT 2000
123
124 #define MEM_CS_EN(n) ((n + 1) << 8)
125 #define MEM_CS_MASK (7 << 8)
126
127 #define MM_SWITCH 0x1
128
129 #define QSPI_SETUP_RD_NORMAL (0x0 << 12)
130 #define QSPI_SETUP_RD_DUAL (0x1 << 12)
131 #define QSPI_SETUP_RD_QUAD (0x3 << 12)
132 #define QSPI_SETUP_ADDR_SHIFT 8
133 #define QSPI_SETUP_DUMMY_SHIFT 10
134
135 #define QSPI_DMA_BUFFER_SIZE SZ_64K
136
ti_qspi_read(struct ti_qspi * qspi,unsigned long reg)137 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
138 unsigned long reg)
139 {
140 return readl(qspi->base + reg);
141 }
142
ti_qspi_write(struct ti_qspi * qspi,unsigned long val,unsigned long reg)143 static inline void ti_qspi_write(struct ti_qspi *qspi,
144 unsigned long val, unsigned long reg)
145 {
146 writel(val, qspi->base + reg);
147 }
148
ti_qspi_setup(struct spi_device * spi)149 static int ti_qspi_setup(struct spi_device *spi)
150 {
151 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
152 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
153 int clk_div = 0, ret;
154 u32 clk_ctrl_reg, clk_rate, clk_mask;
155
156 if (spi->master->busy) {
157 dev_dbg(qspi->dev, "master busy doing other transfers\n");
158 return -EBUSY;
159 }
160
161 if (!qspi->spi_max_frequency) {
162 dev_err(qspi->dev, "spi max frequency not defined\n");
163 return -EINVAL;
164 }
165
166 clk_rate = clk_get_rate(qspi->fclk);
167
168 clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
169
170 if (clk_div < 0) {
171 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
172 return -EINVAL;
173 }
174
175 if (clk_div > QSPI_CLK_DIV_MAX) {
176 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
177 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
178 return -EINVAL;
179 }
180
181 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
182 qspi->spi_max_frequency, clk_div);
183
184 ret = pm_runtime_get_sync(qspi->dev);
185 if (ret < 0) {
186 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
187 return ret;
188 }
189
190 clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
191
192 clk_ctrl_reg &= ~QSPI_CLK_EN;
193
194 /* disable SCLK */
195 ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
196
197 /* enable SCLK */
198 clk_mask = QSPI_CLK_EN | clk_div;
199 ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
200 ctx_reg->clkctrl = clk_mask;
201
202 pm_runtime_mark_last_busy(qspi->dev);
203 ret = pm_runtime_put_autosuspend(qspi->dev);
204 if (ret < 0) {
205 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
206 return ret;
207 }
208
209 return 0;
210 }
211
ti_qspi_restore_ctx(struct ti_qspi * qspi)212 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
213 {
214 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
215
216 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
217 }
218
qspi_is_busy(struct ti_qspi * qspi)219 static inline u32 qspi_is_busy(struct ti_qspi *qspi)
220 {
221 u32 stat;
222 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
223
224 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
225 while ((stat & BUSY) && time_after(timeout, jiffies)) {
226 cpu_relax();
227 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
228 }
229
230 WARN(stat & BUSY, "qspi busy\n");
231 return stat & BUSY;
232 }
233
ti_qspi_poll_wc(struct ti_qspi * qspi)234 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
235 {
236 u32 stat;
237 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
238
239 do {
240 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
241 if (stat & WC)
242 return 0;
243 cpu_relax();
244 } while (time_after(timeout, jiffies));
245
246 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
247 if (stat & WC)
248 return 0;
249 return -ETIMEDOUT;
250 }
251
qspi_write_msg(struct ti_qspi * qspi,struct spi_transfer * t,int count)252 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
253 int count)
254 {
255 int wlen, xfer_len;
256 unsigned int cmd;
257 const u8 *txbuf;
258 u32 data;
259
260 txbuf = t->tx_buf;
261 cmd = qspi->cmd | QSPI_WR_SNGL;
262 wlen = t->bits_per_word >> 3; /* in bytes */
263 xfer_len = wlen;
264
265 while (count) {
266 if (qspi_is_busy(qspi))
267 return -EBUSY;
268
269 switch (wlen) {
270 case 1:
271 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
272 cmd, qspi->dc, *txbuf);
273 if (count >= QSPI_WLEN_MAX_BYTES) {
274 u32 *txp = (u32 *)txbuf;
275
276 data = cpu_to_be32(*txp++);
277 writel(data, qspi->base +
278 QSPI_SPI_DATA_REG_3);
279 data = cpu_to_be32(*txp++);
280 writel(data, qspi->base +
281 QSPI_SPI_DATA_REG_2);
282 data = cpu_to_be32(*txp++);
283 writel(data, qspi->base +
284 QSPI_SPI_DATA_REG_1);
285 data = cpu_to_be32(*txp++);
286 writel(data, qspi->base +
287 QSPI_SPI_DATA_REG);
288 xfer_len = QSPI_WLEN_MAX_BYTES;
289 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
290 } else {
291 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
292 cmd = qspi->cmd | QSPI_WR_SNGL;
293 xfer_len = wlen;
294 cmd |= QSPI_WLEN(wlen);
295 }
296 break;
297 case 2:
298 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
299 cmd, qspi->dc, *txbuf);
300 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
301 break;
302 case 4:
303 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
304 cmd, qspi->dc, *txbuf);
305 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
306 break;
307 }
308
309 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
310 if (ti_qspi_poll_wc(qspi)) {
311 dev_err(qspi->dev, "write timed out\n");
312 return -ETIMEDOUT;
313 }
314 txbuf += xfer_len;
315 count -= xfer_len;
316 }
317
318 return 0;
319 }
320
qspi_read_msg(struct ti_qspi * qspi,struct spi_transfer * t,int count)321 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
322 int count)
323 {
324 int wlen;
325 unsigned int cmd;
326 u8 *rxbuf;
327
328 rxbuf = t->rx_buf;
329 cmd = qspi->cmd;
330 switch (t->rx_nbits) {
331 case SPI_NBITS_DUAL:
332 cmd |= QSPI_RD_DUAL;
333 break;
334 case SPI_NBITS_QUAD:
335 cmd |= QSPI_RD_QUAD;
336 break;
337 default:
338 cmd |= QSPI_RD_SNGL;
339 break;
340 }
341 wlen = t->bits_per_word >> 3; /* in bytes */
342
343 while (count) {
344 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
345 if (qspi_is_busy(qspi))
346 return -EBUSY;
347
348 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
349 if (ti_qspi_poll_wc(qspi)) {
350 dev_err(qspi->dev, "read timed out\n");
351 return -ETIMEDOUT;
352 }
353 switch (wlen) {
354 case 1:
355 *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
356 break;
357 case 2:
358 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
359 break;
360 case 4:
361 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
362 break;
363 }
364 rxbuf += wlen;
365 count -= wlen;
366 }
367
368 return 0;
369 }
370
qspi_transfer_msg(struct ti_qspi * qspi,struct spi_transfer * t,int count)371 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
372 int count)
373 {
374 int ret;
375
376 if (t->tx_buf) {
377 ret = qspi_write_msg(qspi, t, count);
378 if (ret) {
379 dev_dbg(qspi->dev, "Error while writing\n");
380 return ret;
381 }
382 }
383
384 if (t->rx_buf) {
385 ret = qspi_read_msg(qspi, t, count);
386 if (ret) {
387 dev_dbg(qspi->dev, "Error while reading\n");
388 return ret;
389 }
390 }
391
392 return 0;
393 }
394
ti_qspi_dma_callback(void * param)395 static void ti_qspi_dma_callback(void *param)
396 {
397 struct ti_qspi *qspi = param;
398
399 complete(&qspi->transfer_complete);
400 }
401
ti_qspi_dma_xfer(struct ti_qspi * qspi,dma_addr_t dma_dst,dma_addr_t dma_src,size_t len)402 static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst,
403 dma_addr_t dma_src, size_t len)
404 {
405 struct dma_chan *chan = qspi->rx_chan;
406 dma_cookie_t cookie;
407 enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
408 struct dma_async_tx_descriptor *tx;
409 int ret;
410
411 tx = dmaengine_prep_dma_memcpy(chan, dma_dst, dma_src, len, flags);
412 if (!tx) {
413 dev_err(qspi->dev, "device_prep_dma_memcpy error\n");
414 return -EIO;
415 }
416
417 tx->callback = ti_qspi_dma_callback;
418 tx->callback_param = qspi;
419 cookie = tx->tx_submit(tx);
420 reinit_completion(&qspi->transfer_complete);
421
422 ret = dma_submit_error(cookie);
423 if (ret) {
424 dev_err(qspi->dev, "dma_submit_error %d\n", cookie);
425 return -EIO;
426 }
427
428 dma_async_issue_pending(chan);
429 ret = wait_for_completion_timeout(&qspi->transfer_complete,
430 msecs_to_jiffies(len));
431 if (ret <= 0) {
432 dmaengine_terminate_sync(chan);
433 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n");
434 return -ETIMEDOUT;
435 }
436
437 return 0;
438 }
439
ti_qspi_dma_bounce_buffer(struct ti_qspi * qspi,loff_t offs,void * to,size_t readsize)440 static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi, loff_t offs,
441 void *to, size_t readsize)
442 {
443 dma_addr_t dma_src = qspi->mmap_phys_base + offs;
444 int ret = 0;
445
446 /*
447 * Use bounce buffer as FS like jffs2, ubifs may pass
448 * buffers that does not belong to kernel lowmem region.
449 */
450 while (readsize != 0) {
451 size_t xfer_len = min_t(size_t, QSPI_DMA_BUFFER_SIZE,
452 readsize);
453
454 ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr,
455 dma_src, xfer_len);
456 if (ret != 0)
457 return ret;
458 memcpy(to, qspi->rx_bb_addr, xfer_len);
459 readsize -= xfer_len;
460 dma_src += xfer_len;
461 to += xfer_len;
462 }
463
464 return ret;
465 }
466
ti_qspi_dma_xfer_sg(struct ti_qspi * qspi,struct sg_table rx_sg,loff_t from)467 static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg,
468 loff_t from)
469 {
470 struct scatterlist *sg;
471 dma_addr_t dma_src = qspi->mmap_phys_base + from;
472 dma_addr_t dma_dst;
473 int i, len, ret;
474
475 for_each_sg(rx_sg.sgl, sg, rx_sg.nents, i) {
476 dma_dst = sg_dma_address(sg);
477 len = sg_dma_len(sg);
478 ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len);
479 if (ret)
480 return ret;
481 dma_src += len;
482 }
483
484 return 0;
485 }
486
ti_qspi_enable_memory_map(struct spi_device * spi)487 static void ti_qspi_enable_memory_map(struct spi_device *spi)
488 {
489 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
490
491 ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
492 if (qspi->ctrl_base) {
493 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
494 MEM_CS_MASK,
495 MEM_CS_EN(spi->chip_select));
496 }
497 qspi->mmap_enabled = true;
498 qspi->current_cs = spi->chip_select;
499 }
500
ti_qspi_disable_memory_map(struct spi_device * spi)501 static void ti_qspi_disable_memory_map(struct spi_device *spi)
502 {
503 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
504
505 ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
506 if (qspi->ctrl_base)
507 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
508 MEM_CS_MASK, 0);
509 qspi->mmap_enabled = false;
510 qspi->current_cs = -1;
511 }
512
ti_qspi_setup_mmap_read(struct spi_device * spi,u8 opcode,u8 data_nbits,u8 addr_width,u8 dummy_bytes)513 static void ti_qspi_setup_mmap_read(struct spi_device *spi, u8 opcode,
514 u8 data_nbits, u8 addr_width,
515 u8 dummy_bytes)
516 {
517 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
518 u32 memval = opcode;
519
520 switch (data_nbits) {
521 case SPI_NBITS_QUAD:
522 memval |= QSPI_SETUP_RD_QUAD;
523 break;
524 case SPI_NBITS_DUAL:
525 memval |= QSPI_SETUP_RD_DUAL;
526 break;
527 default:
528 memval |= QSPI_SETUP_RD_NORMAL;
529 break;
530 }
531 memval |= ((addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
532 dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
533 ti_qspi_write(qspi, memval,
534 QSPI_SPI_SETUP_REG(spi->chip_select));
535 }
536
ti_qspi_exec_mem_op(struct spi_mem * mem,const struct spi_mem_op * op)537 static int ti_qspi_exec_mem_op(struct spi_mem *mem,
538 const struct spi_mem_op *op)
539 {
540 struct ti_qspi *qspi = spi_master_get_devdata(mem->spi->master);
541 u32 from = 0;
542 int ret = 0;
543
544 /* Only optimize read path. */
545 if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
546 !op->addr.nbytes || op->addr.nbytes > 4)
547 return -ENOTSUPP;
548
549 /* Address exceeds MMIO window size, fall back to regular mode. */
550 from = op->addr.val;
551 if (from + op->data.nbytes > qspi->mmap_size)
552 return -ENOTSUPP;
553
554 mutex_lock(&qspi->list_lock);
555
556 if (!qspi->mmap_enabled || qspi->current_cs != mem->spi->chip_select)
557 ti_qspi_enable_memory_map(mem->spi);
558 ti_qspi_setup_mmap_read(mem->spi, op->cmd.opcode, op->data.buswidth,
559 op->addr.nbytes, op->dummy.nbytes);
560
561 if (qspi->rx_chan) {
562 struct sg_table sgt;
563
564 if (virt_addr_valid(op->data.buf.in) &&
565 !spi_controller_dma_map_mem_op_data(mem->spi->master, op,
566 &sgt)) {
567 ret = ti_qspi_dma_xfer_sg(qspi, sgt, from);
568 spi_controller_dma_unmap_mem_op_data(mem->spi->master,
569 op, &sgt);
570 } else {
571 ret = ti_qspi_dma_bounce_buffer(qspi, from,
572 op->data.buf.in,
573 op->data.nbytes);
574 }
575 } else {
576 memcpy_fromio(op->data.buf.in, qspi->mmap_base + from,
577 op->data.nbytes);
578 }
579
580 mutex_unlock(&qspi->list_lock);
581
582 return ret;
583 }
584
585 static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
586 .exec_op = ti_qspi_exec_mem_op,
587 };
588
ti_qspi_start_transfer_one(struct spi_master * master,struct spi_message * m)589 static int ti_qspi_start_transfer_one(struct spi_master *master,
590 struct spi_message *m)
591 {
592 struct ti_qspi *qspi = spi_master_get_devdata(master);
593 struct spi_device *spi = m->spi;
594 struct spi_transfer *t;
595 int status = 0, ret;
596 unsigned int frame_len_words, transfer_len_words;
597 int wlen;
598
599 /* setup device control reg */
600 qspi->dc = 0;
601
602 if (spi->mode & SPI_CPHA)
603 qspi->dc |= QSPI_CKPHA(spi->chip_select);
604 if (spi->mode & SPI_CPOL)
605 qspi->dc |= QSPI_CKPOL(spi->chip_select);
606 if (spi->mode & SPI_CS_HIGH)
607 qspi->dc |= QSPI_CSPOL(spi->chip_select);
608
609 frame_len_words = 0;
610 list_for_each_entry(t, &m->transfers, transfer_list)
611 frame_len_words += t->len / (t->bits_per_word >> 3);
612 frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
613
614 /* setup command reg */
615 qspi->cmd = 0;
616 qspi->cmd |= QSPI_EN_CS(spi->chip_select);
617 qspi->cmd |= QSPI_FLEN(frame_len_words);
618
619 ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
620
621 mutex_lock(&qspi->list_lock);
622
623 if (qspi->mmap_enabled)
624 ti_qspi_disable_memory_map(spi);
625
626 list_for_each_entry(t, &m->transfers, transfer_list) {
627 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
628 QSPI_WLEN(t->bits_per_word));
629
630 wlen = t->bits_per_word >> 3;
631 transfer_len_words = min(t->len / wlen, frame_len_words);
632
633 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
634 if (ret) {
635 dev_dbg(qspi->dev, "transfer message failed\n");
636 mutex_unlock(&qspi->list_lock);
637 return -EINVAL;
638 }
639
640 m->actual_length += transfer_len_words * wlen;
641 frame_len_words -= transfer_len_words;
642 if (frame_len_words == 0)
643 break;
644 }
645
646 mutex_unlock(&qspi->list_lock);
647
648 ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
649 m->status = status;
650 spi_finalize_current_message(master);
651
652 return status;
653 }
654
ti_qspi_runtime_resume(struct device * dev)655 static int ti_qspi_runtime_resume(struct device *dev)
656 {
657 struct ti_qspi *qspi;
658
659 qspi = dev_get_drvdata(dev);
660 ti_qspi_restore_ctx(qspi);
661
662 return 0;
663 }
664
665 static const struct of_device_id ti_qspi_match[] = {
666 {.compatible = "ti,dra7xxx-qspi" },
667 {.compatible = "ti,am4372-qspi" },
668 {},
669 };
670 MODULE_DEVICE_TABLE(of, ti_qspi_match);
671
ti_qspi_probe(struct platform_device * pdev)672 static int ti_qspi_probe(struct platform_device *pdev)
673 {
674 struct ti_qspi *qspi;
675 struct spi_master *master;
676 struct resource *r, *res_mmap;
677 struct device_node *np = pdev->dev.of_node;
678 u32 max_freq;
679 int ret = 0, num_cs, irq;
680 dma_cap_mask_t mask;
681
682 master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
683 if (!master)
684 return -ENOMEM;
685
686 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
687
688 master->flags = SPI_MASTER_HALF_DUPLEX;
689 master->setup = ti_qspi_setup;
690 master->auto_runtime_pm = true;
691 master->transfer_one_message = ti_qspi_start_transfer_one;
692 master->dev.of_node = pdev->dev.of_node;
693 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
694 SPI_BPW_MASK(8);
695 master->mem_ops = &ti_qspi_mem_ops;
696
697 if (!of_property_read_u32(np, "num-cs", &num_cs))
698 master->num_chipselect = num_cs;
699
700 qspi = spi_master_get_devdata(master);
701 qspi->master = master;
702 qspi->dev = &pdev->dev;
703 platform_set_drvdata(pdev, qspi);
704
705 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
706 if (r == NULL) {
707 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
708 if (r == NULL) {
709 dev_err(&pdev->dev, "missing platform data\n");
710 ret = -ENODEV;
711 goto free_master;
712 }
713 }
714
715 res_mmap = platform_get_resource_byname(pdev,
716 IORESOURCE_MEM, "qspi_mmap");
717 if (res_mmap == NULL) {
718 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
719 if (res_mmap == NULL) {
720 dev_err(&pdev->dev,
721 "memory mapped resource not required\n");
722 }
723 }
724
725 if (res_mmap)
726 qspi->mmap_size = resource_size(res_mmap);
727
728 irq = platform_get_irq(pdev, 0);
729 if (irq < 0) {
730 dev_err(&pdev->dev, "no irq resource?\n");
731 ret = irq;
732 goto free_master;
733 }
734
735 mutex_init(&qspi->list_lock);
736
737 qspi->base = devm_ioremap_resource(&pdev->dev, r);
738 if (IS_ERR(qspi->base)) {
739 ret = PTR_ERR(qspi->base);
740 goto free_master;
741 }
742
743
744 if (of_property_read_bool(np, "syscon-chipselects")) {
745 qspi->ctrl_base =
746 syscon_regmap_lookup_by_phandle(np,
747 "syscon-chipselects");
748 if (IS_ERR(qspi->ctrl_base)) {
749 ret = PTR_ERR(qspi->ctrl_base);
750 goto free_master;
751 }
752 ret = of_property_read_u32_index(np,
753 "syscon-chipselects",
754 1, &qspi->ctrl_reg);
755 if (ret) {
756 dev_err(&pdev->dev,
757 "couldn't get ctrl_mod reg index\n");
758 goto free_master;
759 }
760 }
761
762 qspi->fclk = devm_clk_get(&pdev->dev, "fck");
763 if (IS_ERR(qspi->fclk)) {
764 ret = PTR_ERR(qspi->fclk);
765 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
766 }
767
768 pm_runtime_use_autosuspend(&pdev->dev);
769 pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
770 pm_runtime_enable(&pdev->dev);
771
772 if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
773 qspi->spi_max_frequency = max_freq;
774
775 dma_cap_zero(mask);
776 dma_cap_set(DMA_MEMCPY, mask);
777
778 qspi->rx_chan = dma_request_chan_by_mask(&mask);
779 if (IS_ERR(qspi->rx_chan)) {
780 dev_err(qspi->dev,
781 "No Rx DMA available, trying mmap mode\n");
782 qspi->rx_chan = NULL;
783 ret = 0;
784 goto no_dma;
785 }
786 qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev,
787 QSPI_DMA_BUFFER_SIZE,
788 &qspi->rx_bb_dma_addr,
789 GFP_KERNEL | GFP_DMA);
790 if (!qspi->rx_bb_addr) {
791 dev_err(qspi->dev,
792 "dma_alloc_coherent failed, using PIO mode\n");
793 dma_release_channel(qspi->rx_chan);
794 goto no_dma;
795 }
796 master->dma_rx = qspi->rx_chan;
797 init_completion(&qspi->transfer_complete);
798 if (res_mmap)
799 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start;
800
801 no_dma:
802 if (!qspi->rx_chan && res_mmap) {
803 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
804 if (IS_ERR(qspi->mmap_base)) {
805 dev_info(&pdev->dev,
806 "mmap failed with error %ld using PIO mode\n",
807 PTR_ERR(qspi->mmap_base));
808 qspi->mmap_base = NULL;
809 master->mem_ops = NULL;
810 }
811 }
812 qspi->mmap_enabled = false;
813 qspi->current_cs = -1;
814
815 ret = devm_spi_register_master(&pdev->dev, master);
816 if (!ret)
817 return 0;
818
819 pm_runtime_disable(&pdev->dev);
820 free_master:
821 spi_master_put(master);
822 return ret;
823 }
824
ti_qspi_remove(struct platform_device * pdev)825 static int ti_qspi_remove(struct platform_device *pdev)
826 {
827 struct ti_qspi *qspi = platform_get_drvdata(pdev);
828 int rc;
829
830 rc = spi_master_suspend(qspi->master);
831 if (rc)
832 return rc;
833
834 pm_runtime_put_sync(&pdev->dev);
835 pm_runtime_disable(&pdev->dev);
836
837 if (qspi->rx_bb_addr)
838 dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE,
839 qspi->rx_bb_addr,
840 qspi->rx_bb_dma_addr);
841 if (qspi->rx_chan)
842 dma_release_channel(qspi->rx_chan);
843
844 return 0;
845 }
846
847 static const struct dev_pm_ops ti_qspi_pm_ops = {
848 .runtime_resume = ti_qspi_runtime_resume,
849 };
850
851 static struct platform_driver ti_qspi_driver = {
852 .probe = ti_qspi_probe,
853 .remove = ti_qspi_remove,
854 .driver = {
855 .name = "ti-qspi",
856 .pm = &ti_qspi_pm_ops,
857 .of_match_table = ti_qspi_match,
858 }
859 };
860
861 module_platform_driver(ti_qspi_driver);
862
863 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
864 MODULE_LICENSE("GPL v2");
865 MODULE_DESCRIPTION("TI QSPI controller driver");
866 MODULE_ALIAS("platform:ti-qspi");
867