Lines Matching refs:assigned
247 assigned-clocks = <&clk IMX8QM_I2C0_CLK>;
248 assigned-clock-rates = <24000000>;
261 assigned-clocks = <&clk IMX8QM_I2C1_CLK>;
262 assigned-clock-rates = <24000000>;
275 assigned-clocks = <&clk IMX8QM_I2C2_CLK>;
276 assigned-clock-rates = <24000000>;
289 assigned-clocks = <&clk IMX8QM_I2C3_CLK>;
290 assigned-clock-rates = <24000000>;
303 assigned-clocks = <&clk IMX8QM_I2C4_CLK>;
304 assigned-clock-rates = <24000000>;
404 assigned-clocks = <&clk IMX8QM_UART0_CLK>;
405 assigned-clock-rates = <80000000>;
417 assigned-clocks = <&clk IMX8QM_UART1_CLK>;
418 assigned-clock-rates = <80000000>;
430 assigned-clocks = <&clk IMX8QM_UART2_CLK>;
431 assigned-clock-rates = <80000000>;
443 assigned-clocks = <&clk IMX8QM_UART3_CLK>;
444 assigned-clock-rates = <80000000>;
456 assigned-clocks = <&clk IMX8QM_UART4_CLK>;
457 assigned-clock-rates = <80000000>;
471 assigned-clocks = <&clk IMX8QM_SDHC0_DIV>;
472 assigned-clock-rates = <400000000>;
488 assigned-clocks = <&clk IMX8QM_SDHC1_DIV>;
489 assigned-clock-rates = <200000000>;
505 assigned-clocks = <&clk IMX8QM_SDHC2_DIV>;
506 assigned-clock-rates = <200000000>;
525 assigned-clocks = <&clk IMX8QM_ENET0_ROOT_DIV>,
527 assigned-clock-rates = <250000000>, <125000000>;
549 assigned-clocks = <&clk IMX8QM_ENET1_ROOT_DIV>,
551 assigned-clock-rates = <250000000>, <125000000>;