1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018 NXP 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include "fsl-imx8-ca53.dtsi" 8#include <dt-bindings/clock/imx8qm-clock.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/soc/imx_rsrc.h> 11#include <dt-bindings/soc/imx8_pd.h> 12#include <dt-bindings/pinctrl/pads-imx8qm.h> 13#include <dt-bindings/gpio/gpio.h> 14 15/ { 16 compatible = "fsl,imx8qm"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &fec1; 23 ethernet1 = &fec2; 24 gpio0 = &gpio1; 25 gpio1 = &gpio2; 26 gpio2 = &gpio3; 27 gpio3 = &gpio4; 28 gpio4 = &gpio5; 29 gpio5 = &gpio6; 30 gpio6 = &gpio7; 31 serial0 = &lpuart0; 32 serial1 = &lpuart1; 33 serial2 = &lpuart2; 34 serial3 = &lpuart3; 35 serial4 = &lpuart4; 36 mmc0 = &usdhc1; 37 mmc1 = &usdhc2; 38 mmc2 = &usdhc3; 39 i2c0 = &i2c0; 40 i2c1 = &i2c1; 41 i2c2 = &i2c2; 42 i2c3 = &i2c3; 43 i2c4 = &i2c4; 44 }; 45 46 memory@80000000 { 47 device_type = "memory"; 48 reg = <0x00000000 0x80000000 0 0x40000000>; 49 /* DRAM space - 1, size : 1 GB DRAM */ 50 }; 51 52 gic: interrupt-controller@51a00000 { 53 compatible = "arm,gic-v3"; 54 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 55 <0x0 0x51b00000 0 0xC0000>, /* GICR */ 56 <0x0 0x52000000 0 0x2000>, /* GICC */ 57 <0x0 0x52010000 0 0x1000>, /* GICH */ 58 <0x0 0x52020000 0 0x20000>; /* GICV */ 59 #interrupt-cells = <3>; 60 interrupt-controller; 61 interrupts = <GIC_PPI 9 62 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 63 interrupt-parent = <&gic>; 64 }; 65 66 mu: mu@5d1c0000 { 67 compatible = "fsl,imx8-mu"; 68 reg = <0x0 0x5d1c0000 0x0 0x10000>; 69 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 70 interrupt-parent = <&gic>; 71 fsl,scu_ap_mu_id = <0>; 72 status = "okay"; 73 74 clk: clk { 75 compatible = "fsl,imx8qm-clk"; 76 #clock-cells = <1>; 77 }; 78 79 iomuxc: iomuxc { 80 compatible = "fsl,imx8qm-iomuxc"; 81 }; 82 }; 83 84 imx8qm-pm { 85 compatible = "simple-bus"; 86 #address-cells = <1>; 87 #size-cells = <0>; 88 89 pd_lsio: PD_LSIO { 90 compatible = "nxp,imx8-pd"; 91 reg = <SC_R_LAST>; 92 #power-domain-cells = <0>; 93 #address-cells = <1>; 94 #size-cells = <0>; 95 96 pd_lsio_gpio0: PD_LSIO_GPIO_0 { 97 reg = <SC_R_GPIO_0>; 98 #power-domain-cells = <0>; 99 power-domains = <&pd_lsio>; 100 }; 101 pd_lsio_gpio1: PD_LSIO_GPIO_1 { 102 reg = <SC_R_GPIO_1>; 103 #power-domain-cells = <0>; 104 power-domains = <&pd_lsio>; 105 }; 106 pd_lsio_gpio2: PD_LSIO_GPIO_2 { 107 reg = <SC_R_GPIO_2>; 108 #power-domain-cells = <0>; 109 power-domains = <&pd_lsio>; 110 }; 111 pd_lsio_gpio3: PD_LSIO_GPIO_3 { 112 reg = <SC_R_GPIO_3>; 113 #power-domain-cells = <0>; 114 power-domains = <&pd_lsio>; 115 }; 116 pd_lsio_gpio4: PD_LSIO_GPIO_4 { 117 reg = <SC_R_GPIO_4>; 118 #power-domain-cells = <0>; 119 power-domains = <&pd_lsio>; 120 }; 121 pd_lsio_gpio5: PD_LSIO_GPIO_5{ 122 reg = <SC_R_GPIO_5>; 123 #power-domain-cells = <0>; 124 power-domains = <&pd_lsio>; 125 }; 126 pd_lsio_gpio6:PD_LSIO_GPIO_6 { 127 reg = <SC_R_GPIO_6>; 128 #power-domain-cells = <0>; 129 power-domains = <&pd_lsio>; 130 }; 131 pd_lsio_gpio7: PD_LSIO_GPIO_7 { 132 reg = <SC_R_GPIO_7>; 133 #power-domain-cells = <0>; 134 power-domains = <&pd_lsio>; 135 }; 136 }; 137 138 pd_conn: PD_CONN { 139 compatible = "nxp,imx8-pd"; 140 reg = <SC_R_LAST>; 141 #power-domain-cells = <0>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 145 pd_conn_sdch0: PD_CONN_SDHC_0 { 146 reg = <SC_R_SDHC_0>; 147 #power-domain-cells = <0>; 148 power-domains = <&pd_conn>; 149 }; 150 pd_conn_sdch1: PD_CONN_SDHC_1 { 151 reg = <SC_R_SDHC_1>; 152 #power-domain-cells = <0>; 153 power-domains = <&pd_conn>; 154 }; 155 pd_conn_sdch2: PD_CONN_SDHC_2 { 156 reg = <SC_R_SDHC_2>; 157 #power-domain-cells = <0>; 158 power-domains = <&pd_conn>; 159 }; 160 pd_conn_enet0: PD_CONN_ENET_0 { 161 reg = <SC_R_ENET_0>; 162 #power-domain-cells = <0>; 163 power-domains = <&pd_conn>; 164 wakeup-irq = <258>; 165 }; 166 pd_conn_enet1: PD_CONN_ENET_1 { 167 reg = <SC_R_ENET_1>; 168 #power-domain-cells = <0>; 169 power-domains = <&pd_conn>; 170 fsl,wakeup_irq = <262>; 171 }; 172 }; 173 174 pd_dma: PD_DMA { 175 compatible = "nxp,imx8-pd"; 176 reg = <SC_R_LAST>; 177 #power-domain-cells = <0>; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 181 pd_dma_lpi2c0: PD_DMA_I2C_0 { 182 reg = <SC_R_I2C_0>; 183 #power-domain-cells = <0>; 184 power-domains = <&pd_dma>; 185 }; 186 pd_dma_lpi2c1: PD_DMA_I2C_1 { 187 reg = <SC_R_I2C_1>; 188 #power-domain-cells = <0>; 189 power-domains = <&pd_dma>; 190 }; 191 pd_dma_lpi2c2:PD_DMA_I2C_2 { 192 reg = <SC_R_I2C_2>; 193 #power-domain-cells = <0>; 194 power-domains = <&pd_dma>; 195 }; 196 pd_dma_lpi2c3: PD_DMA_I2C_3 { 197 reg = <SC_R_I2C_3>; 198 #power-domain-cells = <0>; 199 power-domains = <&pd_dma>; 200 }; 201 pd_dma_lpi2c4: PD_DMA_I2C_4 { 202 reg = <SC_R_I2C_4>; 203 #power-domain-cells = <0>; 204 power-domains = <&pd_dma>; 205 }; 206 pd_dma_lpuart0: PD_DMA_UART0 { 207 reg = <SC_R_UART_0>; 208 #power-domain-cells = <0>; 209 power-domains = <&pd_dma>; 210 wakeup-irq = <345>; 211 }; 212 pd_dma_lpuart1: PD_DMA_UART1 { 213 reg = <SC_R_UART_1>; 214 #power-domain-cells = <0>; 215 power-domains = <&pd_dma>; 216 wakeup-irq = <346>; 217 }; 218 pd_dma_lpuart2: PD_DMA_UART2 { 219 reg = <SC_R_UART_2>; 220 #power-domain-cells = <0>; 221 power-domains = <&pd_dma>; 222 wakeup-irq = <347>; 223 }; 224 pd_dma_lpuart3: PD_DMA_UART3 { 225 reg = <SC_R_UART_3>; 226 #power-domain-cells = <0>; 227 power-domains = <&pd_dma>; 228 wakeup-irq = <348>; 229 }; 230 pd_dma_lpuart4: PD_DMA_UART4 { 231 reg = <SC_R_UART_4>; 232 #power-domain-cells = <0>; 233 power-domains = <&pd_dma>; 234 wakeup-irq = <349>; 235 }; 236 }; 237 }; 238 239 i2c0: i2c@5a800000 { 240 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 241 reg = <0x0 0x5a800000 0x0 0x4000>; 242 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 243 interrupt-parent = <&gic>; 244 clocks = <&clk IMX8QM_I2C0_CLK>, 245 <&clk IMX8QM_I2C0_IPG_CLK>; 246 clock-names = "per", "ipg"; 247 assigned-clocks = <&clk IMX8QM_I2C0_CLK>; 248 assigned-clock-rates = <24000000>; 249 power-domains = <&pd_dma_lpi2c0>; 250 status = "disabled"; 251 }; 252 253 i2c1: i2c@5a810000 { 254 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 255 reg = <0x0 0x5a810000 0x0 0x4000>; 256 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 257 interrupt-parent = <&gic>; 258 clocks = <&clk IMX8QM_I2C1_CLK>, 259 <&clk IMX8QM_I2C1_IPG_CLK>; 260 clock-names = "per", "ipg"; 261 assigned-clocks = <&clk IMX8QM_I2C1_CLK>; 262 assigned-clock-rates = <24000000>; 263 power-domains = <&pd_dma_lpi2c1>; 264 status = "disabled"; 265 }; 266 267 i2c2: i2c@5a820000 { 268 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 269 reg = <0x0 0x5a820000 0x0 0x4000>; 270 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 271 interrupt-parent = <&gic>; 272 clocks = <&clk IMX8QM_I2C2_CLK>, 273 <&clk IMX8QM_I2C2_IPG_CLK>; 274 clock-names = "per", "ipg"; 275 assigned-clocks = <&clk IMX8QM_I2C2_CLK>; 276 assigned-clock-rates = <24000000>; 277 power-domains = <&pd_dma_lpi2c2>; 278 status = "disabled"; 279 }; 280 281 i2c3: i2c@5a830000 { 282 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 283 reg = <0x0 0x5a830000 0x0 0x4000>; 284 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 285 interrupt-parent = <&gic>; 286 clocks = <&clk IMX8QM_I2C3_CLK>, 287 <&clk IMX8QM_I2C3_IPG_CLK>; 288 clock-names = "per", "ipg"; 289 assigned-clocks = <&clk IMX8QM_I2C3_CLK>; 290 assigned-clock-rates = <24000000>; 291 power-domains = <&pd_dma_lpi2c3>; 292 status = "disabled"; 293 }; 294 295 i2c4: i2c@5a840000 { 296 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 297 reg = <0x0 0x5a840000 0x0 0x4000>; 298 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 299 interrupt-parent = <&gic>; 300 clocks = <&clk IMX8QM_I2C4_CLK>, 301 <&clk IMX8QM_I2C4_IPG_CLK>; 302 clock-names = "per", "ipg"; 303 assigned-clocks = <&clk IMX8QM_I2C4_CLK>; 304 assigned-clock-rates = <24000000>; 305 power-domains = <&pd_dma_lpi2c4>; 306 status = "disabled"; 307 }; 308 309 gpio0: gpio@5d080000 { 310 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 311 reg = <0x0 0x5d080000 0x0 0x10000>; 312 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 313 gpio-controller; 314 #gpio-cells = <2>; 315 power-domains = <&pd_lsio_gpio0>; 316 interrupt-controller; 317 #interrupt-cells = <2>; 318 }; 319 320 gpio1: gpio@5d090000 { 321 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 322 reg = <0x0 0x5d090000 0x0 0x10000>; 323 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 324 gpio-controller; 325 #gpio-cells = <2>; 326 power-domains = <&pd_lsio_gpio1>; 327 interrupt-controller; 328 #interrupt-cells = <2>; 329 }; 330 331 gpio2: gpio@5d0a0000 { 332 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 333 reg = <0x0 0x5d0a0000 0x0 0x10000>; 334 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 335 gpio-controller; 336 #gpio-cells = <2>; 337 power-domains = <&pd_lsio_gpio2>; 338 interrupt-controller; 339 #interrupt-cells = <2>; 340 }; 341 342 gpio3: gpio@5d0b0000 { 343 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 344 reg = <0x0 0x5d0b0000 0x0 0x10000>; 345 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 346 gpio-controller; 347 #gpio-cells = <2>; 348 power-domains = <&pd_lsio_gpio3>; 349 interrupt-controller; 350 #interrupt-cells = <2>; 351 }; 352 353 gpio4: gpio@5d0c0000 { 354 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 355 reg = <0x0 0x5d0c0000 0x0 0x10000>; 356 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 357 gpio-controller; 358 #gpio-cells = <2>; 359 power-domains = <&pd_lsio_gpio4>; 360 interrupt-controller; 361 #interrupt-cells = <2>; 362 }; 363 364 gpio5: gpio@5d0d0000 { 365 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 366 reg = <0x0 0x5d0d0000 0x0 0x10000>; 367 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 368 gpio-controller; 369 #gpio-cells = <2>; 370 power-domains = <&pd_lsio_gpio5>; 371 interrupt-controller; 372 #interrupt-cells = <2>; 373 }; 374 375 gpio6: gpio@5d0e0000 { 376 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 377 reg = <0x0 0x5d0e0000 0x0 0x10000>; 378 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 379 gpio-controller; 380 #gpio-cells = <2>; 381 power-domains = <&pd_lsio_gpio6>; 382 interrupt-controller; 383 #interrupt-cells = <2>; 384 }; 385 386 gpio7: gpio@5d0f0000 { 387 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 388 reg = <0x0 0x5d0f0000 0x0 0x10000>; 389 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 390 gpio-controller; 391 #gpio-cells = <2>; 392 power-domains = <&pd_lsio_gpio7>; 393 interrupt-controller; 394 #interrupt-cells = <2>; 395 }; 396 397 lpuart0: serial@5a060000 { 398 compatible = "fsl,imx8qm-lpuart"; 399 reg = <0x0 0x5a060000 0x0 0x1000>; 400 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&clk IMX8QM_UART0_CLK>, 402 <&clk IMX8QM_UART0_IPG_CLK>; 403 clock-names = "per", "ipg"; 404 assigned-clocks = <&clk IMX8QM_UART0_CLK>; 405 assigned-clock-rates = <80000000>; 406 power-domains = <&pd_dma_lpuart0>; 407 status = "disabled"; 408 }; 409 410 lpuart1: serial@5a070000 { 411 compatible = "fsl,imx8qm-lpuart"; 412 reg = <0x0 0x5a070000 0x0 0x1000>; 413 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&clk IMX8QM_UART1_CLK>, 415 <&clk IMX8QM_UART1_IPG_CLK>; 416 clock-names = "per", "ipg"; 417 assigned-clocks = <&clk IMX8QM_UART1_CLK>; 418 assigned-clock-rates = <80000000>; 419 power-domains = <&pd_dma_lpuart1>; 420 status = "disabled"; 421 }; 422 423 lpuart2: serial@5a080000 { 424 compatible = "fsl,imx8qm-lpuart"; 425 reg = <0x0 0x5a080000 0x0 0x1000>; 426 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&clk IMX8QM_UART2_CLK>, 428 <&clk IMX8QM_UART2_IPG_CLK>; 429 clock-names = "per", "ipg"; 430 assigned-clocks = <&clk IMX8QM_UART2_CLK>; 431 assigned-clock-rates = <80000000>; 432 power-domains = <&pd_dma_lpuart2>; 433 status = "disabled"; 434 }; 435 436 lpuart3: serial@5a090000 { 437 compatible = "fsl,imx8qm-lpuart"; 438 reg = <0x0 0x5a090000 0x0 0x1000>; 439 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&clk IMX8QM_UART3_CLK>, 441 <&clk IMX8QM_UART3_IPG_CLK>; 442 clock-names = "per", "ipg"; 443 assigned-clocks = <&clk IMX8QM_UART3_CLK>; 444 assigned-clock-rates = <80000000>; 445 power-domains = <&pd_dma_lpuart3>; 446 status = "disabled"; 447 }; 448 449 lpuart4: serial@5a0a0000 { 450 compatible = "fsl,imx8qm-lpuart"; 451 reg = <0x0 0x5a0a0000 0x0 0x1000>; 452 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&clk IMX8QM_UART4_CLK>, 454 <&clk IMX8QM_UART4_IPG_CLK>; 455 clock-names = "per", "ipg"; 456 assigned-clocks = <&clk IMX8QM_UART4_CLK>; 457 assigned-clock-rates = <80000000>; 458 power-domains = <&pd_dma_lpuart4>; 459 status = "disabled"; 460 }; 461 462 usdhc1: usdhc@5b010000 { 463 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; 464 interrupt-parent = <&gic>; 465 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 466 reg = <0x0 0x5b010000 0x0 0x10000>; 467 clocks = <&clk IMX8QM_SDHC0_IPG_CLK>, 468 <&clk IMX8QM_SDHC0_CLK>, 469 <&clk IMX8QM_CLK_DUMMY>; 470 clock-names = "ipg", "per", "ahb"; 471 assigned-clocks = <&clk IMX8QM_SDHC0_DIV>; 472 assigned-clock-rates = <400000000>; 473 power-domains = <&pd_conn_sdch0>; 474 fsl,tuning-start-tap = <20>; 475 fsl,tuning-step= <2>; 476 status = "disabled"; 477 }; 478 479 usdhc2: usdhc@5b020000 { 480 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; 481 interrupt-parent = <&gic>; 482 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 483 reg = <0x0 0x5b020000 0x0 0x10000>; 484 clocks = <&clk IMX8QM_SDHC1_IPG_CLK>, 485 <&clk IMX8QM_SDHC1_CLK>, 486 <&clk IMX8QM_CLK_DUMMY>; 487 clock-names = "ipg", "per", "ahb"; 488 assigned-clocks = <&clk IMX8QM_SDHC1_DIV>; 489 assigned-clock-rates = <200000000>; 490 power-domains = <&pd_conn_sdch1>; 491 fsl,tuning-start-tap = <20>; 492 fsl,tuning-step= <2>; 493 status = "disabled"; 494 }; 495 496 usdhc3: usdhc@5b030000 { 497 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; 498 interrupt-parent = <&gic>; 499 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 500 reg = <0x0 0x5b030000 0x0 0x10000>; 501 clocks = <&clk IMX8QM_SDHC2_IPG_CLK>, 502 <&clk IMX8QM_SDHC2_CLK>, 503 <&clk IMX8QM_CLK_DUMMY>; 504 clock-names = "ipg", "per", "ahb"; 505 assigned-clocks = <&clk IMX8QM_SDHC2_DIV>; 506 assigned-clock-rates = <200000000>; 507 power-domains = <&pd_conn_sdch2>; 508 status = "disabled"; 509 }; 510 511 fec1: ethernet@5b040000 { 512 compatible = "fsl,imx8qm-fec", "fsl,imx7d-fec"; 513 reg = <0x0 0x5b040000 0x0 0x10000>; 514 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&clk IMX8QM_ENET0_IPG_CLK>, 519 <&clk IMX8QM_ENET0_AHB_CLK>, 520 <&clk IMX8QM_ENET0_RGMII_TX_CLK>, 521 <&clk IMX8QM_ENET0_PTP_CLK>, 522 <&clk IMX8QM_ENET0_TX_CLK>; 523 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", 524 "enet_2x_txclk"; 525 assigned-clocks = <&clk IMX8QM_ENET0_ROOT_DIV>, 526 <&clk IMX8QM_ENET0_REF_DIV>; 527 assigned-clock-rates = <250000000>, <125000000>; 528 fsl,num-tx-queues=<3>; 529 fsl,num-rx-queues=<3>; 530 fsl,wakeup_irq = <0>; 531 power-domains = <&pd_conn_enet0>; 532 status = "disabled"; 533 }; 534 535 fec2: ethernet@5b050000 { 536 compatible = "fsl,imx8qm-fec", "fsl,imx7d-fec"; 537 reg = <0x0 0x5b050000 0x0 0x10000>; 538 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&clk IMX8QM_ENET1_IPG_CLK>, 543 <&clk IMX8QM_ENET1_AHB_CLK>, 544 <&clk IMX8QM_ENET1_RGMII_TX_CLK>, 545 <&clk IMX8QM_ENET1_PTP_CLK>, 546 <&clk IMX8QM_ENET1_TX_CLK>; 547 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", 548 "enet_2x_txclk"; 549 assigned-clocks = <&clk IMX8QM_ENET1_ROOT_DIV>, 550 <&clk IMX8QM_ENET1_REF_DIV>; 551 assigned-clock-rates = <250000000>, <125000000>; 552 fsl,num-tx-queues=<3>; 553 fsl,num-rx-queues=<3>; 554 fsl,wakeup_irq = <0>; 555 power-domains = <&pd_conn_enet1>; 556 status = "disabled"; 557 }; 558}; 559 560&A53_0 { 561 clocks = <&clk IMX8QM_A53_DIV>; 562}; 563