151 	cmd_arg_s cmd_reg;  in hi_mci_control_cclk()  local
163 	cmd_reg.cmd_arg = himci_readl(host->base + MCI_CMD);  in hi_mci_control_cclk()
164 	cmd_reg.cmd_arg &= ~MCI_CMD_MASK;  in hi_mci_control_cclk()
165 	cmd_reg.bits.start_cmd = 1;  in hi_mci_control_cclk()
166 	cmd_reg.bits.card_number = host->port;  in hi_mci_control_cclk()
167 	cmd_reg.bits.update_clk_reg_only = 1;  in hi_mci_control_cclk()
168 	himci_writel(cmd_reg.cmd_arg, host->base + MCI_CMD);  in hi_mci_control_cclk()
178 	cmd_arg_s cmd_reg;  in hi_mci_set_cclk()  local
195 	cmd_reg.cmd_arg = himci_readl(host->base + MCI_CMD);  in hi_mci_set_cclk()
196 	cmd_reg.cmd_arg &= ~MCI_CMD_MASK;  in hi_mci_set_cclk()
197 	cmd_reg.bits.start_cmd = 1;  in hi_mci_set_cclk()
198 	cmd_reg.bits.card_number = host->port;  in hi_mci_set_cclk()
199 	cmd_reg.bits.update_clk_reg_only = 1;  in hi_mci_set_cclk()
200 	himci_writel(cmd_reg.cmd_arg, host->base + MCI_CMD);  in hi_mci_set_cclk()
399 	volatile cmd_arg_s cmd_reg;  in hi_mci_exec_cmd()  local
407 	cmd_reg.cmd_arg = himci_readl(host->base + MCI_CMD);  in hi_mci_exec_cmd()
408 	cmd_reg.cmd_arg &= ~MCI_CMD_MASK;  in hi_mci_exec_cmd()
410 		cmd_reg.bits.data_transfer_expected = 1;  in hi_mci_exec_cmd()
412 			cmd_reg.bits.transfer_mode = 0;  in hi_mci_exec_cmd()
415 			cmd_reg.bits.read_write = 1;  in hi_mci_exec_cmd()
417 			cmd_reg.bits.read_write = 0;  in hi_mci_exec_cmd()
419 		cmd_reg.bits.data_transfer_expected = 0;  in hi_mci_exec_cmd()
420 		cmd_reg.bits.transfer_mode = 0;  in hi_mci_exec_cmd()
421 		cmd_reg.bits.read_write = 0;  in hi_mci_exec_cmd()
424 	cmd_reg.bits.wait_prvdata_complete = 1;  in hi_mci_exec_cmd()
426 	cmd_reg.bits.send_auto_stop = 0;  in hi_mci_exec_cmd()
428 		cmd_reg.bits.send_auto_stop = 1;  in hi_mci_exec_cmd()
431 		cmd_reg.bits.stop_abort_cmd = 1;  in hi_mci_exec_cmd()
432 		cmd_reg.bits.wait_prvdata_complete = 0;  in hi_mci_exec_cmd()
434 		cmd_reg.bits.stop_abort_cmd = 0;  in hi_mci_exec_cmd()
435 		cmd_reg.bits.wait_prvdata_complete = 1;  in hi_mci_exec_cmd()
440 		cmd_reg.bits.response_expect = 0;  in hi_mci_exec_cmd()
441 		cmd_reg.bits.response_length = 0;  in hi_mci_exec_cmd()
442 		cmd_reg.bits.check_response_crc = 0;  in hi_mci_exec_cmd()
446 		cmd_reg.bits.response_expect = 1;  in hi_mci_exec_cmd()
447 		cmd_reg.bits.response_length = 0;  in hi_mci_exec_cmd()
448 		cmd_reg.bits.check_response_crc = 1;  in hi_mci_exec_cmd()
451 		cmd_reg.bits.response_expect = 1;  in hi_mci_exec_cmd()
452 		cmd_reg.bits.response_length = 1;  in hi_mci_exec_cmd()
453 		cmd_reg.bits.check_response_crc = 1;  in hi_mci_exec_cmd()
456 		cmd_reg.bits.response_expect = 1;  in hi_mci_exec_cmd()
457 		cmd_reg.bits.response_length = 0;  in hi_mci_exec_cmd()
458 		cmd_reg.bits.check_response_crc = 0;  in hi_mci_exec_cmd()
468 		cmd_reg.bits.send_initialization = 1;  in hi_mci_exec_cmd()
470 		cmd_reg.bits.send_initialization = 0;  in hi_mci_exec_cmd()
472 	cmd_reg.bits.card_number = host->port;  in hi_mci_exec_cmd()
473 	cmd_reg.bits.cmd_index = cmd->cmdidx;  in hi_mci_exec_cmd()
474 	cmd_reg.bits.send_auto_stop = 0;  in hi_mci_exec_cmd()
475 	cmd_reg.bits.start_cmd = 1;  in hi_mci_exec_cmd()
476 	cmd_reg.bits.update_clk_reg_only = 0;  in hi_mci_exec_cmd()
477 	himci_writel(cmd_reg.cmd_arg, host->base + MCI_CMD);  in hi_mci_exec_cmd()