1 /*
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 *
17 */
18
19 #include <config.h>
20 #include <common.h>
21 #include <mmc.h>
22 #include <part.h>
23 #include <malloc.h>
24 #include <cpu_func.h>
25 //#include <asm/errno.h>
26 #include <asm/io.h>
27 #include <himci_reg.h>
28
29 #include "mmc_private.h"
30 #include "himci.h"
31
32 #define MMC_CS_ERROR_MASK 0xFDFFA080
33
34 /*************************************************************************/
35 #ifdef CONFIG_TARGET_HI3516CV500
36 #include "himci_hi3516cv500.c"
37 #endif
38 #if (defined CONFIG_TARGET_HI3516DV300) || (defined CONFIG_TARGET_HI3516AV300)
39 #include "himci_hi3516dv300.c"
40 #endif
41 #ifdef CONFIG_TARGET_HI3556V200
42 #include "himci_hi3556v200.c"
43 #endif
44 #ifdef CONFIG_TARGET_HI3559V200
45 #include "himci_hi3559v200.c"
46 #endif
47 #ifdef CONFIG_TARGET_HI3562V100
48 #include "himci_hi3559v200.c"
49 #endif
50 #ifdef CONFIG_TARGET_HI3566V100
51 #include "himci_hi3559v200.c"
52 #endif
53 /*************************************************************************/
54
55 //#define TUNING_PROC_DEBUG
56
57 #if HI_MCI_DEBUG
58 int debug_type = HIMCI_DEBUG_TYPE;
59
get_debug_type_string(int type)60 char *get_debug_type_string(int type)
61 {
62 if (type & HIMCI_DEBUG_TYPE_REG)
63 return "REG";
64 else if (type & HIMCI_DEBUG_TYPE_FUN)
65 return "FUN";
66 else if (type & HIMCI_DEBUG_TYPE_CMD)
67 return "CMD";
68 else if (type & HIMCI_DEBUG_TYPE_INFO)
69 return "INFO";
70 else if (type & HIMCI_DEBUG_TYPE_ERR)
71 return "ERR";
72 else
73 return "UNKNOWN";
74 }
75 #endif
76
77 static unsigned int retry_count = MAX_RETRY_COUNT;
78
79 static struct himci_dma_des hi_dma_des[MAX_DMA_DES]
80 __attribute__ ((aligned(512)));
81
82 /* reset MMC host controler */
hi_mci_sys_reset(struct himci_host * host)83 static void hi_mci_sys_reset(struct himci_host *host)
84 {
85 unsigned int tmp_reg;
86 unsigned int time_out;
87
88 HIMCI_DEBUG_FUN("Function Call");
89 HIMCI_ASSERT(host);
90
91 tmp_reg = himci_readl(host->base + MCI_BMOD);
92 tmp_reg |= BMOD_SWR;
93 himci_writel(tmp_reg, host->base + MCI_BMOD);
94
95 time_out = 1000;
96 do {
97 tmp_reg = himci_readl(host->base + MCI_BMOD);
98 udelay(10);
99 } while ((tmp_reg & BMOD_SWR) && time_out--);
100
101 tmp_reg = himci_readl(host->base + MCI_BMOD);
102 tmp_reg |= BURST_16 | BURST_INCR;
103 himci_writel(tmp_reg, host->base + MCI_BMOD);
104
105 tmp_reg = himci_readl(host->base + MCI_CTRL);
106 tmp_reg |= CTRL_RESET | FIFO_RESET | DMA_RESET;
107 himci_writel(tmp_reg, host->base + MCI_CTRL);
108 }
109
hi_mci_ctrl_power(struct himci_host * host,int flag)110 static void hi_mci_ctrl_power(struct himci_host *host, int flag)
111 {
112 int reg_value = 0;
113 HIMCI_DEBUG_FUN("Function Call: flag %d", flag);
114 HIMCI_ASSERT(host);
115
116 if (flag)
117 reg_value = 1 << host->port;
118 else
119 reg_value = 0;
120
121 himci_writel(reg_value, host->base + MCI_PWREN);
122 }
123
124 static int tuning_reset_flag = 0;
125
hi_mci_wait_cmd(struct himci_host * host)126 static int hi_mci_wait_cmd(struct himci_host *host)
127 {
128 unsigned int tmp_reg, wait_retry_count = 0;
129 unsigned int retry_count_cmd = 500;
130
131 HIMCI_DEBUG_FUN("Function Call");
132 HIMCI_ASSERT(host);
133
134 do {
135 tmp_reg = himci_readl(host->base + MCI_CMD);
136 if ((tmp_reg & START_CMD) == 0)
137 return 0;
138 udelay(1);
139 wait_retry_count++;
140 } while (wait_retry_count < retry_count_cmd);
141 if (host->is_tuning)
142 tuning_reset_flag = 1;
143 HIMCI_DEBUG_INFO("CMD send timeout");
144
145 return -1;
146 }
147
hi_mci_control_cclk(struct himci_host * host,unsigned int flag)148 static void hi_mci_control_cclk(struct himci_host *host, unsigned int flag)
149 {
150 unsigned int reg;
151 cmd_arg_s cmd_reg;
152
153 HIMCI_DEBUG_FUN("Function Call: flag %d", flag);
154 HIMCI_ASSERT(host);
155
156 reg = himci_readl(host->base + MCI_CLKENA);
157 if (flag == ENABLE)
158 reg |= CCLK_ENABLE << host->port;
159 else
160 reg &= ~(CCLK_ENABLE << host->port);
161 himci_writel(reg, host->base + MCI_CLKENA);
162
163 cmd_reg.cmd_arg = himci_readl(host->base + MCI_CMD);
164 cmd_reg.cmd_arg &= ~MCI_CMD_MASK;
165 cmd_reg.bits.start_cmd = 1;
166 cmd_reg.bits.card_number = host->port;
167 cmd_reg.bits.update_clk_reg_only = 1;
168 himci_writel(cmd_reg.cmd_arg, host->base + MCI_CMD);
169
170 if (hi_mci_wait_cmd(host) != 0)
171 HIMCI_DEBUG_ERR("Disable or enable CLK is timeout");
172
173 }
174
hi_mci_set_cclk(struct himci_host * host,unsigned int cclk)175 static void hi_mci_set_cclk(struct himci_host *host, unsigned int cclk)
176 {
177 unsigned int reg_value;
178 cmd_arg_s cmd_reg;
179
180 HIMCI_DEBUG_FUN("Function Call: cclk %d", cclk);
181 HIMCI_ASSERT(host);
182 HIMCI_ASSERT(cclk);
183
184 /*set card clk divider value, clk_divider = Fmmcclk/(Fmmc_cclk * 2) */
185 reg_value = 0;
186 if (cclk < MMC_CLK) {
187 reg_value = MMC_CLK / (cclk * 2);
188 if (MMC_CLK % (cclk * 2))
189 reg_value++;
190 if (reg_value > 0xFF)
191 reg_value = 0xFF;
192 }
193 himci_writel(reg_value, host->base + MCI_CLKDIV);
194
195 cmd_reg.cmd_arg = himci_readl(host->base + MCI_CMD);
196 cmd_reg.cmd_arg &= ~MCI_CMD_MASK;
197 cmd_reg.bits.start_cmd = 1;
198 cmd_reg.bits.card_number = host->port;
199 cmd_reg.bits.update_clk_reg_only = 1;
200 himci_writel(cmd_reg.cmd_arg, host->base + MCI_CMD);
201
202 if (hi_mci_wait_cmd(host) != 0)
203 HIMCI_DEBUG_ERR("Set card CLK divider is failed");
204 }
205 /**********************************************
206 *1: card off
207 *0: card on
208 ***********************************************/
hi_mci_sys_card_detect(struct himci_host * host)209 static unsigned int hi_mci_sys_card_detect(struct himci_host *host)
210 {
211 unsigned int card_status;
212
213 card_status = readl((uintptr_t)(host->base + MCI_CDETECT));
214 card_status &= (HIMCI_CARD0 << host->port);
215
216 return card_status >> host->port;
217 }
218
hi_mci_init_card(struct himci_host * host)219 static void hi_mci_init_card(struct himci_host *host)
220 {
221 unsigned int tmp_reg;
222
223 HIMCI_DEBUG_FUN("Function Call");
224 HIMCI_ASSERT(host);
225
226 hi_mci_sys_reset(host);
227
228 /* card reset */
229 himci_writel(~(1<<host->port), host->base + MCI_RESET_N);
230 __udelay(CONFIG_MMC_RESET_LOW_TIMEOUT);
231
232 /* card power off and power on */
233 hi_mci_ctrl_power(host, POWER_OFF);
234 __udelay(CONFIG_MMC_POWER_OFF_TIMEOUT * 1000);
235 hi_mci_ctrl_power(host, POWER_ON);
236 __udelay(CONFIG_MMC_POWER_ON_TIMEROUT * 1000);
237
238 /* card reset cancel */
239 himci_writel(1<<host->port, host->base + MCI_RESET_N);
240 __udelay(CONFIG_MMC_RESET_HIGH_TIMEROUT);
241
242 /* set drv/smpl phase shift */
243 tmp_reg = himci_readl(host->base + MCI_UHS_REG_EXT);
244 tmp_reg &= ~(DRV_PHASE_MASK | SMPL_PHASE_MASK);
245 tmp_reg |= DRV_PHASE_SHIFT | SMPL_PHASE_SHIFT;
246 himci_writel(tmp_reg, host->base + MCI_UHS_REG_EXT);
247
248 /* clear MMC host intr */
249 himci_writel(ALL_INT_CLR, host->base + MCI_RINTSTS);
250
251 /*read write threshold*/
252 himci_writel(RW_THRESHOLD_SIZE, host->base + MMC_CARDTHRCTL);
253
254 /* MASK MMC host intr */
255 tmp_reg = himci_readl(host->base + MCI_INTMASK);
256 tmp_reg &= ~ALL_INT_MASK;
257 himci_writel(tmp_reg, host->base + MCI_INTMASK);
258
259 /* enable inner DMA mode and close intr of MMC host controler */
260 tmp_reg = himci_readl(host->base + MCI_CTRL);
261 tmp_reg &= ~INTR_EN;
262 tmp_reg |= USE_INTERNAL_DMA;
263 himci_writel(tmp_reg, host->base + MCI_CTRL);
264
265 /* enable dma intr */
266 tmp_reg = TI | RI | NI;
267 himci_writel(tmp_reg, host->base + MCI_IDINTEN);
268
269 /* set timeout param */
270 himci_writel(DATA_TIMEOUT | RESPONSE_TIMEOUT, host->base + MCI_TIMEOUT);
271
272 /* set FIFO param */
273 himci_writel(BURST_SIZE | RX_WMARK | TX_WMARK, host->base + MCI_FIFOTH);
274
275 /* set dto fix bypass */
276 tmp_reg = himci_readl(host->base + MCI_GPIO);
277 tmp_reg |= DTO_FIX_BYPASS;
278 himci_writel(tmp_reg, host->base + MCI_GPIO);
279 }
280
hi_mci_idma_start(struct himci_host * host,struct mmc_data * data)281 static void hi_mci_idma_start(struct himci_host *host, struct mmc_data *data)
282 {
283 unsigned int tmp_reg;
284
285 HIMCI_DEBUG_FUN("Function Call");
286 HIMCI_ASSERT(host);
287 HIMCI_ASSERT(data);
288
289 himci_writel((unsigned long)(uintptr_t)host->dma_des, host->base + MCI_DBADDR);
290 HIMCI_DEBUG_INFO("host->dma_des is 0x%x", (unsigned int)host->dma_des);
291
292 tmp_reg = himci_readl(host->base + MCI_BMOD);
293 tmp_reg |= BMOD_DMA_EN;
294 himci_writel(tmp_reg, host->base + MCI_BMOD);
295 }
296
hi_mci_idma_stop(struct himci_host * host)297 static void hi_mci_idma_stop(struct himci_host *host)
298 {
299 unsigned int tmp_reg;
300
301 HIMCI_DEBUG_FUN("Function Call");
302 HIMCI_ASSERT(host);
303
304 tmp_reg = himci_readl(host->base + MCI_BMOD);
305 tmp_reg &= ~BMOD_DMA_EN;
306 himci_writel(tmp_reg, host->base + MCI_BMOD);
307 himci_writel(0, host->base + MCI_BYTCNT);
308 himci_writel(0, host->base + MCI_BLKSIZ);
309 himci_writel(0, host->base + MCI_DBADDR);
310 }
311
hi_mci_idma_reset(struct himci_host * host)312 static void hi_mci_idma_reset(struct himci_host *host)
313 {
314 unsigned int regval;
315
316 regval = himci_readl(host->base + MCI_BMOD);
317 regval |= BMOD_SWR;
318 himci_writel(regval, host->base + MCI_BMOD);
319
320 regval = himci_readl(host->base + MCI_CTRL);
321 regval |= CTRL_RESET | FIFO_RESET | DMA_RESET;
322 himci_writel(regval, host->base + MCI_CTRL);
323
324 udelay(1);
325 himci_writel(ALL_INT_CLR, host->base + MCI_RINTSTS);
326 }
327
hi_mci_setup_data(struct himci_host * host,struct mmc_data * data)328 static int hi_mci_setup_data(struct himci_host *host, struct mmc_data *data)
329 {
330 struct himci_dma_des *des = host->dma_des;
331 unsigned long des_cnt;
332 unsigned long data_size = data->blocks * data->blocksize;
333 unsigned long blk_size = data_size;
334 unsigned long src = (uintptr_t)data->src;
335
336 HIMCI_DEBUG_FUN("Function Call");
337 HIMCI_ASSERT(host);
338 HIMCI_ASSERT(data);
339
340 if (((data_size + 0x1000 - 1) / 0x1000) > MAX_DMA_DES) {
341 HIMCI_ERROR("Data size outside the limit of DMA des, "
342 "data size: 0x%08lx, limit of DMA des: 0x%08x",
343 data_size, 0x1000 * MAX_DMA_DES);
344 return -1;
345 }
346
347 des_cnt = 0;
348 while (data_size) {
349 des[des_cnt].idmac_des_ctrl = DMA_DES_OWN | DMA_DES_NEXT_DES;
350 des[des_cnt].idmac_des_buf_addr = src;
351 des[des_cnt].idmac_des_next_addr =
352 (uintptr_t)(des + des_cnt + 1);
353
354 if (data_size >= 0x1000) {
355 des[des_cnt].idmac_des_buf_size = 0x1000;
356 data_size -= 0x1000;
357 src += 0x1000;
358 } else {
359 des[des_cnt].idmac_des_buf_size = data_size;
360 data_size = 0;
361 }
362
363 HIMCI_DEBUG_INFO("des[%ld] vaddr is 0x%X", des_cnt,
364 (unsigned int)&des[des_cnt]);
365 HIMCI_DEBUG_INFO("des[%ld].idmac_des_ctrl is 0x%X", des_cnt,
366 (unsigned int)des[des_cnt].idmac_des_ctrl);
367 HIMCI_DEBUG_INFO("des[%ld].idmac_des_buf_size is 0x%X",
368 des_cnt,
369 (unsigned int)des[des_cnt].idmac_des_buf_size);
370 HIMCI_DEBUG_INFO("des[%ld].idmac_des_buf_addr 0x%X", des_cnt,
371 (unsigned int)des[des_cnt].idmac_des_buf_addr);
372 HIMCI_DEBUG_INFO("des[%ld].idmac_des_next_addr is 0x%X",
373 des_cnt,
374 (unsigned int)des[des_cnt].idmac_des_next_addr);
375
376 des_cnt++;
377 }
378
379 des[0].idmac_des_ctrl |= DMA_DES_FIRST_DES;
380 des[des_cnt - 1].idmac_des_ctrl |= DMA_DES_LAST_DES;
381 des[des_cnt - 1].idmac_des_next_addr = 0;
382
383 blk_size = ALIGN(blk_size, CONFIG_SYS_CACHELINE_SIZE);
384 des_cnt = ALIGN(des_cnt, CONFIG_SYS_CACHELINE_SIZE);
385 if (data->flags != MMC_DATA_READ){
386 flush_cache((uintptr_t)data->src, blk_size);
387 }
388 else
389 invalidate_dcache_range((uintptr_t)data->dest,(uintptr_t)data->dest + blk_size);
390
391 flush_cache((uintptr_t)host->dma_des, sizeof(struct himci_dma_des)*(unsigned long)des_cnt);
392
393 return 0;
394 }
395
hi_mci_exec_cmd(struct himci_host * host,struct mmc_cmd * cmd,struct mmc_data * data)396 static int hi_mci_exec_cmd(struct himci_host *host, struct mmc_cmd *cmd,
397 struct mmc_data *data)
398 {
399 volatile cmd_arg_s cmd_reg;
400
401 HIMCI_DEBUG_FUN("Function Call");
402 HIMCI_ASSERT(host);
403 HIMCI_ASSERT(cmd);
404
405 himci_writel(cmd->cmdarg, host->base + MCI_CMDARG);
406
407 cmd_reg.cmd_arg = himci_readl(host->base + MCI_CMD);
408 cmd_reg.cmd_arg &= ~MCI_CMD_MASK;
409 if (data) {
410 cmd_reg.bits.data_transfer_expected = 1;
411 if (data->flags & (MMC_DATA_WRITE | MMC_DATA_READ))
412 cmd_reg.bits.transfer_mode = 0;
413
414 if (data->flags & MMC_DATA_WRITE)
415 cmd_reg.bits.read_write = 1;
416 else if (data->flags & MMC_DATA_READ)
417 cmd_reg.bits.read_write = 0;
418 } else {
419 cmd_reg.bits.data_transfer_expected = 0;
420 cmd_reg.bits.transfer_mode = 0;
421 cmd_reg.bits.read_write = 0;
422 }
423
424 cmd_reg.bits.wait_prvdata_complete = 1;
425
426 cmd_reg.bits.send_auto_stop = 0;
427 if (!(host->is_tuning))
428 cmd_reg.bits.send_auto_stop = 1;
429
430 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) {
431 cmd_reg.bits.stop_abort_cmd = 1;
432 cmd_reg.bits.wait_prvdata_complete = 0;
433 } else {
434 cmd_reg.bits.stop_abort_cmd = 0;
435 cmd_reg.bits.wait_prvdata_complete = 1;
436 }
437
438 switch (cmd->resp_type) {
439 case MMC_RSP_NONE:
440 cmd_reg.bits.response_expect = 0;
441 cmd_reg.bits.response_length = 0;
442 cmd_reg.bits.check_response_crc = 0;
443 break;
444 case MMC_RSP_R1:
445 case MMC_RSP_R1b:
446 cmd_reg.bits.response_expect = 1;
447 cmd_reg.bits.response_length = 0;
448 cmd_reg.bits.check_response_crc = 1;
449 break;
450 case MMC_RSP_R2:
451 cmd_reg.bits.response_expect = 1;
452 cmd_reg.bits.response_length = 1;
453 cmd_reg.bits.check_response_crc = 1;
454 break;
455 case MMC_RSP_R3:
456 cmd_reg.bits.response_expect = 1;
457 cmd_reg.bits.response_length = 0;
458 cmd_reg.bits.check_response_crc = 0;
459 break;
460 default:
461 HIMCI_ERROR("unhandled response type %02x", cmd->resp_type);
462 return -1;
463 }
464
465 HIMCI_DEBUG_INFO("Send cmd of card is CMD %d", cmd->cmdidx);
466
467 if (cmd->cmdidx == MMC_CMD_GO_IDLE_STATE)
468 cmd_reg.bits.send_initialization = 1;
469 else
470 cmd_reg.bits.send_initialization = 0;
471
472 cmd_reg.bits.card_number = host->port;
473 cmd_reg.bits.cmd_index = cmd->cmdidx;
474 cmd_reg.bits.send_auto_stop = 0;
475 cmd_reg.bits.start_cmd = 1;
476 cmd_reg.bits.update_clk_reg_only = 0;
477 himci_writel(cmd_reg.cmd_arg, host->base + MCI_CMD);
478
479 if (hi_mci_wait_cmd(host) != 0) {
480 HIMCI_DEBUG_ERR("Send card cmd is failed");
481 return -1;
482 }
483 return 0;
484 }
485
hi_mci_cmd_done(struct himci_host * host,unsigned int stat)486 static int hi_mci_cmd_done(struct himci_host *host, unsigned int stat)
487 {
488 struct mmc_cmd *cmd = host->cmd;
489
490 HIMCI_DEBUG_FUN("Function Call: stat 0x%08x", stat);
491 HIMCI_ASSERT(host);
492 HIMCI_ASSERT(cmd);
493
494 host->cmd = NULL;
495
496 if (cmd->resp_type & MMC_RSP_PRESENT) {
497 if (cmd->resp_type & MMC_RSP_136) {
498 cmd->response[0] = himci_readl(host->base + MCI_RESP3);
499 cmd->response[1] = himci_readl(host->base + MCI_RESP2);
500 cmd->response[2] = himci_readl(host->base + MCI_RESP1);
501 cmd->response[3] = himci_readl(host->base + MCI_RESP0);
502 HIMCI_DEBUG_INFO("CMD Response of card is "
503 "%08x %08x %08x %08x",
504 cmd->response[0], cmd->response[1],
505 cmd->response[2], cmd->response[3]);
506 } else {
507 cmd->response[0] = himci_readl(host->base + MCI_RESP0);
508 HIMCI_DEBUG_INFO("CMD Response of card is %08x",
509 cmd->response[0]);
510 }
511 if (host->mmc->version && !IS_SD(host->mmc)) {
512 if ((cmd->resp_type == MMC_RSP_R1)
513 || (cmd->resp_type == MMC_RSP_R1b)) {
514 if (cmd->response[0] & MMC_CS_ERROR_MASK) {
515 HIMCI_DEBUG_ERR("Card status"
516 " stat = 0x%x"
517 " is card error!",
518 cmd->response[0]);
519 return -1;
520 }
521 }
522 }
523 }
524
525 if (stat & RTO_INT_STATUS) {
526 HIMCI_DEBUG_ERR("CMD status stat = 0x%x is timeout error!",
527 stat);
528 return -ETIMEDOUT;
529 } else if (stat & (RCRC_INT_STATUS | RE_INT_STATUS)) {
530 HIMCI_DEBUG_ERR("CMD status stat = 0x%x is response error!",
531 stat);
532 return -1;
533 }
534 return 0;
535 }
536
hi_mci_data_done(struct himci_host * host,unsigned int stat)537 static void hi_mci_data_done(struct himci_host *host, unsigned int stat)
538 {
539 HIMCI_DEBUG_FUN("Function Call: stat 0x%08x", stat);
540 HIMCI_ASSERT(host);
541
542 if (stat & (HTO_INT_STATUS | DRTO_INT_STATUS)) {
543 HIMCI_DEBUG_ERR("Data status stat = 0x%x is timeout error!",
544 stat);
545 } else if (stat & (EBE_INT_STATUS | SBE_INT_STATUS | FRUN_INT_STATUS
546 | DCRC_INT_STATUS)) {
547 HIMCI_DEBUG_ERR("Data status stat = 0x%x is data error!", stat);
548 }
549 }
550
hi_mci_wait_cmd_complete(struct himci_host * host)551 static int hi_mci_wait_cmd_complete(struct himci_host *host)
552 {
553 unsigned int wait_retry_count = 0;
554 unsigned int reg_data = 0;
555 int ret = 0;
556
557 HIMCI_DEBUG_FUN("Function Call");
558 HIMCI_ASSERT(host);
559
560 do {
561 reg_data = himci_readl(host->base + MCI_RINTSTS);
562 if (reg_data & CD_INT_STATUS) {
563 himci_writel(CD_INT_STATUS | RTO_INT_STATUS
564 | RCRC_INT_STATUS | RE_INT_STATUS,
565 host->base + MCI_RINTSTS);
566 ret = hi_mci_cmd_done(host, reg_data);
567 return ret;
568 }
569 udelay(100);
570 wait_retry_count++;
571 } while (wait_retry_count < retry_count);
572
573 HIMCI_DEBUG_ERR("Wait cmd complete error! irq status is 0x%x",
574 reg_data);
575
576 return -1;
577 }
578
hi_mci_wait_data_complete(struct himci_host * host)579 static int hi_mci_wait_data_complete(struct himci_host *host)
580 {
581 unsigned int wait_retry_count = 0;
582 unsigned int reg_data = 0;
583
584 HIMCI_DEBUG_FUN("Function Call");
585 HIMCI_ASSERT(host);
586
587 do {
588 reg_data = himci_readl(host->base + MCI_RINTSTS);
589 if (reg_data & DTO_INT_STATUS) {
590 hi_mci_idma_stop(host);
591 hi_mci_data_done(host, reg_data);
592 return 0;
593 }
594
595 if (host->is_tuning){
596 if (reg_data & (HTO_INT_STATUS | DRTO_INT_STATUS |
597 EBE_INT_STATUS | SBE_INT_STATUS |
598 FRUN_INT_STATUS | DCRC_INT_STATUS)){
599 hi_mci_idma_stop(host);
600 hi_mci_data_done(host, reg_data);
601 return -1;
602 }
603 }
604 udelay(100);
605 wait_retry_count++;
606 } while (wait_retry_count < retry_count);
607
608 HIMCI_DEBUG_ERR("Wait data complete error! irq status is 0x%x",
609 reg_data);
610
611 return -1;
612 }
613
hi_mci_wait_card_complete(struct himci_host * host)614 static int hi_mci_wait_card_complete(struct himci_host *host)
615 {
616 unsigned int wait_retry_count = 0;
617 unsigned int reg_data = 0;
618
619 HIMCI_DEBUG_FUN("Function Call");
620 HIMCI_ASSERT(host);
621
622 do {
623 reg_data = himci_readl(host->base + MCI_STATUS);
624 if (!(reg_data & DATA_BUSY))
625 return 0;
626 udelay(100);
627 wait_retry_count++;
628 } while (wait_retry_count < retry_count);
629
630 HIMCI_DEBUG_ERR("Wait card complete error! status is 0x%x", reg_data);
631
632 return -1;
633 }
634
hi_mci_request(struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data)635 static int hi_mci_request(struct mmc *mmc, struct mmc_cmd *cmd,
636 struct mmc_data *data)
637 {
638 struct himci_host *host = mmc->priv;
639 unsigned int blk_size;
640 unsigned int tmp_reg, fifo_count = 0;
641 int ret = 0;
642
643 HIMCI_DEBUG_FUN("Function Call");
644 HIMCI_ASSERT(mmc);
645 HIMCI_ASSERT(host);
646 HIMCI_ASSERT(cmd);
647
648 host->cmd = cmd;
649
650 himci_writel(ALL_INT_CLR, host->base + MCI_RINTSTS);
651
652 /* prepare data */
653 if (data) {
654 ret = hi_mci_setup_data(host, data);
655 if (ret) {
656 HIMCI_ERROR("Data setup is error!");
657 goto request_end;
658 }
659
660 blk_size = data->blocks * data->blocksize;
661
662 himci_writel(blk_size, host->base + MCI_BYTCNT);
663 himci_writel(data->blocksize, host->base + MCI_BLKSIZ);
664
665 tmp_reg = himci_readl(host->base + MCI_CTRL);
666 tmp_reg |= FIFO_RESET;
667 himci_writel(tmp_reg, host->base + MCI_CTRL);
668
669 do {
670 tmp_reg = himci_readl(host->base + MCI_CTRL);
671 if (fifo_count > retry_count) {
672 HIMCI_ERROR("FIFO reset error!");
673 break;
674 }
675 fifo_count++;
676 } while (tmp_reg & FIFO_RESET);
677
678 /* start DMA */
679 hi_mci_idma_start(host, data);
680 } else {
681 himci_writel(0, host->base + MCI_BYTCNT);
682 himci_writel(0, host->base + MCI_BLKSIZ);
683 }
684
685 /* send command */
686 ret = hi_mci_exec_cmd(host, cmd, data);
687 if (ret) {
688 HIMCI_ERROR("CMD execute is error!");
689 goto request_end;
690 }
691
692 /* wait command send complete */
693 ret = hi_mci_wait_cmd_complete(host);
694 if (ret)
695 goto request_end;
696
697 /* start data transfer */
698 if (data) {
699 /* wait data transfer complete */
700 ret = hi_mci_wait_data_complete(host);
701 if (ret)
702 goto request_end;
703
704 /* wait card complete */
705 ret = hi_mci_wait_card_complete(host);
706 if (ret)
707 goto request_end;
708 }
709
710 if (cmd->resp_type & MMC_RSP_BUSY) {
711 /* wait card complete */
712 ret = hi_mci_wait_card_complete(host);
713 if (ret)
714 goto request_end;
715 }
716 request_end:
717 /* clear MMC host intr */
718 himci_writel(ALL_INT_CLR, host->base + MCI_RINTSTS);
719 return ret;
720 }
721
hi_mci_set_ios(struct mmc * mmc)722 static int hi_mci_set_ios(struct mmc *mmc)
723 {
724 struct himci_host *host = mmc->priv;
725 unsigned int tmp_reg;
726
727 HIMCI_DEBUG_FUN("Function Call");
728 HIMCI_ASSERT(mmc);
729 HIMCI_ASSERT(host);
730
731 if (mmc->clock) {
732 hi_mci_control_cclk(host, DISABLE);
733 hi_mci_set_cclk(host, mmc->clock);
734 hi_mci_control_cclk(host, ENABLE);
735 } else {
736 hi_mci_control_cclk(host, DISABLE);
737 }
738
739 /* set bus_width */
740 HIMCI_DEBUG_INFO("ios->bus_width = %d", mmc->bus_width);
741
742 tmp_reg = himci_readl(host->base + MCI_CTYPE);
743 tmp_reg &= ~CARD_WIDTH_MASK;
744
745 if (mmc->bus_width == 8)
746 tmp_reg |= (CARD_WIDTH_8BIT<<host->port);
747 else if (mmc->bus_width == 4)
748 tmp_reg |= (CARD_WIDTH_4BIT<<host->port);
749 else
750 tmp_reg |= (CARD_WIDTH_1BIT<<host->port);
751
752 himci_writel(tmp_reg, host->base + MCI_CTYPE);
753
754 hi_mci_set_drv_cap(mmc, 0);
755 hi_mci_set_default_phase(mmc);
756
757 return 0;
758 }
759
hi_mci_init(struct mmc * mmc)760 static int hi_mci_init(struct mmc *mmc)
761 {
762 struct himci_host *host = mmc->priv;
763
764 HIMCI_DEBUG_FUN("Function Call");
765
766 hi_mci_init_card(host);
767
768 return 0;
769 }
770
hi_mci_card_busy(struct mmc * mmc)771 static int hi_mci_card_busy(struct mmc *mmc)
772 {
773 struct himci_host *host = mmc->priv;
774 unsigned int regval;
775
776 HIMCI_DEBUG_FUN("Function Call");
777 HIMCI_ASSERT(mmc);
778 HIMCI_ASSERT(host);
779
780 regval = himci_readl(host->base + MCI_STATUS);
781 regval &= DATA_BUSY;
782
783 return regval;
784 }
785
hi_mci_edge_tuning_enable(struct himci_host * host)786 static void hi_mci_edge_tuning_enable(struct himci_host *host)
787 {
788 unsigned int val;
789
790 himci_writel(0x80001, 0x1201014c);
791
792 val = himci_readl(host->base + MCI_TUNING_CTRL);
793 val |= HW_TUNING_EN;
794 himci_writel(val, host->base + MCI_TUNING_CTRL);
795 }
796
hi_mci_edge_tuning_disable(struct himci_host * host)797 static void hi_mci_edge_tuning_disable(struct himci_host *host)
798 {
799 unsigned int val;
800
801 val = himci_readl(0x1201014c);
802 val |= (1 << 16);
803 himci_writel(val, 0x1201014c);
804
805 val = himci_readl(host->base + MCI_TUNING_CTRL);
806 val &= ~HW_TUNING_EN;
807 himci_writel(val, host->base + MCI_TUNING_CTRL);
808 }
809
hi_mci_set_sap_phase(struct himci_host * host,unsigned int phase)810 static void hi_mci_set_sap_phase(struct himci_host *host, unsigned int phase)
811 {
812 unsigned int reg_value;
813
814 reg_value = himci_readl(host->base + MCI_UHS_REG_EXT);
815 reg_value &= ~CLK_SMPL_PHS_MASK;
816 reg_value |= (phase << CLK_SMPL_PHS_SHIFT);
817 himci_writel(reg_value, host->base + MCI_UHS_REG_EXT);
818 }
819
hi_mci_send_stop(struct mmc * mmc)820 static int hi_mci_send_stop(struct mmc * mmc)
821 {
822 struct mmc_cmd cmd = {0};
823 int err;
824
825 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
826 cmd.resp_type = MMC_RSP_R1;
827
828 err = mmc_send_cmd(mmc, &cmd, NULL);
829 return err;
830 }
831
hi_mci_send_tuning(struct mmc * mmc,unsigned int opcode)832 static int hi_mci_send_tuning(struct mmc * mmc, unsigned int opcode)
833 {
834 int err = 0;
835 unsigned int status = 1000;
836 struct himci_host *host = mmc->priv;
837 /* fix a problem that When the I/O voltage is increased to 1.89 V or 1.91V
838 * at high and low temperatures, the system is suspended during the reboot test.
839 */
840 unsigned cmd_count = 1000;
841
842 hi_mci_control_cclk(host, DISABLE);
843 tuning_retry:
844 hi_mci_idma_reset(host);
845 himci_writel(ALL_INT_CLR, host->base + MCI_RINTSTS);
846 hi_mci_control_cclk(host, ENABLE);
847 if (tuning_reset_flag == 1){
848 tuning_reset_flag = 0;
849 cmd_count--;
850 if (cmd_count == 0){
851 printf("BUG_ON:controller reset is failed!!!\n");
852 return -EINVAL;
853 }
854 goto tuning_retry;
855 }
856 err = mmc_send_tuning(mmc, opcode, NULL);
857 hi_mci_send_stop(mmc);
858 mmc_send_status(mmc ,&status);
859 return err;
860 }
861
hi_mci_get_sap_dll_taps(void)862 static unsigned int hi_mci_get_sap_dll_taps(void)
863 {
864 unsigned int regval = 0;
865
866 regval = himci_readl(0x12010150);
867
868 return (regval & 0xff);
869 }
870
hi_mci_set_dll_element(unsigned int element)871 static void hi_mci_set_dll_element(unsigned int element)
872 {
873 unsigned int regval;
874
875 regval = himci_readl(0x1201014c);
876 regval &=~(0xFF << 8);
877 regval |= (element << 8);
878 himci_writel(regval, 0x1201014c);
879
880 }
881
hi_mci_tuning_feedback(struct mmc * mmc)882 static void hi_mci_tuning_feedback(struct mmc * mmc)
883 {
884 struct himci_host *host = mmc->priv;
885
886 hi_mci_control_cclk(host, DISABLE);
887 mdelay(1);
888 hi_mci_sys_reset(host);
889 mdelay(1);
890 himci_writel(ALL_INT_CLR, host->base + MCI_RINTSTS);
891 hi_mci_control_cclk(host, ENABLE);
892 mdelay(1);
893 }
894
895 /*********************************************
896 *********************************************
897 EdgeMode A:
898 |<---- totalphases(ele) ---->|
899 _____________
900 ______|||||||||||||||_______
901 edge_p2f edge_f2p
902 (endp) (startp)
903
904 EdgeMode B:
905 |<---- totalphases(ele) ---->|
906 ________ _________
907 ||||||||||_________|||||||||||
908 edge_f2p edge_p2f
909 (startp) (endp)
910
911 BestPhase:
912 if(endp < startp)
913 endp = endp + totalphases;
914 Best = ((startp + endp) / 2) % totalphases
915 **********************************************
916 **********************************************/
hi_mci_edgedll_mode_tuning(struct mmc * mmc,unsigned int opcode,int edge_p2f,int edge_f2p)917 static int hi_mci_edgedll_mode_tuning(struct mmc *mmc, unsigned int opcode, int edge_p2f, int edge_f2p)
918 {
919 unsigned int index;
920 unsigned int found = 0;
921 unsigned int startp =-1, endp = -1;
922 unsigned int startp_init = 0, endp_init = 0;
923 unsigned int phaseoffset = 0, totalphases = 0;
924 unsigned short ele,start_ele, phase_dll_elements;
925 unsigned char mdly_tap_flag = 0;
926 int prev_err = 0, err = 0;
927 struct himci_host *host = mmc->priv;
928 unsigned int phase_num = HIMCI_PHASE_SCALE;
929
930 mdly_tap_flag = hi_mci_get_sap_dll_taps();
931 phase_dll_elements = mdly_tap_flag / HIMCI_PHASE_SCALE;
932 totalphases = phase_dll_elements * phase_num;
933 startp_init = edge_f2p * phase_dll_elements;
934 endp_init = edge_p2f * phase_dll_elements;
935 startp = startp_init;
936 endp = endp_init;
937
938 found = 1;
939 start_ele = 2;
940
941 /*Note: edgedll tuning must from edge_p2f to edge_f2p*/
942 if(edge_f2p >= edge_p2f) {
943 phaseoffset = edge_p2f * phase_dll_elements;
944 for (index = edge_p2f; index < edge_f2p; index++) {
945 /* set phase shift */
946 hi_mci_set_sap_phase(host, index);
947
948 for (ele = start_ele; ele <= phase_dll_elements ; ele++) {
949 hi_mci_set_dll_element(ele);
950 err = hi_mci_send_tuning(mmc, opcode);
951 if (!err)
952 found = 1;
953
954 if (!prev_err && err && (endp == endp_init))
955 endp = phaseoffset + ele;
956
957 if (err)
958 startp = phaseoffset + ele;
959
960 #ifdef TUNING_PROC_DEBUG
961 printf("\tphase:%01u ele:%02u st:%03u end:%03u error:%d\n", index, ele, startp, endp, err);
962 #endif
963
964 prev_err = err;
965 err = 0;
966 }
967 phaseoffset += phase_dll_elements;
968 }
969 } else {
970
971 phaseoffset = edge_p2f * phase_dll_elements;
972 for (index = edge_p2f ; index < phase_num ; index++) {
973 /* set phase shift */
974 hi_mci_set_sap_phase(host, index);
975 for (ele = start_ele; ele <= phase_dll_elements ; ele++) {
976 hi_mci_set_dll_element(ele);
977 err = hi_mci_send_tuning(mmc, opcode);
978
979 if (!err)
980 found = 1;
981
982 if (!prev_err && err && (endp == endp_init))
983 endp = phaseoffset + ele;
984
985 if (err)
986 startp = phaseoffset + ele;
987
988 #ifdef TUNING_PROC_DEBUG
989 printf("\tphase:%02u ele:%02u st:%03u end:%03u error:%d\n", index, ele, startp, endp, err);
990 #endif
991
992 prev_err = err;
993 err = 0;
994 }
995 phaseoffset += phase_dll_elements;
996 }
997
998 phaseoffset = 0;
999 for (index = 0; index < edge_f2p; index++) {
1000 /* set phase shift */
1001 hi_mci_set_sap_phase(host, index);
1002 for (ele = start_ele; ele <= phase_dll_elements ; ele++) {
1003 hi_mci_set_dll_element(ele);
1004
1005 err = hi_mci_send_tuning(mmc, opcode);
1006 if (!err)
1007 found = 1;
1008
1009 if (!prev_err && err && (endp == endp_init))
1010 endp = phaseoffset + ele;
1011
1012 if (err)
1013 startp = phaseoffset + ele;
1014
1015 #ifdef TUNING_PROC_DEBUG
1016 printf("\tphase:%02u ele:%02u st:%03u end:%03u error:%d\n", index, ele, startp, endp, err);
1017 #endif
1018
1019 prev_err = err;
1020 err = 0;
1021 }
1022 phaseoffset += phase_dll_elements;
1023 }
1024 }
1025
1026 if (found) {
1027 printf("scan elemnts: startp:%u endp:%u\n", startp, endp);
1028
1029 if (endp <= startp)
1030 endp += totalphases;
1031
1032 phaseoffset = (( startp + endp ) / 2) % totalphases;
1033 index = (phaseoffset / phase_dll_elements);
1034 ele = (phaseoffset % phase_dll_elements);
1035 ele = ((ele > start_ele)?ele:start_ele);
1036
1037 hi_mci_set_sap_phase(host, index);
1038 hi_mci_set_dll_element(ele);
1039
1040 printf("Tuning SampleClock. mix set phase:[%02u/%02u] ele:[%0ud/%02u]\n",
1041 index, (phase_num - 1), ele, phase_dll_elements);
1042 himci_writel(ALL_INT_CLR, host->base + MCI_RINTSTS);
1043 return 0;
1044 }
1045 printf( "No valid phase shift! use default\n");
1046 return -1;
1047 }
1048
hi_mci_execute_mix_mode_tuning(struct mmc * mmc,unsigned int opcode)1049 static int hi_mci_execute_mix_mode_tuning(struct mmc * mmc, unsigned int opcode)
1050 {
1051 struct himci_host *host = mmc->priv;
1052 unsigned int index, regval;
1053 unsigned int found = 0,prefound = 0;
1054 unsigned int edge_p2f, edge_f2p;
1055 unsigned int edge_num = 0;
1056 int err;
1057 unsigned int phase_num = HIMCI_PHASE_SCALE;
1058
1059 hi_mci_edge_tuning_enable(host);
1060
1061 edge_p2f = 0;
1062 edge_f2p = phase_num;
1063
1064 for (index = 0; index < phase_num; index++) {
1065
1066 /* set phase shift */
1067 hi_mci_set_sap_phase(host, index);
1068 err = hi_mci_send_tuning(mmc, opcode);
1069 if (!err) {
1070 regval = himci_readl(host->base + MCI_TUNING_CTRL);
1071 found = ((regval & FOUND_EDGE) == FOUND_EDGE);
1072 } else {
1073 found = 1;
1074 }
1075
1076 if (found)
1077 edge_num++;
1078
1079 if (prefound && !found)
1080 edge_f2p = index;
1081 else if (!prefound && found)
1082 edge_p2f = index;
1083
1084 #ifdef TUNING_PROC_DEBUG
1085 printf("\tphase:%02u found:%02u p2f:%u f2p:%u error:%d\n",
1086 index, found, edge_p2f, edge_f2p, err);
1087 #endif
1088
1089 if ((edge_p2f != 0) && (edge_f2p != phase_num))
1090 break;
1091
1092 prefound = found;
1093 found = 0;
1094 }
1095
1096 if ((edge_p2f == 0) && (edge_f2p == phase_num)) {
1097 printf("unfound correct edge! check your config is correct!!\n");
1098 return -1;
1099 }
1100
1101 printf("scan edges:%u p2f:%u f2p:%u\n", edge_num, edge_p2f, edge_f2p);
1102
1103 if (edge_f2p < edge_p2f)
1104 index = ((edge_f2p + edge_p2f) / 2) % phase_num;
1105 else
1106 index = ((edge_f2p + phase_num + edge_p2f) / 2) % phase_num;
1107 printf("mix set temp-phase %u\n", index);
1108 hi_mci_set_sap_phase(host, index);
1109 err = hi_mci_send_tuning(mmc,opcode);
1110
1111 hi_mci_edge_tuning_disable(host);
1112 err = hi_mci_edgedll_mode_tuning(mmc, opcode, edge_p2f, edge_f2p);
1113
1114 return err;
1115 }
hi_mci_execute_tuning(struct mmc * mmc,unsigned int opcode)1116 static int hi_mci_execute_tuning(struct mmc *mmc, unsigned int opcode)
1117 {
1118 struct himci_host *host = mmc->priv;
1119 int err;
1120
1121 host->is_tuning = 1;
1122 err = hi_mci_execute_mix_mode_tuning(mmc, opcode);
1123 hi_mci_tuning_feedback(mmc);
1124 if (!err)
1125 err = hi_mci_send_tuning(mmc, opcode);
1126
1127 host->is_tuning = 0;
1128 return err;
1129 }
1130
himci_shutdown(void)1131 static void himci_shutdown(void)
1132 {
1133 unsigned long base_addr;
1134 unsigned int value;
1135
1136 base_addr = EMMC_REG_BASE;
1137
1138 value = readl((uintptr_t)(base_addr + MCI_CTRL));
1139 value |= CTRL_RESET | FIFO_RESET | DMA_RESET;
1140
1141 writel(value, (uintptr_t)(base_addr + MCI_CTRL));
1142 writel(POWER_OFF, (uintptr_t)(base_addr + MCI_PWREN));
1143
1144 /* Delay 100ms, waiting for the eMMC device power off*/
1145 udelay(100 * 1000);
1146 }
1147
print_ext_csd(struct mmc * mmc)1148 void print_ext_csd(struct mmc *mmc)
1149 {
1150 unsigned char ext_csd[512];
1151 unsigned int tmp;
1152
1153 HIMCI_DEBUG_FUN("Function Call");
1154
1155 int err = mmc_send_ext_csd(mmc, ext_csd);
1156 if (err) {
1157 HIMCI_ERROR("Check est_csd error!");
1158 return;
1159 }
1160
1161 HIMCI_DEBUG_INFO("Extended CSD register:");
1162 for (tmp = 0; tmp < 512; tmp += 8)
1163 HIMCI_DEBUG_INFO
1164 ("%03d: %02x %02x %02x %02x %02x %02x %02x %02x", tmp,
1165 ext_csd[tmp], ext_csd[tmp + 1], ext_csd[tmp + 2],
1166 ext_csd[tmp + 3], ext_csd[tmp + 4], ext_csd[tmp + 5],
1167 ext_csd[tmp + 6], ext_csd[tmp + 7]);
1168 }
1169
print_mmcinfo(struct mmc * mmc)1170 static void print_mmcinfo(struct mmc *mmc)
1171 {
1172 HIMCI_DEBUG_FUN("Function Call");
1173
1174 printf("MMC/SD Card:\n");
1175 printf(" MID: 0x%x\n", mmc->cid[0] >> 24);
1176 printf(" Read Block: %d Bytes\n", mmc->read_bl_len);
1177 printf(" Write Block: %d Bytes\n", mmc->write_bl_len);
1178 printf(" Chip Size: %s Bytes (%s)\n",
1179 ultohstr(mmc->capacity),
1180 mmc->high_capacity ? "High Capacity" : "Low Capacity");
1181 printf(" Name: \"%c%c%c%c%c\"\n",
1182 mmc->cid[0] & 0xff,
1183 (mmc->cid[1] >> 24),
1184 (mmc->cid[1] >> 16) & 0xff,
1185 (mmc->cid[1] >> 8) & 0xff,
1186 mmc->cid[1] & 0xff);
1187
1188 printf(" Chip Type: %s\n"
1189 " Version: %d.%d\n",
1190 IS_SD(mmc) ? "SD" : "MMC",
1191 (mmc->version >> 4) & 0xf, mmc->version & 0xf);
1192
1193 printf(" Speed: %sHz\n", ultohstr(mmc->clock));
1194 printf(" Bus Width: %dbit\n", mmc->bus_width);
1195 }
1196
himci_probe(int dev_num)1197 int himci_probe(int dev_num)
1198 {
1199 struct mmc *mmc = find_mmc_device(dev_num);
1200 int err = 0;
1201
1202 puts("\nEMMC/MMC/SD controller initialization.\n");
1203
1204 if (!mmc) {
1205 printf("mmc device not found!!\n");
1206 return -1;
1207 }
1208
1209 err = mmc_init(mmc);
1210 if (err) {
1211 printf("mmc_init failed! err:%d\n", err);
1212 return err;
1213 }
1214
1215 print_mmcinfo(mmc);
1216 #ifdef CONFIG_SUPPORT_EMMC_BOOT
1217 if (!IS_SD(mmc))
1218 return mmc_set_boot_config(mmc);
1219 #endif
1220 return 0;
1221 }
1222
1223 static const struct mmc_ops himci_ops = {
1224 .send_cmd = hi_mci_request,
1225 .set_ios = hi_mci_set_ios,
1226 .init = hi_mci_init,
1227 .execute_tuning = hi_mci_execute_tuning,
1228 .card_busy = hi_mci_card_busy,
1229 };
1230
himci_setup_cfg(struct mmc_config * cfg,struct himci_host * host,unsigned int max_clk,unsigned int min_clk)1231 static void himci_setup_cfg(struct mmc_config *cfg, struct himci_host *host,
1232 unsigned int max_clk, unsigned int min_clk)
1233 {
1234 cfg->name = host->name;
1235 cfg->f_min = min_clk;
1236 cfg->f_max = max_clk;
1237
1238 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1239
1240 cfg->host_caps |= MMC_MODE_4BIT;
1241 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HS200;
1242 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1243
1244 cfg->ops = &himci_ops;
1245 }
1246
add_himci(struct himci_host * host,unsigned int max_clk,unsigned int min_clk)1247 int add_himci(struct himci_host *host, unsigned int max_clk, unsigned int min_clk)
1248 {
1249 himci_setup_cfg(&host->cfg, host, max_clk, min_clk);
1250
1251 host->mmc = mmc_create(&host->cfg, host);
1252 if (host->mmc == NULL)
1253 return -1;
1254
1255 add_shutdown(himci_shutdown);
1256 return 0;
1257 }
1258
himci_add_port(int index,unsigned int reg_base,unsigned int freq)1259 int himci_add_port(int index, unsigned int reg_base, unsigned int freq)
1260 {
1261 struct himci_host *host = NULL;
1262 unsigned int regval;
1263
1264 HIMCI_DEBUG_FUN("Function Call");
1265 hi_mci_sys_init(index, freq);
1266
1267 /* check controller version. */
1268 regval = himci_readl(reg_base + MCI_VERID);
1269 if ((regval != MCI_VERID_VALUE) && (regval != MCI_VERID_VALUE2)
1270 && (regval != MCI_VERID_VALUE3)) {
1271 printf("MMC/SD/EMMC controller version incorrect.\n");
1272 return -ENODEV;
1273 }
1274
1275 host = calloc(1, sizeof(struct himci_host));
1276 if (!host) {
1277 puts("host malloc fail!\n");
1278 return -ENOMEM;
1279 }
1280
1281 host->name = "himci";
1282 host->dev_id = index;
1283 host->base = (unsigned long)reg_base;
1284 host->dma_des = hi_dma_des;
1285 host->card_status = hi_mci_sys_card_detect(host);
1286 host->port = 0;
1287 host->is_tuning = 0;
1288 return add_himci(host, freq, MMC_CCLK_MIN);
1289 }
1290