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/kernel/linux/linux-5.10/drivers/staging/media/ipu3/
Dipu3-tables.c1 // SPDX-License-Identifier: GPL-2.0
4 #include "ipu3-tables.h"
6 #define X 0 /* Don't care value */
10 /* Scale factor 32 / (32 + 0) = 1 */
12 .even = { { 0, 0, 64, 6, 0, 0, 0 } },
13 .odd = { { 0, 0, 64, 6, 0, 0, 0 } } },
15 .even = { { 0, 0, 64, 6, 0, 0, 0 } },
16 .odd = { { 0, 0, 64, 6, 0, 0, 0 } } },
17 .ptrn_arr = { { 0x3 } },
19 .hor_ds_en = 0,
[all …]
/kernel/linux/linux-5.10/drivers/isdn/mISDN/
Ddsp_audio.c20 /* ulaw[unsigned char] -> signed 16-bit */
22 /* alaw[unsigned char] -> signed 16-bit */
28 /* signed 16-bit -> law */
32 /* alaw -> ulaw */
34 /* ulaw -> alaw */
43 #define AMI_MASK 0x55
51 0xFF, 0x1FF, 0x3FF, 0x7FF, 0xFFF, 0x1FFF, 0x3FFF, 0x7FFF in linear2alaw()
55 if (pcm_val >= 0) { in linear2alaw()
56 /* Sign (7th) bit = 1 */ in linear2alaw()
57 mask = AMI_MASK | 0x80; in linear2alaw()
[all …]
/kernel/linux/linux-4.19/drivers/isdn/mISDN/
Ddsp_audio.c20 /* ulaw[unsigned char] -> signed 16-bit */
22 /* alaw[unsigned char] -> signed 16-bit */
28 /* signed 16-bit -> law */
32 /* alaw -> ulaw */
34 /* ulaw -> alaw */
43 #define AMI_MASK 0x55
51 0xFF, 0x1FF, 0x3FF, 0x7FF, 0xFFF, 0x1FFF, 0x3FFF, 0x7FFF in linear2alaw()
55 if (pcm_val >= 0) { in linear2alaw()
56 /* Sign (7th) bit = 1 */ in linear2alaw()
57 mask = AMI_MASK | 0x80; in linear2alaw()
[all …]
/kernel/linux/linux-5.10/drivers/staging/netlogic/
Dxlr_net.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
3 * Copyright (c) 2003-2012 Broadcom Corporation
9 #define MAC_SPACING 0x400
10 #define XGMAC_SPACING 0x400
12 /* PE-MCXMAC register and bit field definitions */
13 #define R_MAC_CONFIG_1 0x00
26 #define O_MAC_CONFIG_1__txen 0
27 #define R_MAC_CONFIG_2 0x01
35 #define O_MAC_CONFIG_2__fulld 0
36 #define R_IPG_IFG 0x02
[all …]
/kernel/linux/linux-5.10/Documentation/userspace-api/media/v4l/
Dpixfmt-srggb10-ipu3.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-pix-fmt-ipu3-sbggr10:
4 .. _v4l2-pix-fmt-ipu3-sgbrg10:
5 .. _v4l2-pix-fmt-ipu3-sgrbg10:
6 .. _v4l2-pix-fmt-ipu3-srggb10:
12 10-bit Bayer formats
22 In other respects this format is similar to :ref:`V4L2-PIX-FMT-SRGGB10`.
30 .. flat-table::
32 * - start + 0:
33 - B\ :sub:`0000low`
[all …]
/kernel/linux/linux-4.19/Documentation/media/uapi/v4l/
Dpixfmt-srggb10-ipu3.rst1 .. -*- coding: utf-8; mode: rst -*-
3 .. _v4l2-pix-fmt-ipu3-sbggr10:
4 .. _v4l2-pix-fmt-ipu3-sgbrg10:
5 .. _v4l2-pix-fmt-ipu3-sgrbg10:
6 .. _v4l2-pix-fmt-ipu3-srggb10:
12 10-bit Bayer formats
22 In other respects this format is similar to :ref:`V4L2-PIX-FMT-SRGGB10`.
30 .. flat-table::
32 * - start + 0:
33 - B\ :sub:`0000low`
[all …]
/kernel/linux/linux-4.19/drivers/isdn/i4l/
Disdn_audio.c5 * Copyright 1994-1999 by Fritz Elfert (fritz@isdn4linux.de)
22 * Misc. lookup-tables.
25 /* ulaw -> signed 16-bit */
28 0x8284, 0x8684, 0x8a84, 0x8e84, 0x9284, 0x9684, 0x9a84, 0x9e84,
29 0xa284, 0xa684, 0xaa84, 0xae84, 0xb284, 0xb684, 0xba84, 0xbe84,
30 0xc184, 0xc384, 0xc584, 0xc784, 0xc984, 0xcb84, 0xcd84, 0xcf84,
31 0xd184, 0xd384, 0xd584, 0xd784, 0xd984, 0xdb84, 0xdd84, 0xdf84,
32 0xe104, 0xe204, 0xe304, 0xe404, 0xe504, 0xe604, 0xe704, 0xe804,
33 0xe904, 0xea04, 0xeb04, 0xec04, 0xed04, 0xee04, 0xef04, 0xf004,
34 0xf0c4, 0xf144, 0xf1c4, 0xf244, 0xf2c4, 0xf344, 0xf3c4, 0xf444,
[all …]
/kernel/linux/linux-5.10/sound/soc/codecs/
Dwm2200.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * wm2200.h - WM2200 audio codec interface
14 #define WM2200_CLKSRC_MCLK1 0
19 #define WM2200_FLL_SRC_MCLK1 0
26 #define WM2200_SOFTWARE_RESET 0x00
27 #define WM2200_DEVICE_REVISION 0x01
28 #define WM2200_TONE_GENERATOR_1 0x0B
29 #define WM2200_CLOCKING_3 0x102
30 #define WM2200_CLOCKING_4 0x103
31 #define WM2200_FLL_CONTROL_1 0x111
[all …]
/kernel/linux/linux-4.19/sound/soc/codecs/
Dwm2200.h2 * wm2200.h - WM2200 audio codec interface
18 #define WM2200_CLKSRC_MCLK1 0
23 #define WM2200_FLL_SRC_MCLK1 0
30 #define WM2200_SOFTWARE_RESET 0x00
31 #define WM2200_DEVICE_REVISION 0x01
32 #define WM2200_TONE_GENERATOR_1 0x0B
33 #define WM2200_CLOCKING_3 0x102
34 #define WM2200_CLOCKING_4 0x103
35 #define WM2200_FLL_CONTROL_1 0x111
36 #define WM2200_FLL_CONTROL_2 0x112
[all …]
/kernel/linux/linux-5.10/drivers/video/fbdev/via/
Dhw.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
22 #define VIA_LDVP0 0x00000001
23 #define VIA_LDVP1 0x00000002
24 #define VIA_DVP0 0x00000004
25 #define VIA_CRT 0x00000010
26 #define VIA_DVP1 0x00000020
27 #define VIA_LVDS1 0x00000040
28 #define VIA_LVDS2 0x00000080
[all …]
/kernel/linux/linux-5.10/arch/mips/boot/dts/loongson/
Dls7a-pch.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 compatible = "simple-bus";
6 #address-cells = <2>;
7 #size-cells = <2>;
8 ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
9 0 0x20000000 0 0x20000000 0 0x10000000
10 0 0x40000000 0 0x40000000 0 0x40000000 /* PCI MEM */
11 0xe00 0x00000000 0xe00 0x00000000 0x100 0x0000000>;
13 pic: interrupt-controller@10000000 {
14 compatible = "loongson,pch-pic-1.0";
[all …]
/kernel/linux/linux-4.19/drivers/video/fbdev/via/
Dhw.h2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 #define VIA_LDVP0 0x00000001
37 #define VIA_LDVP1 0x00000002
38 #define VIA_DVP0 0x00000004
39 #define VIA_CRT 0x00000010
40 #define VIA_DVP1 0x00000020
41 #define VIA_LVDS1 0x00000040
42 #define VIA_LVDS2 0x00000080
[all …]
/kernel/linux/linux-4.19/arch/sh/include/mach-common/mach/
Dsh2007.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #define CS5BCR 0xff802050
6 #define CS5WCR 0xff802058
7 #define CS5PCR 0xff802070
14 #define PCMCIA_ATA 0
20 #define PCMCIA_ATTR16 7
22 #define TYPE_SRAM 0
25 /* write-read/write-write delay (0-7:0,1,2,3,4,5,6,7) */
26 #define IWW5 0
28 /* different area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
[all …]
/kernel/linux/linux-5.10/arch/sh/include/mach-common/mach/
Dsh2007.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #define CS5BCR 0xff802050
6 #define CS5WCR 0xff802058
7 #define CS5PCR 0xff802070
14 #define PCMCIA_ATA 0
20 #define PCMCIA_ATTR16 7
22 #define TYPE_SRAM 0
25 /* write-read/write-write delay (0-7:0,1,2,3,4,5,6,7) */
26 #define IWW5 0
28 /* different area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
[all …]
/kernel/linux/linux-4.19/drivers/staging/netlogic/
Dxlr_net.h2 * Copyright (c) 2003-2012 Broadcom Corporation
36 #define MAC_SPACING 0x400
37 #define XGMAC_SPACING 0x400
39 /* PE-MCXMAC register and bit field definitions */
40 #define R_MAC_CONFIG_1 0x00
53 #define O_MAC_CONFIG_1__txen 0
54 #define R_MAC_CONFIG_2 0x01
62 #define O_MAC_CONFIG_2__fulld 0
63 #define R_IPG_IFG 0x02
65 #define W_IPG_IFG__ipgr1 7
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-davinci/
Ddm646x.c12 #include <linux/clk-provider.h>
15 #include <linux/dma-mapping.h>
19 #include <linux/platform_data/gpio-davinci.h>
36 #define DAVINCI_VPIF_BASE (0x01C12000)
39 BIT_MASK(0))
43 #define DM646X_EMAC_BASE 0x01c80000
44 #define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
45 #define DM646X_EMAC_CNTRL_OFFSET 0x0000
46 #define DM646X_EMAC_CNTRL_MOD_OFFSET 0x1000
47 #define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000
[all …]
Dda830.c11 #include <linux/clk-provider.h>
15 #include <linux/platform_data/gpio-davinci.h>
28 #define DA830_CMP12_0 0x60
29 #define DA830_CMP12_1 0x64
30 #define DA830_CMP12_2 0x68
31 #define DA830_CMP12_3 0x6c
32 #define DA830_CMP12_4 0x70
33 #define DA830_CMP12_5 0x74
34 #define DA830_CMP12_6 0x78
35 #define DA830_CMP12_7 0x7c
[all …]
Dda850.c2 * TI DA850/OMAP-L138 chip specific setup
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
6 * Derived from: arch/arm/mach-davinci/da830.c
15 #include <linux/clk-provider.h>
21 #include <linux/mfd/da8xx-cfgchip.h>
22 #include <linux/platform_data/clk-da8xx-cfgchip.h>
23 #include <linux/platform_data/clk-davinci-pll.h>
24 #include <linux/platform_data/gpio-davinci.h>
41 #define DA850_PLL1_BASE 0x01e1a000
42 #define DA850_TIMER64P2_BASE 0x01f0c000
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-davinci/
Ddm646x.c12 #include <linux/clk-provider.h>
15 #include <linux/dma-mapping.h>
19 #include <linux/irqchip/irq-davinci-aintc.h>
21 #include <linux/platform_data/gpio-davinci.h>
32 #include <clocksource/timer-davinci.h>
39 #define DAVINCI_VPIF_BASE (0x01C12000)
42 BIT_MASK(0))
46 #define DM646X_EMAC_BASE 0x01c80000
47 #define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
48 #define DM646X_EMAC_CNTRL_OFFSET 0x0000
[all …]
/kernel/linux/linux-5.10/arch/alpha/lib/
Dfls.c1 // SPDX-License-Identifier: GPL-2.0
9 /* This is fls(x)-1, except zero is held to zero. This allows most
10 efficient input into extbl, plus it allows easy handling of fls(0)=0. */
14 0,
15 0,
29 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
30 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
31 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
32 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
33 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
[all …]
/kernel/linux/linux-4.19/arch/alpha/lib/
Dfls.c1 // SPDX-License-Identifier: GPL-2.0
9 /* This is fls(x)-1, except zero is held to zero. This allows most
10 efficient input into extbl, plus it allows easy handling of fls(0)=0. */
14 0,
15 0,
29 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
30 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
31 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
32 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
33 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
[all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/icelake/
Dpipeline.json4 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
6 "UMask": "0x1",
10 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event"
15 …R) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.",
17 "UMask": "0x1",
27 "UMask": "0x2",
37 "UMask": "0x3",
45 …-on-Store blocking code preventing store forwarding. This includes cases when: a. preceding store …
46 "EventCode": "0x03",
47 "Counter": "0,1,2,3",
[all …]
/kernel/linux/linux-5.10/include/drm/
Ddrm_dsc.h1 /* SPDX-License-Identifier: MIT
19 #define DSC_RANGE_BPG_OFFSET_MASK 0x3f
31 #define DSC_PPS_LSB_MASK (0xFF << 0)
32 #define DSC_PPS_BPP_HIGH_MASK (0x3 << 8)
37 #define DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK (0x3 << 8)
38 #define DSC_PPS_SCALE_DEC_INT_HIGH_MASK (0xF << 8)
44 #define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0
48 * struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters
70 * struct drm_dsc_config - Parameters required to configure DSC
87 * Flag to indicate if RGB - YCoCg conversion is needed
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/omapdrm/dss/
Dhdmi5_core.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
28 void __iomem *base = core->base; in hdmi5_core_ddc_init()
43 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); in hdmi5_core_ddc_init()
45 0, 0, 1) != 1) in hdmi5_core_ddc_init()
48 /* Standard (0) or Fast (1) Mode */ in hdmi5_core_ddc_init()
49 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); in hdmi5_core_ddc_init()
54 (v >> 8) & 0xff, 7, 0); in hdmi5_core_ddc_init()
56 v & 0xff, 7, 0); in hdmi5_core_ddc_init()
61 (v >> 8) & 0xff, 7, 0); in hdmi5_core_ddc_init()
[all …]
/kernel/linux/linux-5.10/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi5_core.c1 // SPDX-License-Identifier: GPL-2.0-only
30 [0] = { 7036, 0, 0, 32, 0, 7036, 0, 32, 0, 0, 7036, 32, },
32 [1] = { 7015, 0, 0, 128, 0, 7015, 0, 128, 0, 0, 7015, 128, },
34 [2] = { 7010, 0, 0, 512, 0, 7010, 0, 512, 0, 0, 7010, 512, },
36 [3] = { 8192, 0, 0, 0, 0, 8192, 0, 0, 0, 0, 8192, 0, },
41 void __iomem *base = core->base; in hdmi_core_ddc_init()
56 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); in hdmi_core_ddc_init()
58 0, 0, 1) != 1) in hdmi_core_ddc_init()
61 /* Standard (0) or Fast (1) Mode */ in hdmi_core_ddc_init()
62 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); in hdmi_core_ddc_init()
[all …]

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