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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dtegra124-nyan-blaze-emc.dtsi78 nvidia,emc-auto-cal-config = <0xa1430000>;
79 nvidia,emc-auto-cal-config2 = <0x00000000>;
80 nvidia,emc-auto-cal-config3 = <0x00000000>;
81 nvidia,emc-auto-cal-interval = <0x001fffff>;
82 nvidia,emc-bgbias-ctl0 = <0x00000008>;
83 nvidia,emc-cfg = <0x73240000>;
84 nvidia,emc-cfg-2 = <0x000008c5>;
85 nvidia,emc-ctt-term-ctrl = <0x00000802>;
86 nvidia,emc-mode-1 = <0x80100003>;
87 nvidia,emc-mode-2 = <0x80200008>;
[all …]
Dtegra124-apalis-emc.dtsi94 nvidia,emc-auto-cal-config = <0xa1430000>;
95 nvidia,emc-auto-cal-config2 = <0x00000000>;
96 nvidia,emc-auto-cal-config3 = <0x00000000>;
97 nvidia,emc-auto-cal-interval = <0x001fffff>;
98 nvidia,emc-bgbias-ctl0 = <0x00000008>;
99 nvidia,emc-cfg = <0x73240000>;
100 nvidia,emc-cfg-2 = <0x000008c5>;
101 nvidia,emc-ctt-term-ctrl = <0x00000802>;
102 nvidia,emc-mode-1 = <0x80100003>;
103 nvidia,emc-mode-2 = <0x80200008>;
[all …]
Dtegra124-jetson-tk1-emc.dtsi89 nvidia,emc-auto-cal-config = <0xa1430000>;
90 nvidia,emc-auto-cal-config2 = <0x00000000>;
91 nvidia,emc-auto-cal-config3 = <0x00000000>;
92 nvidia,emc-auto-cal-interval = <0x001fffff>;
93 nvidia,emc-bgbias-ctl0 = <0x00000008>;
94 nvidia,emc-cfg = <0x73240000>;
95 nvidia,emc-cfg-2 = <0x000008c5>;
96 nvidia,emc-ctt-term-ctrl = <0x00000802>;
97 nvidia,emc-mode-1 = <0x80100003>;
98 nvidia,emc-mode-2 = <0x80200008>;
[all …]
Dtegra124-nyan-big-emc.dtsi229 nvidia,emc-auto-cal-config = <0xa1430000>;
230 nvidia,emc-auto-cal-config2 = <0x00000000>;
231 nvidia,emc-auto-cal-config3 = <0x00000000>;
232 nvidia,emc-auto-cal-interval = <0x001fffff>;
233 nvidia,emc-bgbias-ctl0 = <0x00000008>;
234 nvidia,emc-cfg = <0x73240000>;
235 nvidia,emc-cfg-2 = <0x000008c5>;
236 nvidia,emc-ctt-term-ctrl = <0x00000802>;
237 nvidia,emc-mode-1 = <0x80100003>;
238 nvidia,emc-mode-2 = <0x80200008>;
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dtegra124-nyan-blaze-emc.dtsi78 nvidia,emc-auto-cal-config = <0xa1430000>;
79 nvidia,emc-auto-cal-config2 = <0x00000000>;
80 nvidia,emc-auto-cal-config3 = <0x00000000>;
81 nvidia,emc-auto-cal-interval = <0x001fffff>;
82 nvidia,emc-bgbias-ctl0 = <0x00000008>;
83 nvidia,emc-cfg = <0x73240000>;
84 nvidia,emc-cfg-2 = <0x000008c5>;
85 nvidia,emc-ctt-term-ctrl = <0x00000802>;
86 nvidia,emc-mode-1 = <0x80100003>;
87 nvidia,emc-mode-2 = <0x80200008>;
[all …]
Dtegra124-nyan-big-emc.dtsi78 nvidia,emc-auto-cal-config = <0xa1430000>;
79 nvidia,emc-auto-cal-config2 = <0x00000000>;
80 nvidia,emc-auto-cal-config3 = <0x00000000>;
81 nvidia,emc-auto-cal-interval = <0x001fffff>;
82 nvidia,emc-bgbias-ctl0 = <0x00000008>;
83 nvidia,emc-cfg = <0x73240000>;
84 nvidia,emc-cfg-2 = <0x000008c5>;
85 nvidia,emc-ctt-term-ctrl = <0x00000802>;
86 nvidia,emc-mode-1 = <0x80100003>;
87 nvidia,emc-mode-2 = <0x80200008>;
[all …]
Dtegra124-jetson-tk1-emc.dtsi89 nvidia,emc-auto-cal-config = <0xa1430000>;
90 nvidia,emc-auto-cal-config2 = <0x00000000>;
91 nvidia,emc-auto-cal-config3 = <0x00000000>;
92 nvidia,emc-auto-cal-interval = <0x001fffff>;
93 nvidia,emc-bgbias-ctl0 = <0x00000008>;
94 nvidia,emc-cfg = <0x73240000>;
95 nvidia,emc-cfg-2 = <0x000008c5>;
96 nvidia,emc-ctt-term-ctrl = <0x00000802>;
97 nvidia,emc-mode-1 = <0x80100003>;
98 nvidia,emc-mode-2 = <0x80200008>;
[all …]
Dtegra124-apalis-emc.dtsi129 nvidia,emc-auto-cal-config = <0xa1430000>;
130 nvidia,emc-auto-cal-config2 = <0x00000000>;
131 nvidia,emc-auto-cal-config3 = <0x00000000>;
132 nvidia,emc-auto-cal-interval = <0x001fffff>;
133 nvidia,emc-bgbias-ctl0 = <0x00000008>;
134 nvidia,emc-cfg = <0x73240000>;
135 nvidia,emc-cfg-2 = <0x000008c5>;
136 nvidia,emc-ctt-term-ctrl = <0x00000802>;
137 nvidia,emc-mode-1 = <0x80100003>;
138 nvidia,emc-mode-2 = <0x80200008>;
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra124-emc.txt36 - nvidia,emc-mode-reset : Mode Register 0
195 reg = <0x0 0x7001b000 0x0 0x1000>;
211 nvidia,emc-zcal-cnt-long = <0x00000042>;
212 nvidia,emc-auto-cal-interval = <0x001fffff>;
213 nvidia,emc-ctt-term-ctrl = <0x00000802>;
214 nvidia,emc-cfg = <0x73240000>;
215 nvidia,emc-cfg-2 = <0x000008c5>;
216 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
217 nvidia,emc-bgbias-ctl0 = <0x00000008>;
218 nvidia,emc-auto-cal-config = <0xa1430000>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra124-emc.yaml38 "^emc-timings-[0-9]+$":
48 "^timing-[0-9]+$":
79 minimum: 0
142 minimum: 0
340 reg = <0x70019000 0x1000>;
352 reg = <0x7001b000 0x1000>;
358 emc-timings-0 {
361 timing-0 {
364 nvidia,emc-auto-cal-config = <0xa1430000>;
365 nvidia,emc-auto-cal-config2 = <0x00000000>;
[all …]
/kernel/linux/linux-4.19/drivers/phy/
Dphy-xgene.c40 * indirectly from the SDS offset at 0x2000. It is only required for
42 * The PHY PLL CMU CSR is accessed indirectly from the SDS offset at 0x0000.
43 * The Serdes CSR is accessed indirectly from the SDS offset at 0x0400.
48 * at 0x1f23a000 (SATA Port 4/5). For such PHY, another resource is required
64 #define SERDES_PLL_INDIRECT_OFFSET 0x0000
65 #define SERDES_PLL_REF_INDIRECT_OFFSET 0x2000
66 #define SERDES_INDIRECT_OFFSET 0x0400
67 #define SERDES_LANE_STRIDE 0x0200
70 #define DEFAULT_SATA_TXBOOST_GAIN { 0x1e, 0x1e, 0x1e }
71 #define DEFAULT_SATA_TXEYEDIRECTION { 0x0, 0x0, 0x0 }
[all …]
/kernel/linux/linux-5.10/drivers/phy/
Dphy-xgene.c28 * indirectly from the SDS offset at 0x2000. It is only required for
30 * The PHY PLL CMU CSR is accessed indirectly from the SDS offset at 0x0000.
31 * The Serdes CSR is accessed indirectly from the SDS offset at 0x0400.
36 * at 0x1f23a000 (SATA Port 4/5). For such PHY, another resource is required
52 #define SERDES_PLL_INDIRECT_OFFSET 0x0000
53 #define SERDES_PLL_REF_INDIRECT_OFFSET 0x2000
54 #define SERDES_INDIRECT_OFFSET 0x0400
55 #define SERDES_LANE_STRIDE 0x0200
58 #define DEFAULT_SATA_TXBOOST_GAIN { 0x1e, 0x1e, 0x1e }
59 #define DEFAULT_SATA_TXEYEDIRECTION { 0x0, 0x0, 0x0 }
[all …]
/kernel/linux/linux-4.19/drivers/media/pci/saa7164/
Dsaa7164-fw.c39 while ((saa7164_readl(reg) & 0x01) == 0) { in saa7164_dl_wait_ack()
41 if (timeout == 0) { in saa7164_dl_wait_ack()
49 return 0; in saa7164_dl_wait_ack()
55 while (saa7164_readl(reg) & 0x01) { in saa7164_dl_wait_clr()
57 if (timeout == 0) { in saa7164_dl_wait_clr()
65 return 0; in saa7164_dl_wait_clr()
84 "%s(image=%p, size=%d, flags=0x%x, dst=%p, dstsize=0x%x)\n", in saa7164_downloadimage()
105 dprintk(DBGLVL_FW, "%s() dlflag = 0x%x\n", __func__, dlflag); in saa7164_downloadimage()
106 dprintk(DBGLVL_FW, "%s() dlflag_ack = 0x%x\n", __func__, dlflag_ack); in saa7164_downloadimage()
107 dprintk(DBGLVL_FW, "%s() drflag = 0x%x\n", __func__, drflag); in saa7164_downloadimage()
[all …]
/kernel/linux/linux-5.10/drivers/media/pci/saa7164/
Dsaa7164-fw.c29 while ((saa7164_readl(reg) & 0x01) == 0) { in saa7164_dl_wait_ack()
31 if (timeout == 0) { in saa7164_dl_wait_ack()
39 return 0; in saa7164_dl_wait_ack()
45 while (saa7164_readl(reg) & 0x01) { in saa7164_dl_wait_clr()
47 if (timeout == 0) { in saa7164_dl_wait_clr()
55 return 0; in saa7164_dl_wait_clr()
74 "%s(image=%p, size=%d, flags=0x%x, dst=%p, dstsize=0x%x)\n", in saa7164_downloadimage()
95 dprintk(DBGLVL_FW, "%s() dlflag = 0x%x\n", __func__, dlflag); in saa7164_downloadimage()
96 dprintk(DBGLVL_FW, "%s() dlflag_ack = 0x%x\n", __func__, dlflag_ack); in saa7164_downloadimage()
97 dprintk(DBGLVL_FW, "%s() drflag = 0x%x\n", __func__, drflag); in saa7164_downloadimage()
[all …]
/kernel/linux/linux-5.10/arch/csky/kernel/probes/
Dsimulate-insn.h20 } while (0)
22 __CSKY_INSN_FUNCS(br16, 0xfc00, 0x0400)
23 __CSKY_INSN_FUNCS(bt16, 0xfc00, 0x0800)
24 __CSKY_INSN_FUNCS(bf16, 0xfc00, 0x0c00)
25 __CSKY_INSN_FUNCS(jmp16, 0xffc3, 0x7800)
26 __CSKY_INSN_FUNCS(jsr16, 0xffc3, 0x7801)
27 __CSKY_INSN_FUNCS(lrw16, 0xfc00, 0x1000)
28 __CSKY_INSN_FUNCS(pop16, 0xffe0, 0x1480)
30 __CSKY_INSN_FUNCS(br32, 0x0000ffff, 0x0000e800)
31 __CSKY_INSN_FUNCS(bt32, 0x0000ffff, 0x0000e860)
[all …]
/kernel/linux/linux-5.10/arch/sh/include/cpu-sh4/cpu/
Dmmu_context.h10 #define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */
11 #define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
12 #define MMU_TTB 0xFF000008 /* Translation table base register */
13 #define MMU_TEA 0xFF00000C /* TLB Exception Address */
14 #define MMU_PTEA 0xFF000034 /* PTE assistance register */
15 #define MMU_PTEAEX 0xFF00007C /* PTE ASID extension register */
17 #define MMUCR 0xFF000010 /* MMU Control Register */
21 #define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
22 #define MMU_ITLB_ADDRESS_ARRAY2 0xF2800000
23 #define MMU_ITLB_DATA_ARRAY 0xF3000000
[all …]
/kernel/linux/linux-4.19/arch/sh/include/cpu-sh4/cpu/
Dmmu_context.h13 #define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */
14 #define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
15 #define MMU_TTB 0xFF000008 /* Translation table base register */
16 #define MMU_TEA 0xFF00000C /* TLB Exception Address */
17 #define MMU_PTEA 0xFF000034 /* PTE assistance register */
18 #define MMU_PTEAEX 0xFF00007C /* PTE ASID extension register */
20 #define MMUCR 0xFF000010 /* MMU Control Register */
24 #define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
25 #define MMU_ITLB_ADDRESS_ARRAY2 0xF2800000
26 #define MMU_ITLB_DATA_ARRAY 0xF3000000
[all …]
/kernel/linux/linux-4.19/drivers/infiniband/hw/nes/
Dnes_context.h85 #define NES_QPCONTEXT_MISC_IWARP_VER_MASK 0x00000003
86 #define NES_QPCONTEXT_MISC_IWARP_VER_SHIFT 0
87 #define NES_QPCONTEXT_MISC_EFB_SIZE_MASK 0x000000C0
89 #define NES_QPCONTEXT_MISC_RQ_SIZE_MASK 0x00000300
91 #define NES_QPCONTEXT_MISC_SQ_SIZE_MASK 0x00000c00
93 #define NES_QPCONTEXT_MISC_PCI_FCN_MASK 0x00007000
95 #define NES_QPCONTEXT_MISC_DUP_ACKS_MASK 0x00070000
99 NES_QPCONTEXT_MISC_RX_WQE_SIZE = 0x00000004,
100 NES_QPCONTEXT_MISC_IPV4 = 0x00000008,
101 NES_QPCONTEXT_MISC_DO_NOT_FRAG = 0x00000010,
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/ath/ath9k/
Dar9002_phy.h19 #define AR_PHY_TEST 0x9800
20 #define PHY_AGC_CLR 0x10000000
21 #define RFSILENT_BB 0x00002000
23 #define AR_PHY_TURBO 0x9804
24 #define AR_PHY_FC_TURBO_MODE 0x00000001
25 #define AR_PHY_FC_TURBO_SHORT 0x00000002
26 #define AR_PHY_FC_DYN2040_EN 0x00000004
27 #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
28 #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
30 #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
[all …]
/kernel/linux/linux-4.19/drivers/net/wireless/ath/ath9k/
Dar9002_phy.h19 #define AR_PHY_TEST 0x9800
20 #define PHY_AGC_CLR 0x10000000
21 #define RFSILENT_BB 0x00002000
23 #define AR_PHY_TURBO 0x9804
24 #define AR_PHY_FC_TURBO_MODE 0x00000001
25 #define AR_PHY_FC_TURBO_SHORT 0x00000002
26 #define AR_PHY_FC_DYN2040_EN 0x00000004
27 #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
28 #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
30 #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
[all …]
/kernel/linux/linux-4.19/drivers/net/wireless/ath/carl9170/
Dphy.h24 #define AR9170_PHY_REG_BASE (0x1bc000 + 0x9800)
28 #define AR9170_PHY_REG_TEST (AR9170_PHY_REG_BASE + 0x0000)
29 #define AR9170_PHY_TEST_AGC_CLR 0x10000000
30 #define AR9170_PHY_TEST_RFSILENT_BB 0x00002000
32 #define AR9170_PHY_REG_TURBO (AR9170_PHY_REG_BASE + 0x0004)
33 #define AR9170_PHY_TURBO_FC_TURBO_MODE 0x00000001
34 #define AR9170_PHY_TURBO_FC_TURBO_SHORT 0x00000002
35 #define AR9170_PHY_TURBO_FC_DYN2040_EN 0x00000004
36 #define AR9170_PHY_TURBO_FC_DYN2040_PRI_ONLY 0x00000008
37 #define AR9170_PHY_TURBO_FC_DYN2040_PRI_CH 0x00000010
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/ath/carl9170/
Dphy.h24 #define AR9170_PHY_REG_BASE (0x1bc000 + 0x9800)
28 #define AR9170_PHY_REG_TEST (AR9170_PHY_REG_BASE + 0x0000)
29 #define AR9170_PHY_TEST_AGC_CLR 0x10000000
30 #define AR9170_PHY_TEST_RFSILENT_BB 0x00002000
32 #define AR9170_PHY_REG_TURBO (AR9170_PHY_REG_BASE + 0x0004)
33 #define AR9170_PHY_TURBO_FC_TURBO_MODE 0x00000001
34 #define AR9170_PHY_TURBO_FC_TURBO_SHORT 0x00000002
35 #define AR9170_PHY_TURBO_FC_DYN2040_EN 0x00000004
36 #define AR9170_PHY_TURBO_FC_DYN2040_PRI_ONLY 0x00000008
37 #define AR9170_PHY_TURBO_FC_DYN2040_PRI_CH 0x00000010
[all …]
/kernel/linux/linux-5.10/drivers/thermal/qcom/
Dtsens-v1.c13 #define SROT_HW_VER_OFF 0x0000
14 #define SROT_CTRL_OFF 0x0004
17 #define TM_INT_EN_OFF 0x0000
18 #define TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF 0x0004
19 #define TM_Sn_STATUS_OFF 0x0044
20 #define TM_TRDY_OFF 0x0084
21 #define TM_HIGH_LOW_INT_STATUS_OFF 0x0088
22 #define TM_HIGH_LOW_Sn_INT_THRESHOLD_OFF 0x0090
25 #define MSM8976_BASE0_MASK 0xff
26 #define MSM8976_BASE1_MASK 0xff
[all …]
/kernel/linux/linux-4.19/arch/mips/include/asm/xtalk/
Dxwidget.h18 #define WIDGET_ID 0x04
19 #define WIDGET_STATUS 0x0c
20 #define WIDGET_ERR_UPPER_ADDR 0x14
21 #define WIDGET_ERR_LOWER_ADDR 0x1c
22 #define WIDGET_CONTROL 0x24
23 #define WIDGET_REQ_TIMEOUT 0x2c
24 #define WIDGET_INTDEST_UPPER_ADDR 0x34
25 #define WIDGET_INTDEST_LOWER_ADDR 0x3c
26 #define WIDGET_ERR_CMD_WORD 0x44
27 #define WIDGET_LLP_CFG 0x4c
[all …]
/kernel/linux/linux-5.10/arch/mips/include/asm/xtalk/
Dxwidget.h18 #define WIDGET_ID 0x04
19 #define WIDGET_STATUS 0x0c
20 #define WIDGET_ERR_UPPER_ADDR 0x14
21 #define WIDGET_ERR_LOWER_ADDR 0x1c
22 #define WIDGET_CONTROL 0x24
23 #define WIDGET_REQ_TIMEOUT 0x2c
24 #define WIDGET_INTDEST_UPPER_ADDR 0x34
25 #define WIDGET_INTDEST_LOWER_ADDR 0x3c
26 #define WIDGET_ERR_CMD_WORD 0x44
27 #define WIDGET_LLP_CFG 0x4c
[all …]

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