| /kernel/linux/linux-5.10/arch/mips/cobalt/ |
| D | led.c | 15 .start = 0x1c000000,
16 .end = 0x1c000000,
42 return 0; in cobalt_led_add()
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| D | reset.c | 20 #define RESET_PORT ((void __iomem *)CKSEG1ADDR(0x1c000000))
21 #define RESET 0x0f
28 return 0; in ledtrig_power_off_init()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/bus/ |
| D | qcom,ebi2.txt | 24 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
25 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
26 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
27 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
28 CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
29 CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
58 ranges = <0 0x0 0x1a800000 0x00800000>,
59 <1 0x0 0x1b000000 0x00800000>,
60 <2 0x0 0x1b800000 0x00800000>,
61 <3 0x0 0x1d000000 0x08000000>,
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/bus/ |
| D | qcom,ebi2.txt | 24 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
25 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
26 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
27 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
28 CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
29 CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
58 ranges = <0 0x0 0x1a800000 0x00800000>,
59 <1 0x0 0x1b000000 0x00800000>,
60 <2 0x0 0x1b800000 0x00800000>,
61 <3 0x0 0x1d000000 0x08000000>,
[all …]
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| /kernel/linux/linux-4.19/arch/mips/cobalt/ |
| D | led.c | 28 .start = 0x1c000000,
29 .end = 0x1c000000,
55 return 0; in cobalt_led_add()
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| D | reset.c | 20 #define RESET_PORT ((void __iomem *)CKSEG1ADDR(0x1c000000))
21 #define RESET 0x0f
28 return 0; in ledtrig_power_off_init()
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| /kernel/linux/linux-4.19/arch/sh/boards/ |
| D | board-urquell.c | 35 * SW2 0x1x xxxx -> little endian
42 * 0x00000000 - 0x04000000 (CS0) Nor Flash
43 * 0x04000000 - 0x04200000 (CS1) SRAM
44 * 0x05000000 - 0x05800000 (CS1) on board register
45 * 0x05800000 - 0x06000000 (CS1) LAN91C111
46 * 0x06000000 - 0x06400000 (CS1) PCMCIA
47 * 0x08000000 - 0x10000000 (CS2-CS3) DDR3
48 * 0x10000000 - 0x14000000 (CS4) PCIe
49 * 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM
50 * 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM
[all …]
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| /kernel/linux/linux-5.10/arch/sh/boards/ |
| D | board-urquell.c | 32 * SW2 0x1x xxxx -> little endian
39 * 0x00000000 - 0x04000000 (CS0) Nor Flash
40 * 0x04000000 - 0x04200000 (CS1) SRAM
41 * 0x05000000 - 0x05800000 (CS1) on board register
42 * 0x05800000 - 0x06000000 (CS1) LAN91C111
43 * 0x06000000 - 0x06400000 (CS1) PCMCIA
44 * 0x08000000 - 0x10000000 (CS2-CS3) DDR3
45 * 0x10000000 - 0x14000000 (CS4) PCIe
46 * 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM
47 * 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM
[all …]
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| /kernel/linux/linux-5.10/arch/mips/include/asm/mach-ralink/ |
| D | mt7621.h | 10 #define MT7621_PALMBUS_BASE 0x1C000000
11 #define MT7621_PALMBUS_SIZE 0x03FFFFFF
13 #define MT7621_SYSC_BASE 0x1E000000
15 #define SYSC_REG_CHIP_NAME0 0x00
16 #define SYSC_REG_CHIP_NAME1 0x04
17 #define SYSC_REG_CHIP_REV 0x0c
18 #define SYSC_REG_SYSTEM_CONFIG0 0x10
19 #define SYSC_REG_SYSTEM_CONFIG1 0x14
21 #define CHIP_REV_PKG_MASK 0x1
23 #define CHIP_REV_VER_MASK 0xf
[all …]
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| /kernel/linux/linux-4.19/drivers/scsi/qla2xxx/ |
| D | qla_tmpl.c | 12 0x63000000, 0xa4000000, 0x7c050000, 0x00000000,
13 0x30000000, 0x01000000, 0x00000000, 0xc0406eb4,
14 0x00000000, 0x00000000, 0x00000000, 0x00000000,
15 0x00000000, 0x00000000, 0x00000000, 0x00000000,
16 0x00000000, 0x00000000, 0x00000000, 0x00000000,
17 0x00000000, 0x00000000, 0x00000000, 0x00000000,
18 0x00000000, 0x00000000, 0x00000000, 0x00000000,
19 0x00000000, 0x00000000, 0x00000000, 0x00000000,
20 0x00000000, 0x00000000, 0x00000000, 0x00000000,
21 0x00000000, 0x00000000, 0x00000000, 0x00000000,
[all …]
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| /kernel/linux/linux-4.19/arch/mips/include/asm/mach-ralink/ |
| D | mt7621.h | 12 #define MT7621_PALMBUS_BASE 0x1C000000
13 #define MT7621_PALMBUS_SIZE 0x03FFFFFF
15 #define MT7621_SYSC_BASE 0x1E000000
17 #define SYSC_REG_CHIP_NAME0 0x00
18 #define SYSC_REG_CHIP_NAME1 0x04
19 #define SYSC_REG_CHIP_REV 0x0c
20 #define SYSC_REG_SYSTEM_CONFIG0 0x10
21 #define SYSC_REG_SYSTEM_CONFIG1 0x14
23 #define CHIP_REV_PKG_MASK 0x1
25 #define CHIP_REV_VER_MASK 0xf
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,bdpsys.txt | 21 reg = <0 0x1c000000 0 0x1000>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,bdpsys.txt | 22 reg = <0 0x1c000000 0 0x1000>;
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| /kernel/linux/linux-5.10/arch/sh/include/cpu-sh4/cpu/ |
| D | addrspace.h | 10 #define P0SEG 0x00000000
11 #define P1SEG 0x80000000
12 #define P2SEG 0xa0000000
13 #define P3SEG 0xc0000000
14 #define P4SEG 0xe0000000
18 #define P4SEG_IC_ADDR 0xf0000000
19 #define P4SEG_IC_DATA 0xf1000000
20 #define P4SEG_ITLB_ADDR 0xf2000000
21 #define P4SEG_ITLB_DATA 0xf3000000
22 #define P4SEG_OC_ADDR 0xf4000000
[all …]
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| /kernel/linux/linux-4.19/arch/sh/include/cpu-sh4/cpu/ |
| D | addrspace.h | 13 #define P0SEG 0x00000000
14 #define P1SEG 0x80000000
15 #define P2SEG 0xa0000000
16 #define P3SEG 0xc0000000
17 #define P4SEG 0xe0000000
21 #define P4SEG_IC_ADDR 0xf0000000
22 #define P4SEG_IC_DATA 0xf1000000
23 #define P4SEG_ITLB_ADDR 0xf2000000
24 #define P4SEG_ITLB_DATA 0xf3000000
25 #define P4SEG_OC_ADDR 0xf4000000
[all …]
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| /kernel/linux/linux-5.10/arch/arm/include/debug/ |
| D | vexpress.S | 10 #define DEBUG_LL_PHYS_BASE 0x10000000
11 #define DEBUG_LL_UART_OFFSET 0x00009000
13 #define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
14 #define DEBUG_LL_UART_OFFSET_RS1 0x00090000
16 #define DEBUG_LL_UART_PHYS_CRX 0xb0090000
18 #define DEBUG_LL_VIRT_BASE 0xf8000000
27 @ should use UART at 0x10009000
29 @ at 0x1c090000
30 mrc p15, 0, \rp, c0, c0, 0
31 movw \rv, #0xc091
[all …]
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| /kernel/linux/linux-4.19/arch/arm/include/debug/ |
| D | vexpress.S | 13 #define DEBUG_LL_PHYS_BASE 0x10000000
14 #define DEBUG_LL_UART_OFFSET 0x00009000
16 #define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
17 #define DEBUG_LL_UART_OFFSET_RS1 0x00090000
19 #define DEBUG_LL_UART_PHYS_CRX 0xb0090000
21 #define DEBUG_LL_VIRT_BASE 0xf8000000
30 @ should use UART at 0x10009000
32 @ at 0x1c090000
33 mrc p15, 0, \rp, c0, c0, 0
34 movw \rv, #0xc091
[all …]
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| /kernel/linux/linux-4.19/arch/mips/include/asm/mach-malta/ |
| D | spaces.h | 17 * 0x00000000 - 0x0fffffff: 1st RAM region, 256MB
18 * 0x10000000 - 0x1bffffff: GIC and CPC Control Registers
19 * 0x1c000000 - 0x1fffffff: I/O And Flash
20 * 0x20000000 - 0x7fffffff: 2nd RAM region, 1.5GB
21 * 0x80000000 - 0xffffffff: Physical memory aliases to 0x0 (2GB)
23 * The kernel is still located in 0x80000000(kseg0). However,
24 * the physical mask has been shifted to 0x80000000 which exploits the alias
27 * words, the 0x80000000 virtual address maps to 0x80000000 physical address
28 * which in turn aliases to 0x0. We do this in order to be able to use a flat
29 * 2GB of memory (0x80000000 - 0xffffffff) so we can avoid the I/O hole in
[all …]
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| /kernel/linux/linux-5.10/arch/mips/include/asm/mach-malta/ |
| D | spaces.h | 17 * 0x00000000 - 0x0fffffff: 1st RAM region, 256MB
18 * 0x10000000 - 0x1bffffff: GIC and CPC Control Registers
19 * 0x1c000000 - 0x1fffffff: I/O And Flash
20 * 0x20000000 - 0x7fffffff: 2nd RAM region, 1.5GB
21 * 0x80000000 - 0xffffffff: Physical memory aliases to 0x0 (2GB)
23 * The kernel is still located in 0x80000000(kseg0). However,
24 * the physical mask has been shifted to 0x80000000 which exploits the alias
27 * words, the 0x80000000 virtual address maps to 0x80000000 physical address
28 * which in turn aliases to 0x0. We do this in order to be able to use a flat
29 * 2GB of memory (0x80000000 - 0xffffffff) so we can avoid the I/O hole in
[all …]
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| /kernel/linux/linux-5.10/drivers/misc/habanalabs/include/goya/asic_reg/ |
| D | mme_masks.h | 23 #define MME_ARCH_STATUS_A_SHIFT 0
24 #define MME_ARCH_STATUS_A_MASK 0x1
26 #define MME_ARCH_STATUS_B_MASK 0x2
28 #define MME_ARCH_STATUS_CIN_MASK 0x4
30 #define MME_ARCH_STATUS_COUT_MASK 0x8
32 #define MME_ARCH_STATUS_TE_MASK 0x10
34 #define MME_ARCH_STATUS_LD_MASK 0x20
36 #define MME_ARCH_STATUS_ST_MASK 0x40
38 #define MME_ARCH_STATUS_SB_A_EMPTY_MASK 0x80
40 #define MME_ARCH_STATUS_SB_B_EMPTY_MASK 0x100
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/mt7621-dts/ |
| D | gbpc1.dts | 12 memory@0 {
14 reg = <0x0 0x1c000000>, <0x20000000 0x4000000>;
69 m25p80@0 {
73 reg = <0>;
77 partition@0 {
79 reg = <0x0 0x30000>;
85 reg = <0x30000 0x10000>;
91 reg = <0x40000 0x10000>;
97 reg = <0x50000 0x1FB0000>;
116 pinctrl-0 = <&pcie_pins>;
[all …]
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| /kernel/linux/linux-4.19/drivers/staging/mt7621-dts/ |
| D | gbpc1.dts | 12 memory@0 {
14 reg = <0x0 0x1c000000>, <0x20000000 0x4000000>;
69 m25p80@0 {
73 reg = <0>;
76 partition@0 {
78 reg = <0x0 0x30000>;
84 reg = <0x30000 0x10000>;
90 reg = <0x40000 0x10000>;
96 reg = <0x50000 0x1FB0000>;
115 pinctrl-0 = <&pcie_pins>;
[all …]
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| /kernel/linux/linux-4.19/arch/mips/include/asm/dec/ |
| D | kn02xa.h | 22 #define KN02XA_SLOT_BASE 0x1c000000
27 #define KN02XA_MER 0x0c400000 /* memory error register */
28 #define KN02XA_MSR 0x0c800000 /* memory size register */
33 #define KN02XA_MEM_CONF 0x0e000000 /* write timeout config */
34 #define KN02XA_EAR 0x0e000004 /* error address register */
35 #define KN02XA_BOOT0 0x0e000008 /* boot 0 register */
36 #define KN02XA_MEM_INTR 0x0e00000c /* write err IRQ stat & ack */
42 #define KN02XA_MER_RES_28 (0xf<<28) /* unused */
43 #define KN02XA_MER_RES_17 (0x3ff<<17) /* unused */
49 #define KN02XA_MER_BYTERR (0xf<<8) /* byte lane error bitmask: */
[all …]
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| /kernel/linux/linux-5.10/arch/mips/include/asm/dec/ |
| D | kn02xa.h | 22 #define KN02XA_SLOT_BASE 0x1c000000
27 #define KN02XA_MER 0x0c400000 /* memory error register */
28 #define KN02XA_MSR 0x0c800000 /* memory size register */
33 #define KN02XA_MEM_CONF 0x0e000000 /* write timeout config */
34 #define KN02XA_EAR 0x0e000004 /* error address register */
35 #define KN02XA_BOOT0 0x0e000008 /* boot 0 register */
36 #define KN02XA_MEM_INTR 0x0e00000c /* write err IRQ stat & ack */
42 #define KN02XA_MER_RES_28 (0xf<<28) /* unused */
43 #define KN02XA_MER_RES_17 (0x3ff<<17) /* unused */
49 #define KN02XA_MER_BYTERR (0xf<<8) /* byte lane error bitmask: */
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | arm,pl172.txt | 11 first address cell and it may accept values 0..N-1
88 Example for pl172 with nor flash on chip select 0 shown below.
92 reg = <0x40005000 0x1000>;
97 ranges = <0 0 0x1c000000 0x1000000
98 1 0 0x1d000000 0x1000000
99 2 0 0x1e000000 0x1000000
100 3 0 0x1f000000 0x1000000>;
107 mpmc,cs = <0>;
110 mpmc,write-enable-delay = <0>;
111 mpmc,output-enable-delay = <0>;
[all …]
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