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15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…[all …]
14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…[all …]
13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x014 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x015 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x016 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x017 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x018 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x019 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x020 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x021 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x022 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0[all …]
14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x015 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x316 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x017 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x318 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x019 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x020 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x021 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x022 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x023 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0[all …]
20 reg = <0x70000000 0x20000000>,21 <0xb0000000 0x20000000>;24 display-0 {26 #size-cells = <0>;30 pinctrl-0 = <&pinctrl_ipu_disp0>;32 port@0 {33 reg = <0>;66 #size-cells = <0>;68 port@0 {69 reg = <0>;[all …]
15 pinctrl-0 = <&pinctrl_backlight>;25 pinctrl-0 = <&pinctrl_ipu_disp1>;42 pixelclk-active = <0>;76 pinctrl-0 = <&pinctrl_ecspi1>;84 pinctrl-0 = <&pinctrl_ecspi2>;92 pinctrl-0 = <&pinctrl_esdhc1>;100 pinctrl-0 = <&pinctrl_esdhc2>;108 pinctrl-0 = <&pinctrl_i2c2>;114 pinctrl-0 = <&pinctrl_hog>;119 MX51_PAD_DI1_D1_CS__GPIO3_4 0x1F5[all …]
13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x014 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x015 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x016 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x017 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x018 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x019 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x020 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x021 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x022 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0[all …]
13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x014 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x015 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x016 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x017 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x018 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x019 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x020 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x021 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x022 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0[all …]
17 pinctrl-0 = <&pinctrl_ipu_disp1>;44 pwms = <&pwm1 0 3000>;45 brightness-levels = <0 4 8 16 32 64 128 255>;53 pinctrl-0 = <&led_pin_gpio>;57 gpios = <&gpio2 8 0>;63 gpios = <&gpio2 9 0>;71 #size-cells = <0>;79 gpio = <&gpio1 2 0>;88 gpio = <&gpio1 4 0>;111 pinctrl-0 = <&pinctrl_audmux>;[all …]
15 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x016 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x017 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x018 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x019 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x020 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x021 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x022 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x023 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x024 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0[all …]
22 reg = <0x90000000 0x10000000>;38 pinctrl-0 = <&pinctrl_enable_lcd>;48 pwms = <&pwm1 0 78770>;49 brightness-levels = <0 150 200 255>;58 pinctrl-0 = <&pinctrl_lcd>;69 vback-porch = <0>;70 vfront-porch = <0>;85 pinctrl-0 = <&pinctrl_esdhc1>;86 cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;93 pinctrl-0 = <&pinctrl_fec>;[all …]
13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x014 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x015 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x016 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x017 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x018 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x019 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x020 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x021 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x022 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0[all …]
15 reg = <0x70000000 0x20000000>,16 <0xb0000000 0x20000000>;22 pinctrl-0 = <&pinctrl_ipu_disp0>;25 #size-cells = <0>;28 port@0 {29 reg = <0>;72 pinctrl-0 = <&led_pin_gpio7_7>;76 gpios = <&gpio7 7 0>;94 #size-cells = <0>;96 reg_3p2v: regulator@0 {[all …]
19 reg = <0x90000000 0x20000000>;28 #clock-cells = <0>;35 pinctrl-0 = <&pinctrl_clk26mhz_osc>;37 #clock-cells = <0>;44 pinctrl-0 = <&pinctrl_clk26mhz_audio>;46 #clock-cells = <0>;53 pinctrl-0 = <&pinctrl_clk26mhz_usb>;55 #clock-cells = <0>;62 #size-cells = <0>;65 pinctrl-0 = <&pinctrl_ipu_disp1>;[all …]
21 pinctrl-0 = <&pinctrl_backlight>;31 pinctrl-0 = <&pinctrl_ipu_disp1>;48 pixelclk-active = <0>;82 pinctrl-0 = <&pinctrl_ecspi1>;90 pinctrl-0 = <&pinctrl_ecspi2>;98 pinctrl-0 = <&pinctrl_esdhc1>;106 pinctrl-0 = <&pinctrl_esdhc2>;114 pinctrl-0 = <&pinctrl_i2c2>;120 pinctrl-0 = <&pinctrl_hog>;125 MX51_PAD_DI1_D1_CS__GPIO3_4 0x1F5[all …]
17 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x018 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x019 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x020 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x021 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x022 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x023 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x024 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x025 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x026 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0[all …]
17 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x018 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x019 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x020 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x021 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x022 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x023 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x024 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x025 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x026 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0[all …]
23 pinctrl-0 = <&pinctrl_ipu_disp1>;50 pwms = <&pwm1 0 3000>;51 brightness-levels = <0 4 8 16 32 64 128 255>;59 pinctrl-0 = <&led_pin_gpio>;63 gpios = <&gpio2 8 0>;69 gpios = <&gpio2 9 0>;77 #size-cells = <0>;85 gpio = <&gpio1 2 0>;94 gpio = <&gpio1 4 0>;117 pinctrl-0 = <&pinctrl_audmux>;[all …]
26 reg = <0x70000000 0x20000000>,27 <0xb0000000 0x20000000>;30 display-0 {32 #size-cells = <0>;36 pinctrl-0 = <&pinctrl_ipu_disp0>;38 port@0 {39 reg = <0>;69 #size-cells = <0>;72 port@0 {73 reg = <0>;[all …]
19 reg = <0x90000000 0x20000000>;28 #clock-cells = <0>;35 pinctrl-0 = <&pinctrl_clk26mhz_osc>;37 #clock-cells = <0>;44 pinctrl-0 = <&pinctrl_clk26mhz_audio>;46 #clock-cells = <0>;53 pinctrl-0 = <&pinctrl_clk26mhz_usb>;55 #clock-cells = <0>;63 pinctrl-0 = <&pinctrl_ipu_disp1>;90 pinctrl-0 = <&pinctrl_ipu_disp2>;[all …]
17 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x018 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x019 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x020 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x021 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x022 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x023 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x024 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x025 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x026 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0[all …]
15 reg = <0x70000000 0x20000000>,16 <0xb0000000 0x20000000>;23 pinctrl-0 = <&pinctrl_ipu_disp0>;37 hsync-active = <0>;38 vsync-active = <0>;40 pixelclk-active = <0>;78 pinctrl-0 = <&led_pin_gpio7_7>;82 gpios = <&gpio7 7 0>;90 #size-cells = <0>;92 reg_3p2v: regulator@0 {[all …]
17 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x018 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x019 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x020 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x021 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x022 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x023 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x024 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x025 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x026 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0[all …]