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/kernel/linux/linux-5.10/drivers/dma/
Duniphier-xdmac.c20 #define XDMAC_CH_WIDTH 0x100
22 #define XDMAC_TFA 0x08
24 #define XDMAC_TFA_MASK GENMASK(5, 0)
25 #define XDMAC_SADM 0x10
29 #define XDMAC_SADM_SAM_INC 0
30 #define XDMAC_DADM 0x14
35 #define XDMAC_EXSAD 0x18
36 #define XDMAC_EXDAD 0x1c
37 #define XDMAC_SAD 0x20
38 #define XDMAC_DAD 0x24
[all …]
/kernel/linux/linux-5.10/drivers/block/paride/
Dfit3.c32 #define j44(a,b) (((a>>3)&0x0f)|((b<<1)&0xf0))
35 #define r7() (in_p(7) & 0xff)
37 /* cont = 0 - access the IDE register file
48 case 0: in fit3_write_regr()
49 case 1: w2(0xc); w0(regr); w2(0x8); w2(0xc); in fit3_write_regr()
50 w0(val); w2(0xd); in fit3_write_regr()
51 w0(0); w2(0xc); in fit3_write_regr()
54 case 2: w2(0xc); w0(regr); w2(0x8); w2(0xc); in fit3_write_regr()
55 w4(val); w4(0); in fit3_write_regr()
56 w2(0xc); in fit3_write_regr()
[all …]
/kernel/linux/linux-4.19/drivers/block/paride/
Dfit3.c32 #define j44(a,b) (((a>>3)&0x0f)|((b<<1)&0xf0))
35 #define r7() (in_p(7) & 0xff)
37 /* cont = 0 - access the IDE register file
48 case 0: in fit3_write_regr()
49 case 1: w2(0xc); w0(regr); w2(0x8); w2(0xc); in fit3_write_regr()
50 w0(val); w2(0xd); in fit3_write_regr()
51 w0(0); w2(0xc); in fit3_write_regr()
54 case 2: w2(0xc); w0(regr); w2(0x8); w2(0xc); in fit3_write_regr()
55 w4(val); w4(0); in fit3_write_regr()
56 w2(0xc); in fit3_write_regr()
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/kernel/linux/linux-5.10/arch/powerpc/kvm/
Dbook3s_xive_template.c14 static void GLUE(X_PFX,ack_pending)(struct kvmppc_xive_vcpu *xc) in GLUE()
38 cppr = ack & 0xff; in GLUE()
40 xc->pending |= 1 << cppr; in GLUE()
44 if (cppr >= xc->hw_cppr) in GLUE()
46 smp_processor_id(), cppr, xc->hw_cppr); in GLUE()
51 * xc->cppr, this will be done as we scan for interrupts in GLUE()
54 xc->hw_cppr = cppr; in GLUE()
79 __x_writeq(0, __x_eoi_page(xd) + XIVE_ESB_STORE_EOI); in GLUE()
105 __x_writeq(0, __x_trig_page(xd)); in GLUE()
115 static u32 GLUE(X_PFX,scan_interrupts)(struct kvmppc_xive_vcpu *xc, in GLUE()
[all …]
Dbook3s_xive.c91 vcpu->arch.irq_pending = 0; in kvmppc_xive_push_vcpu()
124 /* Now P is 0, we can clear the flag */ in kvmppc_xive_push_vcpu()
125 vcpu->arch.xive_esc_on = 0; in kvmppc_xive_push_vcpu()
144 out_be64(xd->trig_mmio, 0); in xive_irq_trigger()
178 struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; in kvmppc_xive_attach_escalation() local
179 struct xive_q *q = &xc->queues[prio]; in kvmppc_xive_attach_escalation()
184 if (xc->esc_virq[prio]) in kvmppc_xive_attach_escalation()
185 return 0; in kvmppc_xive_attach_escalation()
188 xc->esc_virq[prio] = irq_create_mapping(NULL, q->esc_irq); in kvmppc_xive_attach_escalation()
189 if (!xc->esc_virq[prio]) { in kvmppc_xive_attach_escalation()
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Dbook3s_xive_native.c49 struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; in kvmppc_xive_native_cleanup_queue() local
50 struct xive_q *q = &xc->queues[prio]; in kvmppc_xive_native_cleanup_queue()
52 xive_native_disable_queue(xc->vp_id, q, prio); in kvmppc_xive_native_cleanup_queue()
79 struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; in kvmppc_xive_native_cleanup_vcpu() local
85 if (!xc) in kvmppc_xive_native_cleanup_vcpu()
88 pr_devel("native_cleanup_vcpu(cpu=%d)\n", xc->server_num); in kvmppc_xive_native_cleanup_vcpu()
91 xc->valid = false; in kvmppc_xive_native_cleanup_vcpu()
95 for (i = 0; i < KVMPPC_XIVE_Q_COUNT; i++) { in kvmppc_xive_native_cleanup_vcpu()
97 if (xc->esc_virq[i]) { in kvmppc_xive_native_cleanup_vcpu()
98 if (xc->xive->single_escalation) in kvmppc_xive_native_cleanup_vcpu()
[all …]
/kernel/linux/linux-4.19/arch/powerpc/kvm/
Dbook3s_xive_template.c17 static void GLUE(X_PFX,ack_pending)(struct kvmppc_xive_vcpu *xc) in GLUE()
41 cppr = ack & 0xff; in GLUE()
43 xc->pending |= 1 << cppr; in GLUE()
47 if (cppr >= xc->hw_cppr) in GLUE()
49 smp_processor_id(), cppr, xc->hw_cppr); in GLUE()
54 * xc->cppr, this will be done as we scan for interrupts in GLUE()
57 xc->hw_cppr = cppr; in GLUE()
79 __x_writeq(0, __x_eoi_page(xd) + XIVE_ESB_STORE_EOI); in GLUE()
105 __x_writeq(0, __x_trig_page(xd)); in GLUE()
115 static u32 GLUE(X_PFX,scan_interrupts)(struct kvmppc_xive_vcpu *xc, in GLUE()
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Dbook3s_xive.c78 out_be64(xd->trig_mmio, 0); in xive_irq_trigger()
108 struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; in xive_attach_escalation() local
109 struct xive_q *q = &xc->queues[prio]; in xive_attach_escalation()
114 if (xc->esc_virq[prio]) in xive_attach_escalation()
115 return 0; in xive_attach_escalation()
118 xc->esc_virq[prio] = irq_create_mapping(NULL, q->esc_irq); in xive_attach_escalation()
119 if (!xc->esc_virq[prio]) { in xive_attach_escalation()
121 prio, xc->server_num); in xive_attach_escalation()
125 if (xc->xive->single_escalation) in xive_attach_escalation()
127 vcpu->kvm->arch.lpid, xc->server_num); in xive_attach_escalation()
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/kernel/linux/linux-4.19/arch/s390/lib/
Dxor.c17 " aghi %0,-1\n" in xor_xc_2()
19 " srlg 0,%0,8\n" in xor_xc_2()
20 " ltgr 0,0\n" in xor_xc_2()
22 "0: xc 0(256,%1),0(%2)\n" in xor_xc_2()
25 " brctg 0,0b\n" in xor_xc_2()
26 "1: ex %0,0(1)\n" in xor_xc_2()
28 "2: xc 0(1,%1),0(%2)\n" in xor_xc_2()
31 : "0", "1", "cc", "memory"); in xor_xc_2()
39 " aghi %0,-1\n" in xor_xc_3()
41 " srlg 0,%0,8\n" in xor_xc_3()
[all …]
/kernel/linux/linux-5.10/arch/s390/lib/
Dxor.c18 " aghi %0,-1\n" in xor_xc_2()
20 " srlg 0,%0,8\n" in xor_xc_2()
21 " ltgr 0,0\n" in xor_xc_2()
23 "0: xc 0(256,%1),0(%2)\n" in xor_xc_2()
26 " brctg 0,0b\n" in xor_xc_2()
27 "1: ex %0,0(1)\n" in xor_xc_2()
29 "2: xc 0(1,%1),0(%2)\n" in xor_xc_2()
32 : "0", "1", "cc", "memory"); in xor_xc_2()
40 " aghi %0,-1\n" in xor_xc_3()
42 " srlg 0,%0,8\n" in xor_xc_3()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/thm/
Dthm_9_0_sh_mask.h27 …ON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0
28 …ON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5
29 …ON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7
30 …ON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8
31 …N_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10
32 …N_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12
33 …N_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13
34 …N_CUR_TMP__MCM_EN__SHIFT 0x14
35 …N_CUR_TMP__CUR_TEMP__SHIFT 0x15
36 …MP__PER_STEP_TIME_UP_MASK 0x0000001FL
[all …]
Dthm_10_0_sh_mask.h27 …ON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0
28 …ON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5
29 …ON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7
30 …ON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8
31 …N_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10
32 …N_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12
33 …N_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13
34 …N_CUR_TMP__MCM_EN__SHIFT 0x14
35 …N_CUR_TMP__CUR_TEMP__SHIFT 0x15
36 …MP__PER_STEP_TIME_UP_MASK 0x0000001FL
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/amd/include/asic_reg/thm/
Dthm_9_0_sh_mask.h27 …ON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0
28 …ON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5
29 …ON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7
30 …ON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8
31 …N_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10
32 …N_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12
33 …N_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13
34 …N_CUR_TMP__MCM_EN__SHIFT 0x14
35 …N_CUR_TMP__CUR_TEMP__SHIFT 0x15
36 …MP__PER_STEP_TIME_UP_MASK 0x0000001FL
[all …]
Dthm_10_0_sh_mask.h27 …ON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0
28 …ON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5
29 …ON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7
30 …ON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8
31 …N_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10
32 …N_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12
33 …N_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13
34 …N_CUR_TMP__MCM_EN__SHIFT 0x14
35 …N_CUR_TMP__CUR_TEMP__SHIFT 0x15
36 …MP__PER_STEP_TIME_UP_MASK 0x0000001FL
[all …]
/kernel/linux/linux-4.19/arch/powerpc/sysdev/xive/
Dcommon.c47 #define DBG_VERBOSE(fmt...) do { } while(0)
81 * or 0 if there is no new entry.
90 return 0; in xive_read_eq()
95 return 0; in xive_read_eq()
103 if (q->idx == 0) in xive_read_eq()
107 return cur & 0x7fffffff; in xive_read_eq()
117 * (0xff if none) and return what was found (0 if none).
133 static u32 xive_scan_interrupts(struct xive_cpu *xc, bool just_peek) in xive_scan_interrupts() argument
135 u32 irq = 0; in xive_scan_interrupts()
139 while (xc->pending_prio != 0) { in xive_scan_interrupts()
[all …]
/kernel/linux/linux-5.10/arch/powerpc/sysdev/xive/
Dcommon.c44 #define DBG_VERBOSE(fmt...) do { } while(0)
78 * or 0 if there is no new entry.
87 return 0; in xive_read_eq()
92 return 0; in xive_read_eq()
100 if (q->idx == 0) in xive_read_eq()
104 return cur & 0x7fffffff; in xive_read_eq()
114 * (0xff if none) and return what was found (0 if none).
130 static u32 xive_scan_interrupts(struct xive_cpu *xc, bool just_peek) in xive_scan_interrupts() argument
132 u32 irq = 0; in xive_scan_interrupts()
133 u8 prio = 0; in xive_scan_interrupts()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/mmhub/
Dmmhub_9_4_1_sh_mask.h27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
Dmmhub_9_3_0_sh_mask.h27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
Dmmhub_9_1_sh_mask.h27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
Dmmhub_1_0_sh_mask.h27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/amd/include/asic_reg/mmhub/
Dmmhub_1_0_sh_mask.h27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
Dmmhub_9_3_0_sh_mask.h27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
Dmmhub_9_1_sh_mask.h27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-netx/
Dxc.c2 * arch/arm/mach-netx/xc.c
32 #include <mach/xc.h>
36 static int xc_in_use = 0;
53 int xc_stop(struct xc *x) in xc_stop()
58 return 0; in xc_stop()
61 int xc_start(struct xc *x) in xc_start()
63 writel(0, x->xmac_base + NETX_XMAC_RPU_HOLD_PC_OFS); in xc_start()
64 writel(0, x->xmac_base + NETX_XMAC_TPU_HOLD_PC_OFS); in xc_start()
65 writel(0, x->xpec_base + NETX_XPEC_XPU_HOLD_PC_OFS); in xc_start()
66 return 0; in xc_start()
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/
Dnetx-eth.c35 #include <mach/xc.h>
38 /* XC Fifo Offsets */
39 #define EMPTY_PTR_FIFO(xcno) (0 + ((xcno) << 3)) /* Index of the empty pointer FIFO */
41 /* Data packages are indicated by XC */
43 /* Data packages are indicated by XC */
54 #define PFIFO_MASK(xcno) (0x7f << (xcno*8))
56 #define FIFO_PTR_FRAMELEN_SHIFT 0
57 #define FIFO_PTR_FRAMELEN_MASK (0x7ff << 0)
58 #define FIFO_PTR_FRAMELEN(len) (((len) << 0) & FIFO_PTR_FRAMELEN_MASK)
64 #define FIFO_PTR_FRAMENO_MASK (0x3f << 16)
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