| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/leds/backlight/ |
| D | pm8941-wled.txt | 8 - default-brightness: brightness value on boot, value from: 0-4095
14 - qcom,current-limit: mA; per-string current limit; value from 0 to 25
33 reg = <0xd800>;
|
| /kernel/linux/linux-5.10/drivers/staging/media/atomisp/i2c/ |
| D | mt9m114.h | 46 #define MISENSOR_FWBURST0 0x80
47 #define MISENSOR_FWBURST1 0x81
48 #define MISENSOR_FWBURST4 0x84
49 #define MISENSOR_FWBURST 0x88
51 #define MISENSOR_TOK_TERM 0xf000 /* terminating token for reg list */
52 #define MISENSOR_TOK_DELAY 0xfe00 /* delay token for reg list */
53 #define MISENSOR_TOK_FWLOAD 0xfd00 /* token indicating load FW */
54 #define MISENSOR_TOK_POLL 0xfc00 /* token indicating poll instruction */
55 #define MISENSOR_TOK_RMW 0x0010 /* RMW operation */
56 #define MISENSOR_TOK_MASK 0xfff0
[all …]
|
| /kernel/linux/linux-5.10/drivers/firmware/efi/libstub/ |
| D | vsprintf.c | 25 int i = 0; in skip_atoi()
28 i = i * 10 + *((*s)++) - '0'; in skip_atoi()
33 * put_dec_full4 handles numbers in the range 0 <= r < 10000.
34 * The multiplier 0xccd is round(2^15/10), and the approximation
35 * r/10 == (r * 0xccd) >> 15 is exact for all r < 16389.
42 for (i = 0; i < 3; i++) { in put_dec_full4()
43 unsigned int q = (r * 0xccd) >> 15; in put_dec_full4()
44 *--end = '0' + (r - q * 10); in put_dec_full4()
47 *--end = '0' + r; in put_dec_full4()
54 * The approximation x/10000 == (x * 0x346DC5D7) >> 43
[all …]
|
| D | efi-stub-helper.c | 54 * The position of the most-significant 0 bit gives us the length of in utf8_to_utf32()
57 for (clen = 0; cx & 0x80; ++clen) in utf8_to_utf32()
60 * If the 0 bit is in position 8, this is a valid single-octet in utf8_to_utf32()
61 * encoding. If the 0 bit is in position 7 or positions 1-3, the in utf8_to_utf32()
69 for (i = 0; i < clen; ++i) { in utf8_to_utf32()
71 cx = (*s8)[i] ^ 0x80; in utf8_to_utf32()
72 if (cx & 0xc0) in utf8_to_utf32()
82 if (c32 > 0x10ffff || in utf8_to_utf32()
83 (c32 & 0xf800) == 0xd800 || in utf8_to_utf32()
84 clen != (c32 >= 0x80) + (c32 >= 0x800) + (c32 >= 0x10000)) in utf8_to_utf32()
[all …]
|
| /kernel/linux/linux-5.10/drivers/staging/media/meson/vdec/ |
| D | hevc_regs.h | 9 #define HEVC_ASSIST_MMU_MAP_ADDR 0xc024
11 #define HEVC_ASSIST_MBOX1_CLR_REG 0xc1d4
12 #define HEVC_ASSIST_MBOX1_MASK 0xc1d8
14 #define HEVC_ASSIST_SCRATCH_0 0xc300
15 #define HEVC_ASSIST_SCRATCH_1 0xc304
16 #define HEVC_ASSIST_SCRATCH_2 0xc308
17 #define HEVC_ASSIST_SCRATCH_3 0xc30c
18 #define HEVC_ASSIST_SCRATCH_4 0xc310
19 #define HEVC_ASSIST_SCRATCH_5 0xc314
20 #define HEVC_ASSIST_SCRATCH_6 0xc318
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | qcom-pm8941.dtsi | 8 pm8941_0: pm8941@0 {
10 reg = <0x0 SPMI_USID>;
12 #size-cells = <0>;
16 reg = <0x6000>,
17 <0x6100>;
19 interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
24 reg = <0x800>;
25 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
32 reg = <0x900>;
33 interrupts = <0x0 0x9 0 IRQ_TYPE_EDGE_BOTH>;
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/leds/backlight/ |
| D | qcom-wled.yaml | 62 minimum: 0
69 minimum: 0
107 Array of the WLED strings numbered from 0 to 3. Each
144 0 - Modulator A
148 enum: [ 0, 1 ]
149 default: 0
155 0 - CABC disabled
161 enum: [ 0, 1, 2, 3 ]
215 minimum: 0
219 minimum: 0
[all …]
|
| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | qcom-pm8941.dtsi | 8 pm8941_0: pm8941@0 {
10 reg = <0x0 SPMI_USID>;
12 #size-cells = <0>;
16 reg = <0x6000>,
17 <0x6100>;
19 interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
24 reg = <0x800>;
25 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
32 reg = <0x900>;
33 interrupts = <0x0 0x9 0 IRQ_TYPE_EDGE_BOTH>;
[all …]
|
| /kernel/linux/linux-4.19/drivers/firmware/efi/libstub/ |
| D | efi-stub-helper.c | 64 efi_char16_t ch[2] = { 0 }; in efi_printk()
66 ch[0] = *s8; in efi_printk()
68 efi_char16_t nl[2] = { '\r', 0 }; in efi_printk()
102 *map->desc_size = 0; in efi_get_memory_map()
103 key = 0; in efi_get_memory_map()
181 u64 max_addr = 0; in efi_high_alloc()
208 for (i = 0; i < map_size / desc_size; i++) { in efi_high_alloc()
235 * Don't allocate at 0x0. It will confuse code that in efi_high_alloc()
238 if (start == 0x0) in efi_high_alloc()
253 max_addr = 0; in efi_high_alloc()
[all …]
|
| /kernel/linux/linux-4.19/drivers/net/wireless/mediatek/mt76/ |
| D | mt76x2u_init.c | 39 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(0) | BIT(16)); in mt76x2u_power_on_rf_patch()
42 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x1c), 0xff); in mt76x2u_power_on_rf_patch()
43 mt76_set(dev, MT_VEND_ADDR(CFG, 0x1c), 0x30); in mt76x2u_power_on_rf_patch()
45 mt76_wr(dev, MT_VEND_ADDR(CFG, 0x14), 0x484f); in mt76x2u_power_on_rf_patch()
48 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(17)); in mt76x2u_power_on_rf_patch()
51 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x130), BIT(16)); in mt76x2u_power_on_rf_patch()
54 mt76_set(dev, MT_VEND_ADDR(CFG, 0x14c), BIT(19) | BIT(20)); in mt76x2u_power_on_rf_patch()
59 int shift = unit ? 8 : 0; in mt76x2u_power_on_rf()
63 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(0) << shift); in mt76x2u_power_on_rf()
67 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), val); in mt76x2u_power_on_rf()
[all …]
|
| D | mt76x2_init.c | 36 mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f); in mt76x2_mac_pbf_init()
37 mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf); in mt76x2_mac_pbf_init()
44 s8 offset = 0; in mt76x2_fixup_xtal()
48 offset = eep_val & 0x7f; in mt76x2_fixup_xtal()
49 if ((eep_val & 0xff) == 0xff) in mt76x2_fixup_xtal()
50 offset = 0; in mt76x2_fixup_xtal()
51 else if (eep_val & 0x80) in mt76x2_fixup_xtal()
52 offset = 0 - offset; in mt76x2_fixup_xtal()
55 if (eep_val == 0x00 || eep_val == 0xff) { in mt76x2_fixup_xtal()
57 eep_val &= 0xff; in mt76x2_fixup_xtal()
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/mach-u300/ |
| D | core.c | 29 #define U300_NAND_CS0_PHYS_BASE 0x80000000
31 #define U300_NAND_IF_PHYS_BASE 0x9f800000
36 #define U300_AHB_PER_PHYS_BASE 0xa0000000
37 #define U300_AHB_PER_VIRT_BASE 0xff010000
39 #define U300_FAST_PER_PHYS_BASE 0xc0000000
40 #define U300_FAST_PER_VIRT_BASE 0xff020000
42 #define U300_SLOW_PER_PHYS_BASE 0xc0010000
43 #define U300_SLOW_PER_VIRT_BASE 0xff000000
45 #define U300_BOOTROM_PHYS_BASE 0xffff0000
46 #define U300_BOOTROM_VIRT_BASE 0xffff0000
[all …]
|
| /kernel/linux/linux-4.19/arch/arm/mach-u300/ |
| D | core.c | 30 #define U300_NAND_CS0_PHYS_BASE 0x80000000
32 #define U300_NAND_IF_PHYS_BASE 0x9f800000
37 #define U300_AHB_PER_PHYS_BASE 0xa0000000
38 #define U300_AHB_PER_VIRT_BASE 0xff010000
40 #define U300_FAST_PER_PHYS_BASE 0xc0000000
41 #define U300_FAST_PER_VIRT_BASE 0xff020000
43 #define U300_SLOW_PER_PHYS_BASE 0xc0010000
44 #define U300_SLOW_PER_VIRT_BASE 0xff000000
46 #define U300_BOOTROM_PHYS_BASE 0xffff0000
47 #define U300_BOOTROM_VIRT_BASE 0xffff0000
[all …]
|
| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/ |
| D | mpc8610_hpcd.dts | 26 #size-cells = <0>;
28 PowerPC,8610@0 {
30 reg = <0>;
35 sleep = <&pmc 0x00008000 0 // core
36 &pmc 0x00004000 0>; // timebase
37 timebase-frequency = <0>; // From uboot
38 bus-frequency = <0>; // From uboot
39 clock-frequency = <0>; // From uboot
45 reg = <0x00000000 0x20000000>; // 512M at 0x0
52 reg = <0xe0005000 0x1000>;
[all …]
|
| /kernel/linux/linux-4.19/arch/powerpc/boot/dts/ |
| D | mpc8610_hpcd.dts | 29 #size-cells = <0>;
31 PowerPC,8610@0 {
33 reg = <0>;
38 sleep = <&pmc 0x00008000 0 // core
39 &pmc 0x00004000 0>; // timebase
40 timebase-frequency = <0>; // From uboot
41 bus-frequency = <0>; // From uboot
42 clock-frequency = <0>; // From uboot
48 reg = <0x00000000 0x20000000>; // 512M at 0x0
55 reg = <0xe0005000 0x1000>;
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt7601u/ |
| D | init.c | 94 mt7601u_wr(dev, MT_USB_DMA_CFG, 0); in mt7601u_reset_csr_bbp()
96 mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0); in mt7601u_reset_csr_bbp()
142 for (i = 0; i < 16; i++) { in mt76_init_beacon_offsets()
148 for (i = 0; i < 4; i++) in mt76_init_beacon_offsets()
167 mt7601u_wr(dev, MT_AUX_CLK_CFG, 0); in mt7601u_write_mac_initvals()
169 return 0; in mt7601u_write_mac_initvals()
181 for (i = 0; i < N_WCIDS; i++) { in mt7601u_init_wcid_mem()
182 vals[i * 2] = 0xffffffff; in mt7601u_init_wcid_mem()
183 vals[i * 2 + 1] = 0x00ffffff; in mt7601u_init_wcid_mem()
210 for (i = 0; i < N_WCIDS * 2; i++) in mt7601u_init_wcid_attr_mem()
[all …]
|
| /kernel/linux/linux-4.19/drivers/net/wireless/mediatek/mt7601u/ |
| D | init.c | 102 mt7601u_wr(dev, MT_USB_DMA_CFG, 0); in mt7601u_reset_csr_bbp()
104 mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0); in mt7601u_reset_csr_bbp()
150 for (i = 0; i < 16; i++) { in mt76_init_beacon_offsets()
156 for (i = 0; i < 4; i++) in mt76_init_beacon_offsets()
175 mt7601u_wr(dev, MT_AUX_CLK_CFG, 0); in mt7601u_write_mac_initvals()
177 return 0; in mt7601u_write_mac_initvals()
189 for (i = 0; i < N_WCIDS; i++) { in mt7601u_init_wcid_mem()
190 vals[i * 2] = 0xffffffff; in mt7601u_init_wcid_mem()
191 vals[i * 2 + 1] = 0x00ffffff; in mt7601u_init_wcid_mem()
218 for (i = 0; i < N_WCIDS * 2; i++) in mt7601u_init_wcid_attr_mem()
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/panel/ |
| D | panel-orisetech-otm8009a.c | 25 #define MCS_ADRSFT 0x0000 /* Address Shift Function */
26 #define MCS_PANSET 0xB3A6 /* Panel Type Setting */
27 #define MCS_SD_CTRL 0xC0A2 /* Source Driver Timing Setting */
28 #define MCS_P_DRV_M 0xC0B4 /* Panel Driving Mode */
29 #define MCS_OSC_ADJ 0xC181 /* Oscillator Adjustment for Idle/Normal mode */
30 #define MCS_RGB_VID_SET 0xC1A1 /* RGB Video Mode Setting */
31 #define MCS_SD_PCH_CTRL 0xC480 /* Source Driver Precharge Control */
32 #define MCS_NO_DOC1 0xC48A /* Command not documented */
33 #define MCS_PWR_CTRL1 0xC580 /* Power Control Setting 1 */
34 #define MCS_PWR_CTRL2 0xC590 /* Power Control Setting 2 for Normal Mode */
[all …]
|
| /kernel/linux/linux-4.19/drivers/gpu/drm/panel/ |
| D | panel-orisetech-otm8009a.c | 21 #define MCS_ADRSFT 0x0000 /* Address Shift Function */
22 #define MCS_PANSET 0xB3A6 /* Panel Type Setting */
23 #define MCS_SD_CTRL 0xC0A2 /* Source Driver Timing Setting */
24 #define MCS_P_DRV_M 0xC0B4 /* Panel Driving Mode */
25 #define MCS_OSC_ADJ 0xC181 /* Oscillator Adjustment for Idle/Normal mode */
26 #define MCS_RGB_VID_SET 0xC1A1 /* RGB Video Mode Setting */
27 #define MCS_SD_PCH_CTRL 0xC480 /* Source Driver Precharge Control */
28 #define MCS_NO_DOC1 0xC48A /* Command not documented */
29 #define MCS_PWR_CTRL1 0xC580 /* Power Control Setting 1 */
30 #define MCS_PWR_CTRL2 0xC590 /* Power Control Setting 2 for Normal Mode */
[all …]
|
| /kernel/linux/linux-4.19/drivers/gpu/drm/amd/amdgpu/ |
| D | cikd.h | 27 #define MC_SEQ_MISC0__MT__MASK 0xf0000000
28 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000
29 #define MC_SEQ_MISC0__MT__DDR2 0x20000000
30 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000
31 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000
32 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000
33 #define MC_SEQ_MISC0__MT__HBM 0x60000000
34 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000
39 #define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c)
40 #define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c)
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | cikd.h | 27 #define MC_SEQ_MISC0__MT__MASK 0xf0000000
28 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000
29 #define MC_SEQ_MISC0__MT__DDR2 0x20000000
30 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000
31 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000
32 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000
33 #define MC_SEQ_MISC0__MT__HBM 0x60000000
34 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000
39 #define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c)
40 #define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c)
[all …]
|
| /kernel/linux/linux-4.19/drivers/net/wireless/mediatek/mt76/mt76x0/ |
| D | init.c | 101 val &= ~0x2000; in mt76x0_reset_csr_bbp()
149 for (i = 0; i < ARRAY_SIZE(mt76x0_bbp_switch_tab); i++) { in mt76x0_init_bbp()
159 return 0; in mt76x0_init_bbp()
169 for (i = 0; i < 16; i++) { in mt76_init_beacon_offsets()
175 for (i = 0; i < 4; i++) in mt76_init_beacon_offsets()
187 /* Enable PBF and MAC clock SYS_CTRL[11:10] = 0x3 */ in mt76x0_init_mac_registers()
190 /* Release BBP and MAC reset MAC_SYS_CTRL[1:0] = 0x0 */ in mt76x0_init_mac_registers()
192 reg &= ~0x3; in mt76x0_init_mac_registers()
198 reg &= 0xFFFFFFFE; in mt76x0_init_mac_registers()
202 /* Set 0x141C[15:12]=0xF */ in mt76x0_init_mac_registers()
[all …]
|
| /kernel/linux/linux-5.10/fs/unicode/ |
| D | mkutf8data.c | 50 int verbose = 0;
63 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
98 return 0; in age_valid()
100 return 0; in age_valid()
102 return 0; in age_valid()
119 * if offlen == 0 (non-branching node)
124 * if offlen != 0 (branching node)
133 #define BITNUM 0x07
134 #define NEXTBYTE 0x08
135 #define OFFLEN 0x30
[all …]
|
| D | utf8-norm.c | 23 while (i >= 0 && utf8agetab[i] != 0) { in utf8version_is_supported()
28 return 0; in utf8version_is_supported()
45 * 0x00000000 0x0000007F: 0xxxxxxx
46 * 0x00000000 0x000007FF: 110xxxxx 10xxxxxx
47 * 0x00000000 0x0000FFFF: 1110xxxx 10xxxxxx 10xxxxxx
48 * 0x00000000 0x001FFFFF: 11110xxx 10xxxxxx 10xxxxxx 10xxxxxx
49 * 0x00000000 0x03FFFFFF: 111110xx 10xxxxxx 10xxxxxx 10xxxxxx 10xxxxxx
50 * 0x00000000 0x7FFFFFFF: 1111110x 10xxxxxx 10xxxxxx 10xxxxxx 10xxxxxx 10xxxxxx
57 * 0x00000000 0x0000007F: 0xxxxxxx
58 * 0x00000080 0x000007FF: 110xxxxx 10xxxxxx
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/ethernet/realtek/ |
| D | r8169_phy_config.c | 23 int oldpage = phy_select_page(phydev, 0x0007); in r8168d_modify_extpage()
25 __phy_write(phydev, 0x1e, extpage); in r8168d_modify_extpage()
28 phy_restore_page(phydev, oldpage, 0); in r8168d_modify_extpage()
34 int oldpage = phy_select_page(phydev, 0x0005); in r8168d_phy_param()
36 __phy_write(phydev, 0x05, parm); in r8168d_phy_param()
37 __phy_modify(phydev, 0x06, mask, val); in r8168d_phy_param()
39 phy_restore_page(phydev, oldpage, 0); in r8168d_phy_param()
45 int oldpage = phy_select_page(phydev, 0x0a43); in r8168g_phy_param()
47 __phy_write(phydev, 0x13, parm); in r8168g_phy_param()
48 __phy_modify(phydev, 0x14, mask, val); in r8168g_phy_param()
[all …]
|