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12

/kernel/linux/linux-4.19/arch/unicore32/include/mach/
DPKUnity.h23 #define PKUNITY_SDRAM_BASE 0x00000000 /* 0x00000000 - 0x7FFFFFFF 2GB */
24 #define PKUNITY_MMIO_BASE 0x80000000 /* 0x80000000 - 0xFFFFFFFF 2GB */
27 * PKUNITY System Bus Addresses (PCI): 0x80000000 - 0xBFFFFFFF (1GB)
28 * 0x80000000 - 0x8000000B 12B PCI Configuration regs
29 * 0x80010000 - 0x80010250 592B PCI Bridge Base
30 * 0x80030000 - 0x8003FFFF 64KB PCI Legacy IO
31 * 0x90000000 - 0x97FFFFFF 128MB PCI AHB-PCI MEM-mapping
32 * 0x98000000 - 0x9FFFFFFF 128MB PCI PCI-AHB MEM-mapping
34 #define PKUNITY_PCI_BASE io_p2v(0x80000000) /* 0x80000000 - 0xBFFFFFFF 1GB */
37 #define PKUNITY_PCICFG_BASE (PKUNITY_PCI_BASE + 0x0)
[all …]
/kernel/linux/linux-4.19/arch/unicore32/kernel/
Ddebug-macro.S18 1001: movc \rx, p1.c0, #0
48 mrc p0, #0, \rx, c1, c0
50 moveq \rx, #0xee000000 @ physical base address
51 movne \rx, #0x6e000000 @ virtual address
58 mov r1, #0x80
60 and r1, r2, #0xff00
63 and r1, r2, #0xff
65 mov r1, #0x7
67 mov r1, #0x3
69 mov r1, #0x0
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/memory-controllers/fsl/
Difc.txt37 reg = <0x0 0xffe1e000 0 0x2000>;
42 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
43 0x1 0x0 0x0 0xffa00000 0x00010000
44 0x3 0x0 0x0 0xffb00000 0x00020000>;
46 flash@0,0 {
50 reg = <0x0 0x0 0x2000000>;
54 partition@0 {
56 reg = <0x0 0x02000000>;
61 flash@1,0 {
65 reg = <0x1 0x0 0x10000>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/fsl/
Difc.txt37 reg = <0x0 0xffe1e000 0 0x2000>;
42 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
43 0x1 0x0 0x0 0xffa00000 0x00010000
44 0x3 0x0 0x0 0xffb00000 0x00020000>;
46 flash@0,0 {
50 reg = <0x0 0x0 0x2000000>;
54 partition@0 {
56 reg = <0x0 0x02000000>;
61 flash@1,0 {
65 reg = <0x1 0x0 0x10000>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/
Drenesas,usb-xhci.yaml82 reg = <0xee000000 0xc00>;
/kernel/linux/linux-4.19/arch/powerpc/boot/dts/fsl/
Dp1010rdb_36b.dtsi41 ranges = <0x0 0x0 0xf 0xee000000 0x02000000
42 0x1 0x0 0xf 0xff800000 0x00010000
43 0x3 0x0 0xf 0xffb00000 0x00000020>;
44 reg = <0xf 0xffe1e000 0 0x2000>;
48 ranges = <0x0 0xf 0xffe00000 0x100000>;
52 reg = <0xf 0xffe09000 0 0x1000>;
53 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
54 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
55 pcie@0 {
56 ranges = <0x2000000 0x0 0xc0000000
[all …]
Dp1010rdb_32b.dtsi41 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
42 0x1 0x0 0x0 0xff800000 0x00010000
43 0x3 0x0 0x0 0xffb00000 0x00000020>;
44 reg = <0x0 0xffe1e000 0 0x2000>;
48 ranges = <0x0 0x0 0xffe00000 0x100000>;
52 reg = <0 0xffe09000 0 0x1000>;
53 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
54 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
55 pcie@0 {
56 ranges = <0x2000000 0x0 0xa0000000
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/
Dp1010rdb_36b.dtsi41 ranges = <0x0 0x0 0xf 0xee000000 0x02000000
42 0x1 0x0 0xf 0xff800000 0x00010000
43 0x3 0x0 0xf 0xffb00000 0x00000020>;
44 reg = <0xf 0xffe1e000 0 0x2000>;
48 ranges = <0x0 0xf 0xffe00000 0x100000>;
52 reg = <0xf 0xffe09000 0 0x1000>;
53 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
54 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
55 pcie@0 {
56 ranges = <0x2000000 0x0 0xc0000000
[all …]
Dp1010rdb_32b.dtsi41 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
42 0x1 0x0 0x0 0xff800000 0x00010000
43 0x3 0x0 0x0 0xffb00000 0x00000020>;
44 reg = <0x0 0xffe1e000 0 0x2000>;
48 ranges = <0x0 0x0 0xffe00000 0x100000>;
52 reg = <0 0xffe09000 0 0x1000>;
53 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
54 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
55 pcie@0 {
56 ranges = <0x2000000 0x0 0xa0000000
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-pxa/
Dpcm990_baseboard.h29 #define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */
30 #define PCM990_CTRL_SYSRES 0x0001 /* System RESET REGISTER */
31 #define PCM990_CTRL_RESOUT 0x0002 /* RESETOUT Enable REGISTER */
32 #define PCM990_CTRL_RESGPIO 0x0004 /* RESETGPIO Enable REGISTER */
34 #define PCM990_CTRL_REG1 0x0002 /* Power REGISTER */
35 #define PCM990_CTRL_5VOFF 0x0001 /* Disable 5V Regulators */
36 #define PCM990_CTRL_CANPWR 0x0004 /* Enable CANPWR ADUM */
37 #define PCM990_CTRL_PM_5V 0x0008 /* Read 5V OK */
39 #define PCM990_CTRL_REG2 0x0004 /* LED REGISTER */
40 #define PCM990_CTRL_LEDPWR 0x0001 /* POWER LED enable */
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-pxa/
Dpcm990_baseboard.h42 #define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */
43 #define PCM990_CTRL_SYSRES 0x0001 /* System RESET REGISTER */
44 #define PCM990_CTRL_RESOUT 0x0002 /* RESETOUT Enable REGISTER */
45 #define PCM990_CTRL_RESGPIO 0x0004 /* RESETGPIO Enable REGISTER */
47 #define PCM990_CTRL_REG1 0x0002 /* Power REGISTER */
48 #define PCM990_CTRL_5VOFF 0x0001 /* Disable 5V Regulators */
49 #define PCM990_CTRL_CANPWR 0x0004 /* Enable CANPWR ADUM */
50 #define PCM990_CTRL_PM_5V 0x0008 /* Read 5V OK */
52 #define PCM990_CTRL_REG2 0x0004 /* LED REGISTER */
53 #define PCM990_CTRL_LEDPWR 0x0001 /* POWER LED enable */
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/renesas/
Dr8a77990.dtsi19 #size-cells = <0>;
21 a53_0: cpu@0 {
23 reg = <0>;
39 L2_CA53: cache-controller-0 {
49 #clock-cells = <0>;
51 clock-frequency = <0>;
76 reg = <0 0xe6020000 0 0x0c>;
86 reg = <0 0xe6050000 0 0x50>;
90 gpio-ranges = <&pfc 0 0 18>;
101 reg = <0 0xe6051000 0 0x50>;
[all …]
Dr8a77965.dtsi34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
46 #clock-cells = <0>;
47 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
59 #clock-cells = <0>;
60 clock-frequency = <0>;
65 #size-cells = <0>;
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/ti/
Dnetcp_xgbepcsr.c13 #define XGBE_CTRL_OFFSET 0x0c
14 #define XGBE_SGMII_1_OFFSET 0x0114
15 #define XGBE_SGMII_2_OFFSET 0x0214
18 #define PCSR_CPU_CTRL_OFFSET 0x1fd0
31 #define PHY_A(serdes) 0
40 {0x0000, 0x00800002, 0x00ff00ff},
41 {0x0014, 0x00003838, 0x0000ffff},
42 {0x0060, 0x1c44e438, 0xffffffff},
43 {0x0064, 0x00c18400, 0x00ffffff},
44 {0x0068, 0x17078200, 0xffffff00},
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/ti/
Dnetcp_xgbepcsr.c20 #define XGBE_CTRL_OFFSET 0x0c
21 #define XGBE_SGMII_1_OFFSET 0x0114
22 #define XGBE_SGMII_2_OFFSET 0x0214
25 #define PCSR_CPU_CTRL_OFFSET 0x1fd0
38 #define PHY_A(serdes) 0
47 {0x0000, 0x00800002, 0x00ff00ff},
48 {0x0014, 0x00003838, 0x0000ffff},
49 {0x0060, 0x1c44e438, 0xffffffff},
50 {0x0064, 0x00c18400, 0x00ffffff},
51 {0x0068, 0x17078200, 0xffffff00},
[all …]
/kernel/linux/linux-5.10/crypto/
Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]
/kernel/linux/linux-4.19/crypto/
Daes_generic.c68 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
69 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
70 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
71 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
72 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
73 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
74 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
75 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
76 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
77 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/via/
Dvia_3d_reg.h27 #define HC_REG_BASE 0x0400
29 #define HC_REG_TRANS_SPACE 0x0040
31 #define HC_ParaN_MASK 0xffffffff
32 #define HC_Para_MASK 0x00ffffff
33 #define HC_SubA_MASK 0xff000000
37 #define HC_REG_TRANS_SET 0x003c
38 #define HC_ParaSubType_MASK 0xff000000
39 #define HC_ParaType_MASK 0x00ff0000
40 #define HC_ParaOS_MASK 0x0000ff00
41 #define HC_ParaAdr_MASK 0x000000ff
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/via/
Dvia_3d_reg.h27 #define HC_REG_BASE 0x0400
29 #define HC_REG_TRANS_SPACE 0x0040
31 #define HC_ParaN_MASK 0xffffffff
32 #define HC_Para_MASK 0x00ffffff
33 #define HC_SubA_MASK 0xff000000
37 #define HC_REG_TRANS_SET 0x003c
38 #define HC_ParaSubType_MASK 0xff000000
39 #define HC_ParaType_MASK 0x00ff0000
40 #define HC_ParaOS_MASK 0x0000ff00
41 #define HC_ParaAdr_MASK 0x000000ff
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dr8a7743.dtsi38 * The external audio clocks are configured as 0 Hz fixed frequency
44 #clock-cells = <0>;
45 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
Dr8a7791.dtsi40 * The external audio clocks are configured as 0 Hz fixed frequency
46 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
52 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dr8a7742.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
35 #clock-cells = <0>;
36 clock-frequency = <0>;
42 #clock-cells = <0>;
44 clock-frequency = <0>;
49 #size-cells = <0>;
[all …]
Dr8a7791.dtsi40 * The external audio clocks are configured as 0 Hz fixed frequency
46 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
52 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
Dr8a7743.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
51 #size-cells = <0>;
[all …]
Dr8a7744.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
51 #size-cells = <0>;
[all …]

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