Searched +full:1 +full:c20000 (Results 1 – 25 of 48) sorted by relevance
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26 maxItems: 129 maxItems: 132 maxItems: 145 clk@1c20000 {54 clk@1c20000 {63 clk@1c20000 {
13 - #clock-cells: should be 1.24 Example 1: An example of a clock controller node is listed below.36 #clock-cells = <1>;44 serial@12c20000 {
15 const: 118 const: 148 maxItems: 1128 ccu: clock@1c20000 {133 #clock-cells = <1>;134 #reset-cells = <1>;138 r_ccu: clock@1f01400 {143 #clock-cells = <1>;144 #reset-cells = <1>;
33 - #clock-cells : must contain 134 - #reset-cells : must contain 144 ccu: clock@1c20000 {49 #clock-cells = <1>;50 #reset-cells = <1>;54 r_ccu: clock@1f01400 {59 #clock-cells = <1>;60 #reset-cells = <1>;
3 This binding uses the common clock binding[1].5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt80 "allwinner,sun4i-a10-tcon-ch1-clk" - for the TCON channel 1 clock on the A1097 the following compatibles where it shall be set to 1:107 - reset-cells : shall be set to 1113 - #reset-cells : shall be set to 1123 For the other clocks with "#clock-cells" = 1, the additional ID shall132 IDs 1 and 2, respectively.140 osc24M: clk@1c20050 {148 pll1: clk@1c20000 {[all …]
56 dmc: memory-controller@10c20000 {82 interrupts = <16 0>, <16 1>;
8 #address-cells = <1>;9 #size-cells = <1>;37 #address-cells = <1>;38 #size-cells = <1>;41 sram-controller@1c00000 {45 #address-cells = <1>;46 #size-cells = <1>;52 #address-cells = <1>;53 #size-cells = <1>;65 ccu: clock@1c20000 {[all …]
18 #address-cells = <1>;19 #size-cells = <1>;34 #address-cells = <1>;35 #size-cells = <1>;55 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,117 serial_2: serial@12c20000 {133 #address-cells = <1>;143 #address-cells = <1>;153 #address-cells = <1>;163 #address-cells = <1>;[all …]
16 #address-cells = <1>;17 #size-cells = <1>;34 #address-cells = <1>;44 cpu@1 {82 #address-cells = <1>;83 #size-cells = <1>;89 #clock-cells = <1>;95 #clock-cells = <1>;101 #clock-cells = <1>;107 #clock-cells = <1>;[all …]
49 #address-cells = <1>;50 #size-cells = <1>;54 #address-cells = <1>;55 #size-cells = <1>;69 #address-cells = <1>;95 #address-cells = <1>;96 #size-cells = <1>;118 #address-cells = <1>;119 #size-cells = <1>;130 #clock-cells = <1>;[all …]
51 #address-cells = <1>;52 #size-cells = <1>;55 #address-cells = <1>;67 #address-cells = <1>;68 #size-cells = <1>;92 #address-cells = <1>;93 #size-cells = <1>;112 #address-cells = <1>;113 #size-cells = <1>;128 #address-cells = <1>;[all …]
16 #address-cells = <1>;17 #size-cells = <1>;30 #address-cells = <1>;40 cpu@1 {78 #address-cells = <1>;79 #size-cells = <1>;85 #clock-cells = <1>;91 #clock-cells = <1>;97 #clock-cells = <1>;103 #clock-cells = <1>;[all …]
48 #address-cells = <1>;49 #size-cells = <1>;53 #address-cells = <1>;79 #address-cells = <1>;80 #size-cells = <1>;100 #address-cells = <1>;101 #size-cells = <1>;112 #clock-cells = <1>;113 #reset-cells = <1>;128 #address-cells = <1>;[all …]
56 #address-cells = <1>;57 #size-cells = <1>;83 #address-cells = <1>;92 cpu@1 {95 reg = <1>;100 #address-cells = <1>;101 #size-cells = <1>;121 soc@1c00000 {123 #address-cells = <1>;124 #size-cells = <1>;[all …]
51 #address-cells = <1>;52 #size-cells = <1>;56 #address-cells = <1>;57 #size-cells = <1>;76 #address-cells = <1>;85 cpu@1 {88 reg = <1>;112 #address-cells = <1>;113 #size-cells = <1>;125 #clock-cells = <1>;[all …]
55 #address-cells = <1>;67 #address-cells = <1>;68 #size-cells = <1>;80 framebuffer@1 {92 #address-cells = <1>;93 #size-cells = <1>;96 osc24M: clk@1c20050 {111 soc@1c00000 {113 #address-cells = <1>;114 #size-cells = <1>;[all …]
44 interrupts = <16 2 1 20>;53 cell-index = <1>;241 interrupts = <16 2 1 9>;261 /include/ "qoriq-fman3-0-1g-4.dtsi"262 /include/ "qoriq-fman3-0-1g-5.dtsi"264 /include/ "qoriq-fman3-0-10g-1.dtsi"279 L2_1: l2-cache-controller@c20000 {
53 cpu@1 {156 #address-cells = <1>;157 #size-cells = <1>;169 #address-cells = <1>;170 #size-cells = <1>;177 gic_its: gic-its@63c20000 {180 #msi-cells = <1>;188 #global-interrupts = <1>;260 #address-cells = <1>;261 #size-cells = <1>;[all …]
32 #address-cells = <1>;42 cpu_atlas1: cpu@1 {71 #address-cells = <1>;72 #size-cells = <1>;99 #address-cells = <1>;100 #size-cells = <1>;109 #dma-cells = <1>;120 #dma-cells = <1>;129 #clock-cells = <1>;135 #clock-cells = <1>;[all …]
49 #address-cells = <1>;59 cpu_atlas1: cpu@1 {90 #address-cells = <1>;91 #size-cells = <1>;116 #dma-cells = <1>;127 #dma-cells = <1>;135 #clock-cells = <1>;141 #clock-cells = <1>;154 #clock-cells = <1>;167 #clock-cells = <1>;[all …]
55 #address-cells = <1>;56 #size-cells = <1>;59 #address-cells = <1>;60 #size-cells = <1>;83 #address-cells = <1>;93 cpu1: cpu@1 {96 reg = <1>;174 #address-cells = <1>;175 #size-cells = <1>;181 allwinner,sram = <&de2_sram 1>;[all …]