1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/clock/sun8i-de2.h> 47#include <dt-bindings/clock/sun8i-r-ccu.h> 48#include <dt-bindings/interrupt-controller/arm-gic.h> 49#include <dt-bindings/reset/sun50i-a64-ccu.h> 50#include <dt-bindings/reset/sun8i-de2.h> 51#include <dt-bindings/reset/sun8i-r-ccu.h> 52 53/ { 54 interrupt-parent = <&gic>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 58 chosen { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 63 simplefb_lcd: framebuffer-lcd { 64 compatible = "allwinner,simple-framebuffer", 65 "simple-framebuffer"; 66 allwinner,pipeline = "mixer0-lcd0"; 67 clocks = <&ccu CLK_TCON0>, 68 <&display_clocks CLK_MIXER0>; 69 status = "disabled"; 70 }; 71 72 simplefb_hdmi: framebuffer-hdmi { 73 compatible = "allwinner,simple-framebuffer", 74 "simple-framebuffer"; 75 allwinner,pipeline = "mixer1-lcd1-hdmi"; 76 clocks = <&display_clocks CLK_MIXER1>, 77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 78 status = "disabled"; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 cpu0: cpu@0 { 87 compatible = "arm,cortex-a53", "arm,armv8"; 88 device_type = "cpu"; 89 reg = <0>; 90 enable-method = "psci"; 91 }; 92 93 cpu1: cpu@1 { 94 compatible = "arm,cortex-a53", "arm,armv8"; 95 device_type = "cpu"; 96 reg = <1>; 97 enable-method = "psci"; 98 }; 99 100 cpu2: cpu@2 { 101 compatible = "arm,cortex-a53", "arm,armv8"; 102 device_type = "cpu"; 103 reg = <2>; 104 enable-method = "psci"; 105 }; 106 107 cpu3: cpu@3 { 108 compatible = "arm,cortex-a53", "arm,armv8"; 109 device_type = "cpu"; 110 reg = <3>; 111 enable-method = "psci"; 112 }; 113 }; 114 115 osc24M: osc24M_clk { 116 #clock-cells = <0>; 117 compatible = "fixed-clock"; 118 clock-frequency = <24000000>; 119 clock-output-names = "osc24M"; 120 }; 121 122 osc32k: osc32k_clk { 123 #clock-cells = <0>; 124 compatible = "fixed-clock"; 125 clock-frequency = <32768>; 126 clock-output-names = "osc32k"; 127 }; 128 129 iosc: internal-osc-clk { 130 #clock-cells = <0>; 131 compatible = "fixed-clock"; 132 clock-frequency = <16000000>; 133 clock-accuracy = <300000000>; 134 clock-output-names = "iosc"; 135 }; 136 137 psci { 138 compatible = "arm,psci-0.2"; 139 method = "smc"; 140 }; 141 142 sound_spdif { 143 compatible = "simple-audio-card"; 144 simple-audio-card,name = "On-board SPDIF"; 145 146 simple-audio-card,cpu { 147 sound-dai = <&spdif>; 148 }; 149 150 simple-audio-card,codec { 151 sound-dai = <&spdif_out>; 152 }; 153 }; 154 155 spdif_out: spdif-out { 156 #sound-dai-cells = <0>; 157 compatible = "linux,spdif-dit"; 158 }; 159 160 timer { 161 compatible = "arm,armv8-timer"; 162 interrupts = <GIC_PPI 13 163 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 164 <GIC_PPI 14 165 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 166 <GIC_PPI 11 167 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 168 <GIC_PPI 10 169 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 170 }; 171 172 soc { 173 compatible = "simple-bus"; 174 #address-cells = <1>; 175 #size-cells = <1>; 176 ranges; 177 178 de2@1000000 { 179 compatible = "allwinner,sun50i-a64-de2"; 180 reg = <0x1000000 0x400000>; 181 allwinner,sram = <&de2_sram 1>; 182 #address-cells = <1>; 183 #size-cells = <1>; 184 ranges = <0 0x1000000 0x400000>; 185 186 display_clocks: clock@0 { 187 compatible = "allwinner,sun50i-a64-de2-clk"; 188 reg = <0x0 0x100000>; 189 clocks = <&ccu CLK_DE>, 190 <&ccu CLK_BUS_DE>; 191 clock-names = "mod", 192 "bus"; 193 resets = <&ccu RST_BUS_DE>; 194 #clock-cells = <1>; 195 #reset-cells = <1>; 196 }; 197 }; 198 199 syscon: syscon@1c00000 { 200 compatible = "allwinner,sun50i-a64-system-control"; 201 reg = <0x01c00000 0x1000>; 202 #address-cells = <1>; 203 #size-cells = <1>; 204 ranges; 205 206 sram_c: sram@18000 { 207 compatible = "mmio-sram"; 208 reg = <0x00018000 0x28000>; 209 #address-cells = <1>; 210 #size-cells = <1>; 211 ranges = <0 0x00018000 0x28000>; 212 213 de2_sram: sram-section@0 { 214 compatible = "allwinner,sun50i-a64-sram-c"; 215 reg = <0x0000 0x28000>; 216 }; 217 }; 218 }; 219 220 dma: dma-controller@1c02000 { 221 compatible = "allwinner,sun50i-a64-dma"; 222 reg = <0x01c02000 0x1000>; 223 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 224 clocks = <&ccu CLK_BUS_DMA>; 225 dma-channels = <8>; 226 dma-requests = <27>; 227 resets = <&ccu RST_BUS_DMA>; 228 #dma-cells = <1>; 229 }; 230 231 mmc0: mmc@1c0f000 { 232 compatible = "allwinner,sun50i-a64-mmc"; 233 reg = <0x01c0f000 0x1000>; 234 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 235 clock-names = "ahb", "mmc"; 236 resets = <&ccu RST_BUS_MMC0>; 237 reset-names = "ahb"; 238 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 239 max-frequency = <150000000>; 240 status = "disabled"; 241 #address-cells = <1>; 242 #size-cells = <0>; 243 }; 244 245 mmc1: mmc@1c10000 { 246 compatible = "allwinner,sun50i-a64-mmc"; 247 reg = <0x01c10000 0x1000>; 248 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 249 clock-names = "ahb", "mmc"; 250 resets = <&ccu RST_BUS_MMC1>; 251 reset-names = "ahb"; 252 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 253 max-frequency = <150000000>; 254 status = "disabled"; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 }; 258 259 mmc2: mmc@1c11000 { 260 compatible = "allwinner,sun50i-a64-emmc"; 261 reg = <0x01c11000 0x1000>; 262 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 263 clock-names = "ahb", "mmc"; 264 resets = <&ccu RST_BUS_MMC2>; 265 reset-names = "ahb"; 266 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 267 max-frequency = <200000000>; 268 status = "disabled"; 269 #address-cells = <1>; 270 #size-cells = <0>; 271 }; 272 273 usb_otg: usb@1c19000 { 274 compatible = "allwinner,sun8i-a33-musb"; 275 reg = <0x01c19000 0x0400>; 276 clocks = <&ccu CLK_BUS_OTG>; 277 resets = <&ccu RST_BUS_OTG>; 278 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 279 interrupt-names = "mc"; 280 phys = <&usbphy 0>; 281 phy-names = "usb"; 282 extcon = <&usbphy 0>; 283 status = "disabled"; 284 }; 285 286 usbphy: phy@1c19400 { 287 compatible = "allwinner,sun50i-a64-usb-phy"; 288 reg = <0x01c19400 0x14>, 289 <0x01c1a800 0x4>, 290 <0x01c1b800 0x4>; 291 reg-names = "phy_ctrl", 292 "pmu0", 293 "pmu1"; 294 clocks = <&ccu CLK_USB_PHY0>, 295 <&ccu CLK_USB_PHY1>; 296 clock-names = "usb0_phy", 297 "usb1_phy"; 298 resets = <&ccu RST_USB_PHY0>, 299 <&ccu RST_USB_PHY1>; 300 reset-names = "usb0_reset", 301 "usb1_reset"; 302 status = "disabled"; 303 #phy-cells = <1>; 304 }; 305 306 ehci0: usb@1c1a000 { 307 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 308 reg = <0x01c1a000 0x100>; 309 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&ccu CLK_BUS_OHCI0>, 311 <&ccu CLK_BUS_EHCI0>, 312 <&ccu CLK_USB_OHCI0>; 313 resets = <&ccu RST_BUS_OHCI0>, 314 <&ccu RST_BUS_EHCI0>; 315 status = "disabled"; 316 }; 317 318 ohci0: usb@1c1a400 { 319 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 320 reg = <0x01c1a400 0x100>; 321 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&ccu CLK_BUS_OHCI0>, 323 <&ccu CLK_USB_OHCI0>; 324 resets = <&ccu RST_BUS_OHCI0>; 325 status = "disabled"; 326 }; 327 328 ehci1: usb@1c1b000 { 329 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 330 reg = <0x01c1b000 0x100>; 331 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&ccu CLK_BUS_OHCI1>, 333 <&ccu CLK_BUS_EHCI1>, 334 <&ccu CLK_USB_OHCI1>; 335 resets = <&ccu RST_BUS_OHCI1>, 336 <&ccu RST_BUS_EHCI1>; 337 phys = <&usbphy 1>; 338 phy-names = "usb"; 339 status = "disabled"; 340 }; 341 342 ohci1: usb@1c1b400 { 343 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 344 reg = <0x01c1b400 0x100>; 345 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&ccu CLK_BUS_OHCI1>, 347 <&ccu CLK_USB_OHCI1>; 348 resets = <&ccu RST_BUS_OHCI1>; 349 phys = <&usbphy 1>; 350 phy-names = "usb"; 351 status = "disabled"; 352 }; 353 354 ccu: clock@1c20000 { 355 compatible = "allwinner,sun50i-a64-ccu"; 356 reg = <0x01c20000 0x400>; 357 clocks = <&osc24M>, <&osc32k>; 358 clock-names = "hosc", "losc"; 359 #clock-cells = <1>; 360 #reset-cells = <1>; 361 }; 362 363 pio: pinctrl@1c20800 { 364 compatible = "allwinner,sun50i-a64-pinctrl"; 365 reg = <0x01c20800 0x400>; 366 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&ccu 58>, <&osc24M>, <&rtc 0>; 370 clock-names = "apb", "hosc", "losc"; 371 gpio-controller; 372 #gpio-cells = <3>; 373 interrupt-controller; 374 #interrupt-cells = <3>; 375 376 i2c0_pins: i2c0_pins { 377 pins = "PH0", "PH1"; 378 function = "i2c0"; 379 }; 380 381 i2c1_pins: i2c1_pins { 382 pins = "PH2", "PH3"; 383 function = "i2c1"; 384 }; 385 386 mmc0_pins: mmc0-pins { 387 pins = "PF0", "PF1", "PF2", "PF3", 388 "PF4", "PF5"; 389 function = "mmc0"; 390 drive-strength = <30>; 391 bias-pull-up; 392 }; 393 394 mmc1_pins: mmc1-pins { 395 pins = "PG0", "PG1", "PG2", "PG3", 396 "PG4", "PG5"; 397 function = "mmc1"; 398 drive-strength = <30>; 399 bias-pull-up; 400 }; 401 402 mmc2_pins: mmc2-pins { 403 pins = "PC1", "PC5", "PC6", "PC8", "PC9", 404 "PC10","PC11", "PC12", "PC13", 405 "PC14", "PC15", "PC16"; 406 function = "mmc2"; 407 drive-strength = <30>; 408 bias-pull-up; 409 }; 410 411 pwm_pin: pwm_pin { 412 pins = "PD22"; 413 function = "pwm"; 414 }; 415 416 rmii_pins: rmii_pins { 417 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 418 "PD18", "PD19", "PD20", "PD22", "PD23"; 419 function = "emac"; 420 drive-strength = <40>; 421 }; 422 423 rgmii_pins: rgmii_pins { 424 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 425 "PD13", "PD15", "PD16", "PD17", "PD18", 426 "PD19", "PD20", "PD21", "PD22", "PD23"; 427 function = "emac"; 428 drive-strength = <40>; 429 }; 430 431 spdif_tx_pin: spdif { 432 pins = "PH8"; 433 function = "spdif"; 434 }; 435 436 spi0_pins: spi0 { 437 pins = "PC0", "PC1", "PC2", "PC3"; 438 function = "spi0"; 439 }; 440 441 spi1_pins: spi1 { 442 pins = "PD0", "PD1", "PD2", "PD3"; 443 function = "spi1"; 444 }; 445 446 uart0_pins_a: uart0 { 447 pins = "PB8", "PB9"; 448 function = "uart0"; 449 }; 450 451 uart1_pins: uart1_pins { 452 pins = "PG6", "PG7"; 453 function = "uart1"; 454 }; 455 456 uart1_rts_cts_pins: uart1_rts_cts_pins { 457 pins = "PG8", "PG9"; 458 function = "uart1"; 459 }; 460 461 uart2_pins: uart2-pins { 462 pins = "PB0", "PB1"; 463 function = "uart2"; 464 }; 465 466 uart3_pins: uart3-pins { 467 pins = "PD0", "PD1"; 468 function = "uart3"; 469 }; 470 471 uart4_pins: uart4-pins { 472 pins = "PD2", "PD3"; 473 function = "uart4"; 474 }; 475 476 uart4_rts_cts_pins: uart4-rts-cts-pins { 477 pins = "PD4", "PD5"; 478 function = "uart4"; 479 }; 480 }; 481 482 spdif: spdif@1c21000 { 483 #sound-dai-cells = <0>; 484 compatible = "allwinner,sun50i-a64-spdif", 485 "allwinner,sun8i-h3-spdif"; 486 reg = <0x01c21000 0x400>; 487 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 489 resets = <&ccu RST_BUS_SPDIF>; 490 clock-names = "apb", "spdif"; 491 dmas = <&dma 2>; 492 dma-names = "tx"; 493 pinctrl-names = "default"; 494 pinctrl-0 = <&spdif_tx_pin>; 495 status = "disabled"; 496 }; 497 498 i2s0: i2s@1c22000 { 499 #sound-dai-cells = <0>; 500 compatible = "allwinner,sun50i-a64-i2s", 501 "allwinner,sun8i-h3-i2s"; 502 reg = <0x01c22000 0x400>; 503 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 505 clock-names = "apb", "mod"; 506 resets = <&ccu RST_BUS_I2S0>; 507 dma-names = "rx", "tx"; 508 dmas = <&dma 3>, <&dma 3>; 509 status = "disabled"; 510 }; 511 512 i2s1: i2s@1c22400 { 513 #sound-dai-cells = <0>; 514 compatible = "allwinner,sun50i-a64-i2s", 515 "allwinner,sun8i-h3-i2s"; 516 reg = <0x01c22400 0x400>; 517 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 519 clock-names = "apb", "mod"; 520 resets = <&ccu RST_BUS_I2S1>; 521 dma-names = "rx", "tx"; 522 dmas = <&dma 4>, <&dma 4>; 523 status = "disabled"; 524 }; 525 526 uart0: serial@1c28000 { 527 compatible = "snps,dw-apb-uart"; 528 reg = <0x01c28000 0x400>; 529 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 530 reg-shift = <2>; 531 reg-io-width = <4>; 532 clocks = <&ccu CLK_BUS_UART0>; 533 resets = <&ccu RST_BUS_UART0>; 534 status = "disabled"; 535 }; 536 537 uart1: serial@1c28400 { 538 compatible = "snps,dw-apb-uart"; 539 reg = <0x01c28400 0x400>; 540 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 541 reg-shift = <2>; 542 reg-io-width = <4>; 543 clocks = <&ccu CLK_BUS_UART1>; 544 resets = <&ccu RST_BUS_UART1>; 545 status = "disabled"; 546 }; 547 548 uart2: serial@1c28800 { 549 compatible = "snps,dw-apb-uart"; 550 reg = <0x01c28800 0x400>; 551 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 552 reg-shift = <2>; 553 reg-io-width = <4>; 554 clocks = <&ccu CLK_BUS_UART2>; 555 resets = <&ccu RST_BUS_UART2>; 556 status = "disabled"; 557 }; 558 559 uart3: serial@1c28c00 { 560 compatible = "snps,dw-apb-uart"; 561 reg = <0x01c28c00 0x400>; 562 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 563 reg-shift = <2>; 564 reg-io-width = <4>; 565 clocks = <&ccu CLK_BUS_UART3>; 566 resets = <&ccu RST_BUS_UART3>; 567 status = "disabled"; 568 }; 569 570 uart4: serial@1c29000 { 571 compatible = "snps,dw-apb-uart"; 572 reg = <0x01c29000 0x400>; 573 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 574 reg-shift = <2>; 575 reg-io-width = <4>; 576 clocks = <&ccu CLK_BUS_UART4>; 577 resets = <&ccu RST_BUS_UART4>; 578 status = "disabled"; 579 }; 580 581 i2c0: i2c@1c2ac00 { 582 compatible = "allwinner,sun6i-a31-i2c"; 583 reg = <0x01c2ac00 0x400>; 584 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&ccu CLK_BUS_I2C0>; 586 resets = <&ccu RST_BUS_I2C0>; 587 status = "disabled"; 588 #address-cells = <1>; 589 #size-cells = <0>; 590 }; 591 592 i2c1: i2c@1c2b000 { 593 compatible = "allwinner,sun6i-a31-i2c"; 594 reg = <0x01c2b000 0x400>; 595 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&ccu CLK_BUS_I2C1>; 597 resets = <&ccu RST_BUS_I2C1>; 598 status = "disabled"; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 }; 602 603 i2c2: i2c@1c2b400 { 604 compatible = "allwinner,sun6i-a31-i2c"; 605 reg = <0x01c2b400 0x400>; 606 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 607 clocks = <&ccu CLK_BUS_I2C2>; 608 resets = <&ccu RST_BUS_I2C2>; 609 status = "disabled"; 610 #address-cells = <1>; 611 #size-cells = <0>; 612 }; 613 614 615 spi0: spi@1c68000 { 616 compatible = "allwinner,sun8i-h3-spi"; 617 reg = <0x01c68000 0x1000>; 618 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 620 clock-names = "ahb", "mod"; 621 dmas = <&dma 23>, <&dma 23>; 622 dma-names = "rx", "tx"; 623 pinctrl-names = "default"; 624 pinctrl-0 = <&spi0_pins>; 625 resets = <&ccu RST_BUS_SPI0>; 626 status = "disabled"; 627 num-cs = <1>; 628 #address-cells = <1>; 629 #size-cells = <0>; 630 }; 631 632 spi1: spi@1c69000 { 633 compatible = "allwinner,sun8i-h3-spi"; 634 reg = <0x01c69000 0x1000>; 635 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 636 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 637 clock-names = "ahb", "mod"; 638 dmas = <&dma 24>, <&dma 24>; 639 dma-names = "rx", "tx"; 640 pinctrl-names = "default"; 641 pinctrl-0 = <&spi1_pins>; 642 resets = <&ccu RST_BUS_SPI1>; 643 status = "disabled"; 644 num-cs = <1>; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 }; 648 649 emac: ethernet@1c30000 { 650 compatible = "allwinner,sun50i-a64-emac"; 651 syscon = <&syscon>; 652 reg = <0x01c30000 0x10000>; 653 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 654 interrupt-names = "macirq"; 655 resets = <&ccu RST_BUS_EMAC>; 656 reset-names = "stmmaceth"; 657 clocks = <&ccu CLK_BUS_EMAC>; 658 clock-names = "stmmaceth"; 659 status = "disabled"; 660 661 mdio: mdio { 662 compatible = "snps,dwmac-mdio"; 663 #address-cells = <1>; 664 #size-cells = <0>; 665 }; 666 }; 667 668 gic: interrupt-controller@1c81000 { 669 compatible = "arm,gic-400"; 670 reg = <0x01c81000 0x1000>, 671 <0x01c82000 0x2000>, 672 <0x01c84000 0x2000>, 673 <0x01c86000 0x2000>; 674 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 675 interrupt-controller; 676 #interrupt-cells = <3>; 677 }; 678 679 pwm: pwm@1c21400 { 680 compatible = "allwinner,sun50i-a64-pwm", 681 "allwinner,sun5i-a13-pwm"; 682 reg = <0x01c21400 0x400>; 683 clocks = <&osc24M>; 684 pinctrl-names = "default"; 685 pinctrl-0 = <&pwm_pin>; 686 #pwm-cells = <3>; 687 status = "disabled"; 688 }; 689 690 rtc: rtc@1f00000 { 691 compatible = "allwinner,sun6i-a31-rtc"; 692 reg = <0x01f00000 0x54>; 693 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 695 clock-output-names = "rtc-osc32k", "rtc-osc32k-out"; 696 clocks = <&osc32k>; 697 #clock-cells = <1>; 698 }; 699 700 r_intc: interrupt-controller@1f00c00 { 701 compatible = "allwinner,sun50i-a64-r-intc", 702 "allwinner,sun6i-a31-r-intc"; 703 interrupt-controller; 704 #interrupt-cells = <2>; 705 reg = <0x01f00c00 0x400>; 706 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 707 }; 708 709 r_ccu: clock@1f01400 { 710 compatible = "allwinner,sun50i-a64-r-ccu"; 711 reg = <0x01f01400 0x100>; 712 clocks = <&osc24M>, <&osc32k>, <&iosc>, 713 <&ccu 11>; 714 clock-names = "hosc", "losc", "iosc", "pll-periph"; 715 #clock-cells = <1>; 716 #reset-cells = <1>; 717 }; 718 719 r_i2c: i2c@1f02400 { 720 compatible = "allwinner,sun50i-a64-i2c", 721 "allwinner,sun6i-a31-i2c"; 722 reg = <0x01f02400 0x400>; 723 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 724 clocks = <&r_ccu CLK_APB0_I2C>; 725 resets = <&r_ccu RST_APB0_I2C>; 726 status = "disabled"; 727 #address-cells = <1>; 728 #size-cells = <0>; 729 }; 730 731 r_pwm: pwm@1f03800 { 732 compatible = "allwinner,sun50i-a64-pwm", 733 "allwinner,sun5i-a13-pwm"; 734 reg = <0x01f03800 0x400>; 735 clocks = <&osc24M>; 736 pinctrl-names = "default"; 737 pinctrl-0 = <&r_pwm_pin>; 738 #pwm-cells = <3>; 739 status = "disabled"; 740 }; 741 742 r_pio: pinctrl@1f02c00 { 743 compatible = "allwinner,sun50i-a64-r-pinctrl"; 744 reg = <0x01f02c00 0x400>; 745 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 746 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 747 clock-names = "apb", "hosc", "losc"; 748 gpio-controller; 749 #gpio-cells = <3>; 750 interrupt-controller; 751 #interrupt-cells = <3>; 752 753 r_i2c_pins_a: i2c-a { 754 pins = "PL8", "PL9"; 755 function = "s_i2c"; 756 }; 757 758 r_pwm_pin: pwm { 759 pins = "PL10"; 760 function = "s_pwm"; 761 }; 762 763 r_rsb_pins: rsb { 764 pins = "PL0", "PL1"; 765 function = "s_rsb"; 766 }; 767 }; 768 769 r_rsb: rsb@1f03400 { 770 compatible = "allwinner,sun8i-a23-rsb"; 771 reg = <0x01f03400 0x400>; 772 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 773 clocks = <&r_ccu 6>; 774 clock-frequency = <3000000>; 775 resets = <&r_ccu 2>; 776 pinctrl-names = "default"; 777 pinctrl-0 = <&r_rsb_pins>; 778 status = "disabled"; 779 #address-cells = <1>; 780 #size-cells = <0>; 781 }; 782 783 wdt0: watchdog@1c20ca0 { 784 compatible = "allwinner,sun50i-a64-wdt", 785 "allwinner,sun6i-a31-wdt"; 786 reg = <0x01c20ca0 0x20>; 787 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 788 }; 789 }; 790}; 791