| /kernel/linux/linux-5.10/Documentation/core-api/ |
| D | packing.rst | 6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
15 definitions from the hardware documentation into bit field indices for the
18 (sometimes even 64 bit ones). This creates the inconvenience of having to
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/ufs/ |
| D | tc-dwc-g210-pltfrm.txt | 3 DWC_UFS nodes are defined to describe on-chip UFS host controllers and MPHY.
7 - compatible : compatible list must contain the PHY type & version:
8 "snps,g210-tc-6.00-20bit"
9 "snps,g210-tc-6.00-40bit"
11 "snps,dwc-ufshcd-1.40a"
13 "jedec,ufs-1.1"
14 "jedec,ufs-2.0"
16 - reg : <registers mapping>
17 - interrupts : <interrupt mapping for UFS host controller IRQ>
19 Example for a setup using a 1.40a DWC Controller with a 6.00 G210 40-bit TC:
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/ufs/ |
| D | tc-dwc-g210-pltfrm.txt | 3 DWC_UFS nodes are defined to describe on-chip UFS host controllers and MPHY.
7 - compatible : compatible list must contain the PHY type & version:
8 "snps,g210-tc-6.00-20bit"
9 "snps,g210-tc-6.00-40bit"
11 "snps,dwc-ufshcd-1.40a"
13 "jedec,ufs-1.1"
14 "jedec,ufs-2.0"
16 - reg : <registers mapping>
17 - interrupts : <interrupt mapping for UFS host controller IRQ>
19 Example for a setup using a 1.40a DWC Controller with a 6.00 G210 40-bit TC:
[all …]
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| /kernel/linux/linux-4.19/arch/ia64/include/asm/sn/ |
| D | tioca.h | 9 * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
62 u64 ca_gart_tlb_addr[8]; /* 0x2{08..40} */
73 * Fields consisting of a single bit have a single #define have a single
74 * macro declaration to mask the bit. Fields consisting of multiple bits
104 /* bit 41 unused */
128 #define CA_CRM_TNUMTO_PERIOD (0x1fffull << 40)
129 #define CA_CRM_TNUMTO_PERIOD_SHFT 40
136 /* bit 63 unused */
145 /* bit 7 unused */
148 /* bit 15 unused */
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| /kernel/linux/linux-4.19/arch/alpha/kernel/ |
| D | sys_sable.c | 1 // SPDX-License-Identifier: GPL-2.0
9 * Code supporting the Sable, Sable-Gamma, and Lynx systems.
40 /* Note mask bit is true for DISABLED irqs. */
43 void (*update_irq_hw)(unsigned long bit, unsigned long mask);
44 void (*ack_irq_hw)(unsigned long bit);
56 * For SABLE, which is really baroque, we manage 40 IRQ's, but the
59 * 0-7 (char at 536)
60 * 8-15 (char at 53a)
61 * 16-23 (char at 53c)
65 * Bit Meaning Kernel IRQ
[all …]
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| D | sys_wildfire.c | 1 // SPDX-License-Identifier: GPL-2.0
42 int qbbno = (irq >> 8) & (WILDFIRE_MAX_QBB - 1); in wildfire_update_irq_hw()
43 int pcano = (irq >> 6) & (WILDFIRE_PCA_PER_QBB - 1); in wildfire_update_irq_hw()
50 " got irq %d for non-existent PCA %d" in wildfire_update_irq_hw()
58 enable0 = (unsigned long *) &pca->pca_int[0].enable; /* ??? */ in wildfire_update_irq_hw()
73 enable0 = (unsigned long *) &pca->pca_int[0].enable; in wildfire_init_irq_hw()
74 enable1 = (unsigned long *) &pca->pca_int[1].enable; in wildfire_init_irq_hw()
75 enable2 = (unsigned long *) &pca->pca_int[2].enable; in wildfire_init_irq_hw()
76 enable3 = (unsigned long *) &pca->pca_int[3].enable; in wildfire_init_irq_hw()
78 target0 = (unsigned long *) &pca->pca_int[0].target; in wildfire_init_irq_hw()
[all …]
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| /kernel/linux/linux-5.10/arch/alpha/kernel/ |
| D | sys_sable.c | 1 // SPDX-License-Identifier: GPL-2.0
9 * Code supporting the Sable, Sable-Gamma, and Lynx systems.
39 /* Note mask bit is true for DISABLED irqs. */
42 void (*update_irq_hw)(unsigned long bit, unsigned long mask);
43 void (*ack_irq_hw)(unsigned long bit);
55 * For SABLE, which is really baroque, we manage 40 IRQ's, but the
58 * 0-7 (char at 536)
59 * 8-15 (char at 53a)
60 * 16-23 (char at 53c)
64 * Bit Meaning Kernel IRQ
[all …]
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| D | sys_wildfire.c | 1 // SPDX-License-Identifier: GPL-2.0
41 int qbbno = (irq >> 8) & (WILDFIRE_MAX_QBB - 1); in wildfire_update_irq_hw()
42 int pcano = (irq >> 6) & (WILDFIRE_PCA_PER_QBB - 1); in wildfire_update_irq_hw()
49 " got irq %d for non-existent PCA %d" in wildfire_update_irq_hw()
57 enable0 = (unsigned long *) &pca->pca_int[0].enable; /* ??? */ in wildfire_update_irq_hw()
72 enable0 = (unsigned long *) &pca->pca_int[0].enable; in wildfire_init_irq_hw()
73 enable1 = (unsigned long *) &pca->pca_int[1].enable; in wildfire_init_irq_hw()
74 enable2 = (unsigned long *) &pca->pca_int[2].enable; in wildfire_init_irq_hw()
75 enable3 = (unsigned long *) &pca->pca_int[3].enable; in wildfire_init_irq_hw()
77 target0 = (unsigned long *) &pca->pca_int[0].target; in wildfire_init_irq_hw()
[all …]
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| /kernel/linux/linux-4.19/arch/mips/loongson64/loongson-3/ |
| D | dma.c | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/dma-direct.h>
8 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from in __phys_to_dma()
9 * Loongson-3's 48bit address space and embed it into 40bit */ in __phys_to_dma()
16 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from in __dma_to_phys()
17 * Loongson-3's 48bit address space and embed it into 40bit */ in __dma_to_phys()
|
| /kernel/linux/linux-5.10/arch/mips/loongson64/ |
| D | dma.c | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/dma-direct.h>
9 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from in phys_to_dma()
10 * Loongson-3's 48bit address space and embed it into 40bit */ in phys_to_dma()
18 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from in dma_to_phys()
19 * Loongson-3's 48bit address space and embed it into 40bit */ in dma_to_phys()
|
| /kernel/linux/linux-4.19/arch/arm64/kvm/hyp/ |
| D | s2-setup.c | 2 * Copyright (C) 2016 - ARM Ltd
32 * PS is only 3. Fortunately, bit 19 is RES0 in VTCR_EL2... in __init_stage2_translation()
48 parange = 40; in __init_stage2_translation()
63 * ... and clamp it to 40 bits, unless we have some braindead in __init_stage2_translation()
68 val |= 64 - (parange > 40 ? 40 : parange); in __init_stage2_translation()
71 * Check the availability of Hardware Access Flag / Dirty Bit in __init_stage2_translation()
80 * bit in VTCR_EL2. in __init_stage2_translation()
|
| /kernel/linux/linux-5.10/arch/powerpc/include/asm/nohash/32/ |
| D | pte-40x.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 * At present, all PowerPC 400-class processors share a similar TLB
9 * 64-entry, fully-associative TLB which is maintained totally under
11 * hardware-managed, 4-entry, fully-associative TLB which serves as a
15 * There are several potential gotchas here. The 40x hardware TLBLO
23 * - bits 20 and 21 must be cleared, because we use 4k pages (40x can
26 * - We use only zones 0 (for kernel pages) and 1 (for user pages)
27 * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
28 * miss handler. Bit 27 is PAGE_USER, thus selecting the correct
30 * - PRESENT *must* be in the bottom two bits because swap cache
[all …]
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | pxa3xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
18 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
19 (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \
20 (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \
21 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
23 (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \
33 (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \
[all …]
|
| /kernel/linux/linux-4.19/arch/powerpc/include/asm/nohash/32/ |
| D | pte-40x.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 * At present, all PowerPC 400-class processors share a similar TLB
9 * 64-entry, fully-associative TLB which is maintained totally under
11 * hardware-managed, 4-entry, fully-associative TLB which serves as a
15 * There are several potential gotchas here. The 40x hardware TLBLO
23 * - bits 20 and 21 must be cleared, because we use 4k pages (40x can
26 * - We use only zones 0 (for kernel pages) and 1 (for user pages)
27 * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
28 * miss handler. Bit 27 is PAGE_USER, thus selecting the correct
30 * - PRESENT *must* be in the bottom two bits because swap cache
[all …]
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| /kernel/linux/linux-4.19/drivers/auxdisplay/ |
| D | panel.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2000-2008, Willy Tarreau <w@1wt.eu>
5 * Copyright (C) 2016-2017 Glider bvba
10 * The LCD module may either be an HD44780-like 8-bit parallel LCD, or a 1-bit
15 * data output pins or to the ground. The combinations have to be hard-coded
22 * - the initialization/deinitialization process is very dirty and should
26 * - document 24 keys keyboard (3 rows of 8 cols, 32 diodes + 2 inputs)
27 * - make the LCD a part of a virtual screen of Vx*Vy
28 * - make the inputs list smp-safe
29 * - change the keyboard to a double mapping : signals -> key_id -> values
[all …]
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| /kernel/linux/linux-5.10/drivers/auxdisplay/ |
| D | panel.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2000-2008, Willy Tarreau <w@1wt.eu>
5 * Copyright (C) 2016-2017 Glider bvba
10 * The LCD module may either be an HD44780-like 8-bit parallel LCD, or a 1-bit
15 * data output pins or to the ground. The combinations have to be hard-coded
22 * - the initialization/deinitialization process is very dirty and should
26 * - document 24 keys keyboard (3 rows of 8 cols, 32 diodes + 2 inputs)
27 * - make the LCD a part of a virtual screen of Vx*Vy
28 * - make the inputs list smp-safe
29 * - change the keyboard to a double mapping : signals -> key_id -> values
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | pxa3xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
18 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
19 (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \
20 (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \
21 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
23 (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \
33 (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \
[all …]
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| /kernel/linux/linux-4.19/arch/arm/mach-ep93xx/ |
| D | timer-ep93xx.c | 1 // SPDX-License-Identifier: GPL-2.0
16 * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
17 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
18 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
19 * is free-running, and can't generate interrupts.
22 * most common values of HZ divide 508 kHz nicely. We pick the 32 bit
28 * a stable 40 bit time base.
115 evt->event_handler(evt); in ep93xx_timer_interrupt()
133 EP93XX_TIMER4_RATE, 200, 40, in ep93xx_timer_init()
135 sched_clock_register(ep93xx_read_sched_clock, 40, in ep93xx_timer_init()
|
| /kernel/linux/linux-5.10/arch/arm/mach-ep93xx/ |
| D | timer-ep93xx.c | 1 // SPDX-License-Identifier: GPL-2.0
16 * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
17 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
18 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
19 * is free-running, and can't generate interrupts.
22 * most common values of HZ divide 508 kHz nicely. We pick the 32 bit
28 * a stable 40 bit time base.
115 evt->event_handler(evt); in ep93xx_timer_interrupt()
129 EP93XX_TIMER4_RATE, 200, 40, in ep93xx_timer_init()
131 sched_clock_register(ep93xx_read_sched_clock, 40, in ep93xx_timer_init()
|
| /kernel/linux/linux-5.10/drivers/mtd/nand/spi/ |
| D | micron.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2017 Micron Technology, Inc.
21 #define MICRON_CFG_CR BIT(0)
24 * As per datasheet, die selection is done by the 6th bit of Die
51 return -ERANGE; in micron_8_ooblayout_ecc()
53 region->offset = mtd->oobsize / 2; in micron_8_ooblayout_ecc()
54 region->length = mtd->oobsize / 2; in micron_8_ooblayout_ecc()
63 return -ERANGE; in micron_8_ooblayout_free()
66 region->offset = 2; in micron_8_ooblayout_free()
67 region->length = (mtd->oobsize / 2) - 2; in micron_8_ooblayout_free()
[all …]
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| /kernel/linux/linux-5.10/arch/mips/include/asm/octeon/ |
| D | cvmx.h | 7 * Copyright (c) 2003-2017 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
42 /* These macros for use when using 32 bit pointers. */
56 #include <asm/octeon/cvmx-asm.h>
57 #include <asm/octeon/cvmx-packet.h>
58 #include <asm/octeon/cvmx-sysinfo.h>
60 #include <asm/octeon/cvmx-ciu-defs.h>
61 #include <asm/octeon/cvmx-ciu3-defs.h>
62 #include <asm/octeon/cvmx-gpio-defs.h>
[all …]
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| /kernel/linux/linux-4.19/arch/mips/include/asm/octeon/ |
| D | cvmx.h | 7 * Copyright (c) 2003-2017 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
42 /* These macros for use when using 32 bit pointers. */
56 #include <asm/octeon/cvmx-asm.h>
57 #include <asm/octeon/cvmx-packet.h>
58 #include <asm/octeon/cvmx-sysinfo.h>
60 #include <asm/octeon/cvmx-ciu-defs.h>
61 #include <asm/octeon/cvmx-ciu3-defs.h>
62 #include <asm/octeon/cvmx-gpio-defs.h>
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/fbtft/ |
| D | fb_hx8353d.c | 1 // SPDX-License-Identifier: GPL-2.0+
18 #define DEFAULT_GAMMA "50 77 40 08 BF 00 03 0F 00 01 73 00 72 03 B0 0F 08 00 0F"
22 par->fbtftops.reset(par); in init_display()
43 /* SLPOUT - Sleep out & booster on */ in init_display()
47 /* DISPON - Display On */ in init_display()
53 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, in init_display()
56 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, in init_display()
59 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62); in init_display()
76 #define my BIT(7)
77 #define mx BIT(6)
[all …]
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| /kernel/linux/linux-4.19/drivers/staging/fbtft/ |
| D | fb_hx8353d.c | 1 // SPDX-License-Identifier: GPL-2.0+
18 #define DEFAULT_GAMMA "50 77 40 08 BF 00 03 0F 00 01 73 00 72 03 B0 0F 08 00 0F"
22 par->fbtftops.reset(par); in init_display()
43 /* SLPOUT - Sleep out & booster on */ in init_display()
47 /* DISPON - Display On */ in init_display()
53 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, in init_display()
56 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, in init_display()
59 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62); in init_display()
76 #define my BIT(7)
77 #define mx BIT(6)
[all …]
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| /kernel/linux/linux-5.10/drivers/net/wireless/marvell/mwifiex/ |
| D | cfp.c | 4 * Copyright 2011-2020 NXP
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
78 /* LGI 40M */
82 /* SGI 40M */
113 /* LG 40M */
117 /* SG 40M */
146 /* LG 40M */
150 /* SG 40M */
[all …]
|