1// SPDX-License-Identifier: GPL-2.0 2/* The pxa3xx skeleton simply augments the 2xx version */ 3#include "pxa2xx.dtsi" 4 5#define MFP_PIN_PXA300(gpio) \ 6 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \ 7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \ 8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \ 9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ 10 0) 11#define MFP_PIN_PXA300_2(gpio) \ 12 ((gpio <= 1) ? (0x674 + 4 * gpio) : \ 13 (gpio <= 6) ? (0x2dc + 4 * gpio) : \ 14 0) 15 16#define MFP_PIN_PXA310(gpio) \ 17 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \ 18 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \ 19 (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \ 20 (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \ 21 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ 22 (gpio <= 262) ? 0 : \ 23 (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \ 24 0) 25#define MFP_PIN_PXA310_2(gpio) \ 26 ((gpio <= 1) ? (0x674 + 4 * gpio) : \ 27 (gpio <= 6) ? (0x2dc + 4 * gpio) : \ 28 (gpio <= 10) ? (0x52c + 4 * gpio) : \ 29 0) 30 31#define MFP_PIN_PXA320(gpio) \ 32 ((gpio <= 4) ? (0x0124 + 4 * gpio) : \ 33 (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \ 34 (gpio <= 10) ? (0x0458 + 4 * (gpio - 10)) : \ 35 (gpio <= 26) ? (0x02a0 + 4 * (gpio - 11)) : \ 36 (gpio <= 48) ? (0x0400 + 4 * (gpio - 27)) : \ 37 (gpio <= 62) ? (0x045c + 4 * (gpio - 49)) : \ 38 (gpio <= 73) ? (0x04b4 + 4 * (gpio - 63)) : \ 39 (gpio <= 98) ? (0x04f0 + 4 * (gpio - 74)) : \ 40 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ 41 0) 42#define MFP_PIN_PXA320_2(gpio) \ 43 ((gpio <= 3) ? (0x674 + 4 * gpio) : \ 44 (gpio <= 5) ? (0x284 + 4 * gpio) : \ 45 0) 46 47/* 48 * MFP Alternate functions for pins having a gpio. 49 * Example of use: pinctrl-single,pins = < MFP_PIN_PXA310(21) MFP_AF1 > 50 */ 51#define MFP_AF0 (0 << 0) 52#define MFP_AF1 (1 << 0) 53#define MFP_AF2 (2 << 0) 54#define MFP_AF3 (3 << 0) 55#define MFP_AF4 (4 << 0) 56#define MFP_AF5 (5 << 0) 57#define MFP_AF6 (6 << 0) 58 59/* 60 * MFP drive strength functions for pins. 61 * Example of use: pinctrl-single,drive-strength = MFP_DS03X; 62 */ 63#define MFP_DSMSK (0x7 << 10) 64#define MFP_DS01X < (0x0 << 10) MFP_DSMSK > 65#define MFP_DS02X < (0x1 << 10) MFP_DSMSK > 66#define MFP_DS03X < (0x2 << 10) MFP_DSMSK > 67#define MFP_DS04X < (0x3 << 10) MFP_DSMSK > 68#define MFP_DS06X < (0x4 << 10) MFP_DSMSK > 69#define MFP_DS08X < (0x5 << 10) MFP_DSMSK > 70#define MFP_DS10X < (0x6 << 10) MFP_DSMSK > 71#define MFP_DS13X < (0x7 << 10) MFP_DSMSK > 72 73/* 74 * MFP low power mode for pins. 75 * Example of use: 76 * pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW|MFP_LPM_EDGE_FALL); 77 * 78 * Table that determines the low power modes outputs, with actual settings 79 * used in parentheses for don't-care values. Except for the float output, 80 * the configured driven and pulled levels match, so if there is a need for 81 * non-LPM pulled output, the same configuration could probably be used. 82 * 83 * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel 84 * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15) 85 * 86 * Input 0 X(0) X(0) X(0) 0 87 * Drive 0 0 0 0 X(1) 0 88 * Drive 1 0 1 X(1) 0 0 89 * Pull hi (1) 1 X(1) 1 0 0 90 * Pull lo (0) 1 X(0) 0 1 0 91 * Z (float) 1 X(0) 0 0 0 92 */ 93#define MFP_LPM(x) < (x) MFP_LPM_MSK > 94 95#define MFP_LPM_MSK 0xe1f0 96#define MFP_LPM_INPUT 0x0000 97#define MFP_LPM_DRIVE_LOW 0x2000 98#define MFP_LPM_DRIVE_HIGH 0x4100 99#define MFP_LPM_PULL_LOW 0x2080 100#define MFP_LPM_PULL_HIGH 0x4180 101#define MFP_LPM_FLOAT 0x0080 102 103#define MFP_LPM_EDGE_NONE 0x0000 104#define MFP_LPM_EDGE_RISE 0x0010 105#define MFP_LPM_EDGE_FALL 0x0020 106#define MFP_LPM_EDGE_BOTH 0x0030 107 108/ { 109 model = "Marvell PXA3xx familiy SoC"; 110 compatible = "marvell,pxa3xx"; 111 112 pxabus { 113 pdma: dma-controller@40000000 { 114 compatible = "marvell,pdma-1.0"; 115 reg = <0x40000000 0x10000>; 116 interrupts = <25>; 117 #dma-channels = <32>; 118 #dma-cells = <2>; 119 #dma-requests = <100>; 120 status = "okay"; 121 }; 122 123 pwri2c: i2c@40f500c0 { 124 compatible = "mrvl,pwri2c"; 125 reg = <0x40f500c0 0x30>; 126 interrupts = <6>; 127 clocks = <&clks CLK_PWRI2C>; 128 #address-cells = <0x1>; 129 #size-cells = <0>; 130 status = "disabled"; 131 }; 132 133 nand_controller: nand-controller@43100000 { 134 compatible = "marvell,pxa3xx-nand-controller"; 135 reg = <0x43100000 90>; 136 interrupts = <45>; 137 clocks = <&clks CLK_NAND>; 138 clock-names = "core"; 139 dmas = <&pdma 97 3>; 140 dma-names = "data"; 141 #address-cells = <1>; 142 #size-cells = <0>; 143 status = "disabled"; 144 }; 145 146 pxairq: interrupt-controller@40d00000 { 147 marvell,intc-priority; 148 marvell,intc-nr-irqs = <56>; 149 }; 150 151 pinctrl: pinctrl@40e10000 { 152 compatible = "pinconf-single"; 153 reg = <0x40e10000 0xffff>; 154 #address-cells = <1>; 155 #size-cells = <0>; 156 #pinctrl-cells = <1>; 157 pinctrl-single,register-width = <32>; 158 pinctrl-single,function-mask = <0x7>; 159 }; 160 161 gpio: gpio@40e00000 { 162 compatible = "intel,pxa3xx-gpio"; 163 reg = <0x40e00000 0x10000>; 164 clocks = <&clks CLK_GPIO>; 165 gpio-ranges = <&pinctrl 0 0 128>; 166 interrupt-names = "gpio0", "gpio1", "gpio_mux"; 167 interrupts = <8 9 10>; 168 gpio-controller; 169 #gpio-cells = <0x2>; 170 interrupt-controller; 171 #interrupt-cells = <0x2>; 172 }; 173 174 mmc0: mmc@41100000 { 175 compatible = "marvell,pxa-mmc"; 176 reg = <0x41100000 0x1000>; 177 interrupts = <23>; 178 clocks = <&clks CLK_MMC1>; 179 dmas = <&pdma 21 3 180 &pdma 22 3>; 181 dma-names = "rx", "tx"; 182 status = "disabled"; 183 }; 184 185 mmc1: mmc@42000000 { 186 compatible = "marvell,pxa-mmc"; 187 reg = <0x42000000 0x1000>; 188 interrupts = <41>; 189 clocks = <&clks CLK_MMC2>; 190 dmas = <&pdma 93 3 191 &pdma 94 3>; 192 dma-names = "rx", "tx"; 193 status = "disabled"; 194 }; 195 196 mmc2: mmc@42500000 { 197 compatible = "marvell,pxa-mmc"; 198 reg = <0x42500000 0x1000>; 199 interrupts = <55>; 200 clocks = <&clks CLK_MMC3>; 201 dmas = <&pdma 46 3 202 &pdma 47 3>; 203 dma-names = "rx", "tx"; 204 status = "disabled"; 205 }; 206 207 usb0: usb@4c000000 { 208 compatible = "marvell,pxa-ohci"; 209 reg = <0x4c000000 0x10000>; 210 interrupts = <3>; 211 clocks = <&clks CLK_USBH>; 212 status = "disabled"; 213 }; 214 215 pwm0: pwm@40b00000 { 216 compatible = "marvell,pxa270-pwm"; 217 reg = <0x40b00000 0x10>; 218 #pwm-cells = <1>; 219 clocks = <&clks CLK_PWM0>; 220 status = "disabled"; 221 }; 222 223 pwm1: pwm@40b00010 { 224 compatible = "marvell,pxa270-pwm"; 225 reg = <0x40b00010 0x10>; 226 #pwm-cells = <1>; 227 clocks = <&clks CLK_PWM1>; 228 status = "disabled"; 229 }; 230 231 pwm2: pwm@40c00000 { 232 compatible = "marvell,pxa270-pwm"; 233 reg = <0x40c00000 0x10>; 234 #pwm-cells = <1>; 235 clocks = <&clks CLK_PWM0>; 236 status = "disabled"; 237 }; 238 239 pwm3: pwm@40c00010 { 240 compatible = "marvell,pxa270-pwm"; 241 reg = <0x40c00010 0x10>; 242 #pwm-cells = <1>; 243 clocks = <&clks CLK_PWM1>; 244 status = "disabled"; 245 }; 246 247 ssp1: ssp@41000000 { 248 compatible = "mrvl,pxa3xx-ssp"; 249 reg = <0x41000000 0x40>; 250 interrupts = <24>; 251 clocks = <&clks CLK_SSP1>; 252 status = "disabled"; 253 }; 254 255 ssp2: ssp@41700000 { 256 compatible = "mrvl,pxa3xx-ssp"; 257 reg = <0x41700000 0x40>; 258 interrupts = <16>; 259 clocks = <&clks CLK_SSP2>; 260 status = "disabled"; 261 }; 262 263 ssp3: ssp@41900000 { 264 compatible = "mrvl,pxa3xx-ssp"; 265 reg = <0x41900000 0x40>; 266 interrupts = <0>; 267 clocks = <&clks CLK_SSP3>; 268 status = "disabled"; 269 }; 270 271 ssp4: ssp@41a00000 { 272 compatible = "mrvl,pxa3xx-ssp"; 273 reg = <0x41a00000 0x40>; 274 interrupts = <13>; 275 clocks = <&clks CLK_SSP4>; 276 status = "disabled"; 277 }; 278 }; 279 280 clocks { 281 /* 282 * The muxing of external clocks/internal dividers for osc* clock 283 * sources has been hidden under the carpet by now. 284 */ 285 #address-cells = <1>; 286 #size-cells = <1>; 287 ranges; 288 289 clks: pxa3xx_clks@41300004 { 290 compatible = "marvell,pxa300-clocks"; 291 #clock-cells = <1>; 292 status = "okay"; 293 }; 294 }; 295 296 timer@40a00000 { 297 compatible = "marvell,pxa-timer"; 298 reg = <0x40a00000 0x20>; 299 interrupts = <26>; 300 clocks = <&clks CLK_OSTIMER>; 301 status = "okay"; 302 }; 303}; 304