| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | renesas,cmt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
26 - items:
27 - enum:
28 - renesas,r8a7740-cmt0 # 32-bit CMT0 on R-Mobile A1
29 - renesas,r8a7740-cmt1 # 48-bit CMT1 on R-Mobile A1
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/timer/ |
| D | renesas,cmt.txt | 1 * Renesas R-Car Compare Match Timer (CMT)
3 The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
14 - compatible: must contain one or more of the following:
15 - "renesas,cmt-48-sh73a0" for the sh73A0 48-bit CMT
17 - "renesas,cmt-48-r8a7740" for the r8a7740 48-bit CMT
19 - "renesas,cmt-48" for all non-second generation 48-bit CMT
21 This is a fallback for the above renesas,cmt-48-* entries.
23 - "renesas,r8a73a4-cmt0" for the 32-bit CMT0 device included in r8a73a4.
24 - "renesas,r8a73a4-cmt1" for the 48-bit CMT1 device included in r8a73a4.
25 - "renesas,r8a7743-cmt0" for the 32-bit CMT0 device included in r8a7743.
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| /kernel/linux/linux-5.10/drivers/gpio/ |
| D | gpio-104-idi-48.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the ACCES 104-IDI-48 family
6 * This driver supports the following ACCES devices: 104-IDI-48A,
7 * 104-IDI-48AC, 104-IDI-48B, and 104-IDI-48BC.
30 MODULE_PARM_DESC(base, "ACCES 104-IDI-48 base addresses");
34 MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line numbers");
37 * struct idi_48_gpio - GPIO device private data structure
43 * @cos_enb: Change-Of-State IRQ enable boundaries mask
72 for (i = 0; i < 48; i += 8) in idi_48_gpio_get()
75 mask = BIT(offset - i); in idi_48_gpio_get()
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| D | gpio-104-dio-48e.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the ACCES 104-DIO-48E series
6 * This driver supports the following ACCES devices: 104-DIO-48E and
7 * 104-DIO-24E.
30 MODULE_PARM_DESC(base, "ACCES 104-DIO-48E base addresses");
34 MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers");
37 * struct dio48e_gpio - GPIO device private data structure
39 * @io_state: bit I/O state (whether bit is set to input or output)
60 const unsigned mask = BIT(offset % 8); in dio48e_gpio_get_direction()
62 if (dio48egpio->io_state[port] & mask) in dio48e_gpio_get_direction()
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| /kernel/linux/linux-4.19/drivers/gpio/ |
| D | gpio-104-idi-48.c | 2 * GPIO driver for the ACCES 104-IDI-48 family
14 * This driver supports the following ACCES devices: 104-IDI-48A,
15 * 104-IDI-48AC, 104-IDI-48B, and 104-IDI-48BC.
38 MODULE_PARM_DESC(base, "ACCES 104-IDI-48 base addresses");
42 MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line numbers");
45 * struct idi_48_gpio - GPIO device private data structure
51 * @cos_enb: Change-Of-State IRQ enable boundaries mask
80 for (i = 0; i < 48; i += 8) in idi_48_gpio_get()
83 mask = BIT(offset - i); in idi_48_gpio_get()
85 return !!(inb(idi48gpio->base + base_offset) & mask); in idi_48_gpio_get()
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| /kernel/linux/linux-5.10/Documentation/arm64/ |
| D | memory.rst | 12 with the 4KB page configuration, allowing 39-bit (512GB) or 48-bit
14 64KB pages, only 2 levels of translation tables, allowing 42-bit (4TB)
21 User addresses have bits 63:48 set to 0 while the kernel addresses have
22 the same bits set to 1. TTBRx selection is given by bit 63 of the
24 mappings while the user pgd contains only user (non-global) mappings.
29 AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit)::
32 -----------------------------------------------------------------------
48 AArch64 Linux memory layout with 64KB pages + 3 levels (52-bit with HW support)::
51 -----------------------------------------------------------------------
70 +--------+--------+--------+--------+--------+--------+--------+--------+
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| /kernel/linux/linux-4.19/include/uapi/linux/ |
| D | dccp.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
9 * struct dccp_hdr - generic part of DCCP packet header
11 * @dccph_sport - Relevant port on the endpoint that sent this packet
12 * @dccph_dport - Relevant port on the other endpoint
13 * @dccph_doff - Data Offset from the start of the DCCP header, in 32-bit words
14 * @dccph_ccval - Used by the HC-Sender CCID
15 * @dccph_cscov - Parts of the packet that are covered by the Checksum field
16 * @dccph_checksum - Internet checksum, depends on dccph_cscov
17 * @dccph_x - 0 = 24 bit sequence number, 1 = 48
18 * @dccph_type - packet type, see DCCP_PKT_ prefixed macros
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| D | hdreg.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
17 #define IDE_DRIVE_TASK_INVALID -1
137 * 0x01->0x02 Reserved
141 * 0x04->0x07 Reserved
146 * 0x09->0x0F Reserved
151 * 0x10->0x1F Reserved
153 #define WIN_READ 0x20 /* 28-Bit */
154 #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
155 #define WIN_READ_LONG 0x22 /* 28-Bit */
156 #define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */
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| /kernel/linux/linux-5.10/include/uapi/linux/ |
| D | dccp.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
9 * struct dccp_hdr - generic part of DCCP packet header
11 * @dccph_sport - Relevant port on the endpoint that sent this packet
12 * @dccph_dport - Relevant port on the other endpoint
13 * @dccph_doff - Data Offset from the start of the DCCP header, in 32-bit words
14 * @dccph_ccval - Used by the HC-Sender CCID
15 * @dccph_cscov - Parts of the packet that are covered by the Checksum field
16 * @dccph_checksum - Internet checksum, depends on dccph_cscov
17 * @dccph_x - 0 = 24 bit sequence number, 1 = 48
18 * @dccph_type - packet type, see DCCP_PKT_ prefixed macros
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| D | hdreg.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
17 #define IDE_DRIVE_TASK_INVALID -1
137 * 0x01->0x02 Reserved
141 * 0x04->0x07 Reserved
146 * 0x09->0x0F Reserved
151 * 0x10->0x1F Reserved
153 #define WIN_READ 0x20 /* 28-Bit */
154 #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
155 #define WIN_READ_LONG 0x22 /* 28-Bit */
156 #define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */
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| /kernel/linux/linux-5.10/Documentation/core-api/ |
| D | packing.rst | 6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
15 definitions from the hardware documentation into bit field indices for the
18 (sometimes even 64 bit ones). This creates the inconvenience of having to
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
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| /kernel/linux/linux-5.10/arch/mips/include/asm/sgi/ |
| D | heart.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2004-2007 Stanislaw Skowronek <skylark@unaligned.org>
7 * 2007-2015 Joshua Kinard <kumba@gentoo.org>
27 * struct ip30_heart_regs - struct that maps IP30 HEART registers.
28 * @mode: HEART_MODE - Purpose Unknown, machine reset called from here.
29 * @sdram_mode: HEART_SDRAM_MODE - purpose unknown.
30 * @mem_refresh: HEART_MEM_REF - purpose unknown.
31 * @mem_req_arb: HEART_MEM_REQ_ARB - purpose unknown.
32 * @mem_cfg.q: union for 64bit access to HEART_MEMCFG - 4x 64bit registers.
33 * @mem_cfg.l: union for 32bit access to HEART_MEMCFG - 8x 32bit registers.
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| /kernel/linux/linux-5.10/Documentation/sound/cards/ |
| D | audiophile-usb.rst | 2 Guide to using M-Audio Audiophile USB with ALSA and Jack
9 This document is a guide to using the M-Audio Audiophile USB (tm) device with
15 * v1.4 - Thibault Le Meur (2007-07-11)
17 - Added Low Endianness nature of 16bits-modes
19 - Modifying document structure
21 * v1.5 - Thibault Le Meur (2007-07-12)
22 - Added AC3/DTS passthru info
35 - This port supports 2 pairs of line-level audio inputs (1/4" TS and RCA)
36 - When the 1/4" TS (jack) connectors are connected, the RCA connectors
52 Please exit any audio application running before switching between bit depths
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| /kernel/linux/linux-4.19/Documentation/sound/cards/ |
| D | audiophile-usb.rst | 2 Guide to using M-Audio Audiophile USB with ALSA and Jack
9 This document is a guide to using the M-Audio Audiophile USB (tm) device with
15 * v1.4 - Thibault Le Meur (2007-07-11)
17 - Added Low Endianness nature of 16bits-modes
19 - Modifying document structure
21 * v1.5 - Thibault Le Meur (2007-07-12)
22 - Added AC3/DTS passthru info
35 - This port supports 2 pairs of line-level audio inputs (1/4" TS and RCA)
36 - When the 1/4" TS (jack) connectors are connected, the RCA connectors
52 Please exit any audio application running before switching between bit depths
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| /kernel/linux/linux-5.10/arch/powerpc/kernel/vdso32/ |
| D | sigtramp.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
23 .Lsig_start = . - 4
43 .uleb128 9f - 1f; /* length */ \
56 .uleb128 9f - 1f; /* length */ \
65 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
72 .uleb128 9f - 1f; /* length */ \
97 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
102 .uleb128 9f - 1f; /* length */ \
105 .byte 0x2f; .short 2b - 9f; /* DW_OP_skip */ \
108 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
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| /kernel/linux/linux-4.19/arch/powerpc/kernel/vdso32/ |
| D | sigtramp.S | 27 .Lsig_start = . - 4
47 .uleb128 9f - 1f; /* length */ \
60 .uleb128 9f - 1f; /* length */ \
69 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
76 .uleb128 9f - 1f; /* length */ \
101 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
106 .uleb128 9f - 1f; /* length */ \
109 .byte 0x2f; .short 2b - 9f; /* DW_OP_skip */ \
112 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
117 .uleb128 9f - 1f; /* length */ \
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| /kernel/linux/linux-5.10/drivers/staging/media/hantro/ |
| D | imx8m_vpu_hw.c | 1 // SPDX-License-Identifier: GPL-2.0
16 #define RESET_G1 BIT(1)
17 #define RESET_G2 BIT(0)
20 #define CLOCK_G1 BIT(1)
21 #define CLOCK_G2 BIT(0)
32 val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
34 writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
39 val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
41 writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); in imx8m_soft_reset()
48 val = readl(vpu->ctrl_base + CTRL_CLOCK_ENABLE); in imx8m_clk_enable()
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| /kernel/linux/linux-5.10/arch/x86/crypto/ |
| D | crct10dif-pcl-asm_64.S | 2 # Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
50 # /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
107 # bit order match the polynomial coefficient order.
137 # While >= 128 data bytes remain (not counting xmm0-7), fold the 128
138 # bytes xmm0-7 into them, storing the result back into xmm0-7.
148 # Now fold the 112 bytes in xmm0-xmm6 into the 16 bytes in xmm7.
168 add $128-16, len
201 movdqu -16(buf, len), %xmm1
204 # xmm2 = high order part of second chunk: xmm7 left-shifted by 'len' bytes.
210 # xmm7 = first chunk: xmm7 right-shifted by '16-len' bytes.
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| /kernel/linux/linux-5.10/sound/pci/emu10k1/ |
| D | p16v.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
9 * Rates: 44.1, 48, 96, 192.
17 * Corrected speaker output, so Front -> Front etc.
36 * Merging with snd-emu10k1 driver.
38 * One stereo channel at 24bit now works.
45 * Some stability problems when unloading the snd-p16v kernel module.
46 * --
53 * --
56 * P16V Chip: CA0151-DBS
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| /kernel/linux/linux-4.19/sound/pci/emu10k1/ |
| D | p16v.h | 2 * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
8 * Rates: 44.1, 48, 96, 192.
16 * Corrected speaker output, so Front -> Front etc.
35 * Merging with snd-emu10k1 driver.
37 * One stereo channel at 24bit now works.
45 * Some stability problems when unloading the snd-p16v kernel module.
46 * --
53 * --
56 * P16V Chip: CA0151-DBS
57 * Audigy 2 Chip: CA0102-IAT
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| /kernel/linux/linux-5.10/arch/powerpc/kernel/vdso64/ |
| D | sigtramp.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
42 .quad 0,-21*8
48 .uleb128 9f - 1f; /* length */ \
61 .uleb128 9f - 1f; /* length */ \
70 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
77 .uleb128 9f - 1f; /* length */ \
103 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
108 .uleb128 9f - 1f; /* length */ \
111 .byte 0x2f; .short 2b - 9f; /* DW_OP_skip */ \
114 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
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| /kernel/linux/linux-4.19/arch/powerpc/kernel/vdso64/ |
| D | sigtramp.S | 29 .Lsigrt_start = . - 4
40 .quad 0,-21*8
46 .uleb128 9f - 1f; /* length */ \
59 .uleb128 9f - 1f; /* length */ \
68 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
75 .uleb128 9f - 1f; /* length */ \
101 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
106 .uleb128 9f - 1f; /* length */ \
109 .byte 0x2f; .short 2b - 9f; /* DW_OP_skip */ \
112 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
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| /kernel/linux/linux-5.10/include/sound/ |
| D | emu10k1.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 #include <sound/pcm-indirect.h>
25 /* ------------------- DEFINES -------------------- */
29 #define MAXPAGES0 4096 /* 32 bit mode */
30 #define MAXPAGES1 8192 /* 31 bit mode */
37 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
38 #define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */
39 #define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit mode */
55 #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
57 /* accessed. For non per-channel registers the */
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| /kernel/linux/linux-4.19/include/sound/ |
| D | emu10k1.h | 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 #include <sound/pcm-indirect.h>
40 /* ------------------- DEFINES -------------------- */
44 #define MAXPAGES0 4096 /* 32 bit mode */
45 #define MAXPAGES1 8192 /* 31 bit mode */
52 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
53 #define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */
54 #define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit mode */
70 #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
72 /* accessed. For non per-channel registers the */
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| /kernel/linux/linux-5.10/arch/arm/crypto/ |
| D | crct10dif-ce-core.S | 2 // Accelerated CRC-T10DIF using ARM NEON and Crypto Extensions instructions
14 // Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
62 // /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
75 .arch armv8-a
76 .fpu crypto-neon-fp-armv8
118 vld1.64 {q11-q12}, [buf]!
166 // the bit order match the polynomial coefficient order.
167 vld1.64 {q0-q1}, [buf]!
168 vld1.64 {q2-q3}, [buf]!
169 vld1.64 {q4-q5}, [buf]!
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