Searched +full:armv8 +full:- +full:based (Results 1 – 25 of 79) sorted by relevance
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| /kernel/linux/linux-5.10/arch/arm64/ |
| D | Kconfig.platforms | 1 # SPDX-License-Identifier: GPL-2.0-only
17 bool "Allwinner sunxi 64-bit SoC Family"
23 This enables support for Allwinner sunxi based SoCs like the A64.
52 This enables support for Broadcom iProc based SoCs
69 bool "Broadcom Set-Top-Box SoCs"
76 This enables support for Broadcom's ARMv8 Set Top Box SoCs
79 bool "ARMv8 based Samsung Exynos SoC family"
90 This enables support for ARMv8 based Samsung Exynos SoC family.
93 bool "ARMv8 based Microchip Sparx5 SoC family"
97 This enables support for the Microchip Sparx5 ARMv8-based
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
161 if $(cc-option,-fpatchable-function-entry=2)
206 ARM 64-bit (AArch64) Linux support.
238 # VA_BITS - PAGE_SHIFT - 3
331 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
358 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
363 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
366 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
372 data cache clean-and-invalidate.
380 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/ |
| D | fsl.txt | 2 -----------------------------------------------
6 - compatible = "fsl,imx23-evk", "fsl,imx23";
10 - compatible = "fsl,imx25-pdk", "fsl,imx25";
14 - compatible = "fsl,imx27-pdk", "fsl,imx27";
18 - compatible = "fsl,imx28-evk", "fsl,imx28";
22 - compatible = "fsl,imx51-babbage", "fsl,imx51";
26 - compatible = "fsl,imx53-ard", "fsl,imx53";
30 - compatible = "fsl,imx53-evk", "fsl,imx53";
34 - compatible = "fsl,imx53-qsb", "fsl,imx53";
38 - compatible = "fsl,imx53-smd", "fsl,imx53";
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| D | coresight-cpu-debug.txt | 3 CoreSight CPU debug component are compliant with the ARMv8 architecture
5 external debug module is mainly used for two modes: self-hosted debug and
8 debug module provides sample-based profiling extension, which can be used
14 - compatible : should be "arm,coresight-cpu-debug"; supplemented with
18 - reg : physical base address and length of the register set.
20 - clocks : the clock associated to this component.
22 - clock-names : the name of the clock referenced by the code. Since we are
29 - cpu : the CPU phandle the debug module is affined to. When omitted
34 - power-domains: a phandle to the debug power domain. We use "power-domains"
44 compatible = "arm,coresight-cpu-debug","arm,primecell";
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| /kernel/linux/linux-4.19/arch/arm64/ |
| D | Kconfig.platforms | 10 bool "Allwinner sunxi 64-bit SoC Family"
16 This enables support for Allwinner sunxi based SoCs like the A64.
44 This enables support for Broadcom iProc based SoCs
56 bool "Broadcom Set-Top-Box SoCs"
60 This enables support for Broadcom's ARMv8 Set Top Box SoCs
63 bool "ARMv8 based Samsung Exynos SoC family"
73 This enables support for ARMv8 based Samsung Exynos SoC family.
83 bool "ARMv8 based Freescale Layerscape SoC family"
99 This enables support for Hisilicon ARMv8 SoC family
108 & MT81xx ARMv8 SoCs
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| D | Kconfig | 171 ARM 64-bit (AArch64) Linux support.
197 # VA_BITS - PAGE_SHIFT - 3
314 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
318 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
321 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
327 data cache clean-and-invalidate.
335 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
339 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
348 data cache clean-and-invalidate.
356 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
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| /kernel/linux/linux-4.19/arch/arm/crypto/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
13 tristate "SHA1 digest algorithm (ARM-asm)"
17 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented
27 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented
37 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented
38 using special ARMv8 Crypto Extensions.
41 tristate "SHA-224/256 digest algorithm (ARM v8 Crypto Extensions)"
46 SHA-256 secure hash standard (DFIPS 180-2) implemented
47 using special ARMv8 Crypto Extensions.
50 tristate "SHA-224/256 digest algorithm (ARM-asm and NEON)"
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| /kernel/linux/linux-5.10/arch/arm/crypto/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
13 tristate "SHA1 digest algorithm (ARM-asm)"
17 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented
27 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented
37 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented
38 using special ARMv8 Crypto Extensions.
41 tristate "SHA-224/256 digest algorithm (ARM v8 Crypto Extensions)"
46 SHA-256 secure hash standard (DFIPS 180-2) implemented
47 using special ARMv8 Crypto Extensions.
50 tristate "SHA-224/256 digest algorithm (ARM-asm and NEON)"
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| /kernel/linux/linux-5.10/Documentation/trace/coresight/ |
| D | coresight-cpu-debug.rst | 9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
32 registers to decide if sample-based profiling is implemented or not. On some
36 - At the time this documentation was written, the debug driver mainly relies on
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| /kernel/linux/linux-4.19/Documentation/trace/ |
| D | coresight-cpu-debug.txt | 8 ------------
10 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
12 debug module and it is mainly used for two modes: self-hosted debug and
15 explore debugging method which rely on self-hosted debug mode, this document
18 The debug module provides sample-based profiling extension, which can be used
20 every CPU has one dedicated debug module to be connected. Based on self-hosted
28 --------------
30 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
31 registers to decide if sample-based profiling is implemented or not. On some
35 - At the time this documentation was written, the debug driver mainly relies on
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| /kernel/linux/linux-5.10/drivers/perf/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
45 tristate "Arm CMN-600 PMU support"
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
56 Say y if you want to use CPU performance monitors on ARM-based
70 based on the Stream ID of the corresponding master.
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| /kernel/linux/linux-4.19/drivers/perf/ |
| D | Kconfig | 16 If compiled as a module, it will be called arm-cci.
19 bool "support CCI-400"
24 CCI-400 provides 4 independent event counters counting events related
28 bool "support CCI-500/CCI-550"
32 CCI-500/CCI-550 both provide 8 independent event counters, which can
48 Say y if you want to use CPU performance monitors on ARM-based
72 bool "Qualcomm Technologies L2-cache PMU"
81 bool "Qualcomm Technologies L3-cache PMU"
92 bool "APM X-Gene SoC PMU"
95 Say y if you want to use APM X-Gene SoC performance monitors.
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| /kernel/linux/linux-5.10/drivers/soc/samsung/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
15 # There is no need to enable these drivers for ARMv8
17 bool "Exynos ASV ARMv7-specific driver extensions" if COMPILE_TEST
31 # There is no need to enable these drivers for ARMv8
33 bool "Exynos PMU ARMv7-specific driver extensions" if COMPILE_TEST
48 Resume code. See <file:Documentation/arm/samsung-s3c24xx/suspend.rst>
58 Note, this currently only works for S3C64XX based SMDK boards.
73 See <file:Documentation/arm/samsung-s3c24xx/suspend.rst>
85 See <file:Documentation/arm/samsung-s3c24xx/suspend.rst>
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| /kernel/linux/linux-5.10/drivers/clk/samsung/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
10 bool "Samsung Exynos ARMv8-family clock controller support" if COMPILE_TEST
27 Build the s3c2410 clock driver based on the common clock framework.
34 Temporary symbol to build the dclk driver based on the common clock
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| /kernel/linux/linux-4.19/drivers/clk/samsung/ |
| D | Kconfig | 9 bool "Samsung Exynos ARMv8-family clock controller support" if COMPILE_TEST
26 Build the s3c2410 clock driver based on the common clock framework.
33 Temporary symbol to build the dclk driver based on the common clock
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | microchip,sparx5.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
14 gigabit TSN-capable gigabit switches.
16 The SparX-5 Ethernet switch family provides a rich set of switching
17 features such as advanced TCAM-based VLAN and QoS processing
19 TCAM-based frame processing using versatile content aware processor
27 - description: The Sparx5 pcb125 board is a modular board,
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| D | coresight-cpu-debug.txt | 3 CoreSight CPU debug component are compliant with the ARMv8 architecture
5 external debug module is mainly used for two modes: self-hosted debug and
8 debug module provides sample-based profiling extension, which can be used
14 - compatible : should be "arm,coresight-cpu-debug"; supplemented with
18 - reg : physical base address and length of the register set.
20 - clocks : the clock associated to this component.
22 - clock-names : the name of the clock referenced by the code. Since we are
29 - cpu : the CPU phandle the debug module is affined to. Do not assume it
34 - power-domains: a phandle to the debug power domain. We use "power-domains"
44 compatible = "arm,coresight-cpu-debug","arm,primecell";
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| /kernel/linux/linux-4.19/drivers/soc/tegra/ |
| D | Kconfig | 3 # 32-bit ARM SoCs
19 Support for NVIDIA Tegra AP20 and T20 processors, based on the
32 Support for NVIDIA Tegra T30 processor family, based on the
44 Support for NVIDIA Tegra T114 processor family, based on the
55 Support for NVIDIA Tegra T124 processor family, based on the
60 # 64-bit ARM SoCs
69 Enable support for NVIDIA Tegra132 SoC, based on the Denver
70 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
72 Tegra124's "4+1" Cortex-A15 CPU complex.
81 the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
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| /kernel/linux/linux-5.10/drivers/soc/tegra/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
4 # 32-bit ARM SoCs
21 Support for NVIDIA Tegra AP20 and T20 processors, based on the
35 Support for NVIDIA Tegra T30 processor family, based on the
47 Support for NVIDIA Tegra T114 processor family, based on the
58 Support for NVIDIA Tegra T124 processor family, based on the
63 # 64-bit ARM SoCs
72 Enable support for NVIDIA Tegra132 SoC, based on the Denver
73 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
75 Tegra124's "4+1" Cortex-A15 CPU complex.
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| /kernel/linux/linux-4.19/arch/arm64/boot/dts/hisilicon/ |
| D | hip07.dtsi | 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 compatible = "hisilicon,hip07-d05";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
26 #address-cells = <1>;
27 #size-cells = <0>;
29 cpu-map {
273 compatible = "arm,cortex-a72", "arm,armv8";
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| D | hip06.dtsi | 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 compatible = "hisilicon,hip06-d03";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
26 #address-cells = <1>;
27 #size-cells = <0>;
29 cpu-map {
90 compatible = "arm,cortex-a57", "arm,armv8";
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| /kernel/linux/linux-5.10/Documentation/arm64/ |
| D | pointer-authentication.rst | 7 Date: 2017-07-19
14 ---------------------
16 The ARMv8.3 Pointer Authentication extension adds primitives that can be
27 of high-order bits of the pointer, which varies dependent on the
36 The extension provides five separate keys to generate PACs - two for
42 -------------
56 Recent versions of GCC can compile code with APIAKey-based return
57 address protection when passed the -msign-return-address option. This
58 uses instructions in the HINT space (unless -march=armv8.3-a or higher
70 ---------
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| D | arm-acpi.rst | 2 ACPI on ARMv8 Servers
5 ACPI can be used for ARMv8 general purpose servers designed to follow
11 The ARMv8 kernel implements the reduced hardware model of ACPI version
17 If an ARMv8 system does not meet the requirements of the SBSA and SBBR,
22 industry-standard ARMv8 servers, they also apply to more than one operating
24 ACPI and Linux only, on an ARMv8 system -- that is, what Linux expects of
29 ----------------
32 exist in Linux for describing non-enumerable hardware, after all. In this
34 reasoning behind ACPI on ARMv8 servers. Actually, we snitch a good portion
39 - ACPI’s byte code (AML) allows the platform to encode hardware behavior,
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| D | memory-tagging-extension.rst | 8 Date: 2020-02-25
16 ARMv8.5 based processors introduce the Memory Tagging Extension (MTE)
17 feature. MTE is built on top of the ARMv8.0 virtual address tagging TBI
18 (Top Byte Ignore) feature and allows software to access a 4-bit
19 allocation tag for each 16-byte granule in the physical address space.
20 Such memory range must be mapped with the Normal-Tagged memory
21 attribute. A logical tag is derived from bits 59-56 of the virtual
34 --------
40 ``PROT_MTE`` - Pages allow access to the MTE allocation tags.
43 user address space and preserved on copy-on-write. ``MAP_SHARED`` is
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| /kernel/linux/linux-4.19/Documentation/arm64/ |
| D | arm-acpi.txt | 1 ACPI on ARMv8 Servers
2 ---------------------
3 ACPI can be used for ARMv8 general purpose servers designed to follow
9 The ARMv8 kernel implements the reduced hardware model of ACPI version
15 If an ARMv8 system does not meet the requirements of the SBSA and SBBR,
20 industry-standard ARMv8 servers, they also apply to more than one operating
22 ACPI and Linux only, on an ARMv8 system -- that is, what Linux expects of
27 ----------------
30 exist in Linux for describing non-enumerable hardware, after all. In this
32 reasoning behind ACPI on ARMv8 servers. Actually, we snitch a good portion
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