| /kernel/linux/linux-4.19/drivers/isdn/hisax/ |
| D | icc.c | 26 #define ARCOFI_USE 0
32 ICCVersion(struct IsdnCardState *cs, char *s) in ICCVersion() argument
36 val = cs->readisac(cs, ICC_RBCH); in ICCVersion()
41 ph_command(struct IsdnCardState *cs, unsigned int command) in ph_command() argument
43 if (cs->debug & L1_DEB_ISAC) in ph_command()
44 debugl1(cs, "ph_command %x", command); in ph_command()
45 cs->writeisac(cs, ICC_CIX0, (command << 2) | 3); in ph_command()
50 icc_new_ph(struct IsdnCardState *cs) in icc_new_ph() argument
52 switch (cs->dc.icc.ph_state) { in icc_new_ph()
54 ph_command(cs, ICC_CMD_DI); in icc_new_ph()
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| D | isac.c | 31 void ISACVersion(struct IsdnCardState *cs, char *s) in ISACVersion() argument
35 val = cs->readisac(cs, ISAC_RBCH); in ISACVersion()
40 ph_command(struct IsdnCardState *cs, unsigned int command) in ph_command() argument
42 if (cs->debug & L1_DEB_ISAC) in ph_command()
43 debugl1(cs, "ph_command %x", command); in ph_command()
44 cs->writeisac(cs, ISAC_CIX0, (command << 2) | 3); in ph_command()
49 isac_new_ph(struct IsdnCardState *cs) in isac_new_ph() argument
51 switch (cs->dc.isac.ph_state) { in isac_new_ph()
54 ph_command(cs, ISAC_CMD_DUI); in isac_new_ph()
55 l1_msg(cs, HW_RESET | INDICATION, NULL); in isac_new_ph()
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| D | amd7930_fn.c | 6 * Author Christoph Ersfeld <info@formula-n.de>
7 * Formula-n Europe AG (www.formula-n.com)
19 * (compressed) debug-logs.
22 * Log D-channel-processing as follows:
24 * 1. Load hisax with card-specific parameters, this example ist for
25 * Formula-n enter:now ISDN PCI and compatible
33 * 2. set debug-level
35 * hisaxctrl gerdes 1 0x3ff
36 * hisaxctrl gerdes 11 0x4f
44 * Programming the driver for Formula-n enter:now ISDN PCI and
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| D | elsa.c | 36 {"None", "PC", "PCC-8", "PCC-16", "PCF", "PCF-Pro",
38 "PCMCIA-IPAC" };
41 {"?0?", "?1?", "?2?", "?3?", "?4?", "V2.2",
47 #define ELSA_ISAC 0
71 #define ELSA_PCI_IRQ_MASK 0x04
74 #define ITAC_SYS 0x34
75 #define ITAC_ISEN 0x48
76 #define ITAC_RFIE 0x4A
77 #define ITAC_XFIE 0x4C
78 #define ITAC_SCIE 0x4E
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| D | sedlbauer.c | 6 * support for the Sedlbauer ISDN-Controller PC/104 and
11 * Copyright by Marcus Niemann <niemann@www-bib.fh-bielefeld.de>
24 * ---------------------------------------------------------------------
25 * Speed Card ISAC_HSCX DIP-SWITCH
30 * ISDN PC/104 IPAC DIP-SWITCH
58 #define PCI_SUBVENDOR_SPEEDFAX_PYRAMID 0x51
59 #define PCI_SUBVENDOR_HST_SAPHIR3 0x52
60 #define PCI_SUBVENDOR_SEDLBAUER_PCI 0x53
61 #define PCI_SUBVENDOR_SPEEDFAX_PCI 0x54
62 #define PCI_SUB_ID_SEDLBAUER 0x01
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| D | w6692.c | 33 {0, 0, "U.S.Robotics", "ISDN PCI Card TA"}
36 #define W6692_SV_USR 0x16ec
37 #define W6692_SD_USR 0x3409
38 #define W6692_WINBOND 0
51 W6692Version(struct IsdnCardState *cs, char *s) in W6692Version() argument
55 val = cs->readW6692(cs, W_D_RBCH); in W6692Version()
60 ph_command(struct IsdnCardState *cs, unsigned int command) in ph_command() argument
62 if (cs->debug & L1_DEB_ISAC) in ph_command()
63 debugl1(cs, "ph_command %x", command); in ph_command()
64 cs->writeisac(cs, W_CIX, command); in ph_command()
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| D | diva.c | 33 #define DIVA_HSCX_DATA 0
38 #define DIVA_IPAC_ADR 0
42 #define DIVA_PCI_ISAC_ADR 0xc
43 #define DIVA_PCI_CTRL 0x10
53 #define DIVA_IRQ_STAT 0x01
54 #define DIVA_EEPROM_SDA 0x02
57 #define DIVA_IRQ_REQ 0x01
58 #define DIVA_RESET 0x08
59 #define DIVA_EEPROM_CLK 0x40
60 #define DIVA_PCI_LED_A 0x10
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| D | hfc_2bds0.c | 29 dummyf(struct IsdnCardState *cs, u_char *data, int size) in dummyf() argument
35 ReadReg(struct IsdnCardState *cs, int data, u_char reg) in ReadReg() argument
40 if (cs->hw.hfcD.cip != reg) { in ReadReg()
41 cs->hw.hfcD.cip = reg; in ReadReg()
42 byteout(cs->hw.hfcD.addr | 1, reg); in ReadReg()
44 ret = bytein(cs->hw.hfcD.addr); in ReadReg()
46 if (cs->debug & L1_DEB_HSCX_FIFO && (data != 2)) in ReadReg()
47 debugl1(cs, "t3c RD %02x %02x", reg, ret); in ReadReg()
50 ret = bytein(cs->hw.hfcD.addr | 1); in ReadReg()
55 WriteReg(struct IsdnCardState *cs, int data, u_char reg, u_char value) in WriteReg() argument
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| D | asuscom.c | 28 #define ASUS_ISAC 0
34 #define ASUS_IPAC_ALE 0
41 #define ASUS_RESET 0x80 /* Bit 7 Reset-Leitung */
78 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
80 return (readreg(cs->hw.asus.adr, cs->hw.asus.isac, offset)); in ReadISAC()
84 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
86 writereg(cs->hw.asus.adr, cs->hw.asus.isac, offset, value); in WriteISAC()
90 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
92 readfifo(cs->hw.asus.adr, cs->hw.asus.isac, 0, data, size); in ReadISACfifo()
96 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
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| D | gazel.c | 29 #define PLX_CNTRL 0x50 /* registre de controle PLX */
30 #define RESET_GAZEL 0x4
31 #define RESET_9050 0x40000000
32 #define PLX_INCSR 0x4C /* registre d'IT du 9050 */
33 #define INT_ISAC_EN 0x8 /* 1 = enable IT isac */
34 #define INT_ISAC 0x20 /* 1 = IT isac en cours */
35 #define INT_HSCX_EN 0x1 /* 1 = enable IT hscx */
36 #define INT_HSCX 0x4 /* 1 = IT hscx en cours */
37 #define INT_PCI_EN 0x40 /* 1 = enable IT PCI */
38 #define INT_IPAC_EN 0x3 /* enable IT ipac */
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| D | hscx.c | 26 HscxVersion(struct IsdnCardState *cs, char *s) in HscxVersion() argument
30 verA = cs->BC_Read_Reg(cs, 0, HSCX_VSTR) & 0xf; in HscxVersion()
31 verB = cs->BC_Read_Reg(cs, 1, HSCX_VSTR) & 0xf; in HscxVersion()
34 if ((verA == 0) | (verA == 0xf) | (verB == 0) | (verB == 0xf)) in HscxVersion()
37 return (0); in HscxVersion()
43 struct IsdnCardState *cs = bcs->cs; in modehscx() local
44 int hscx = bcs->hw.hscx.hscx; in modehscx()
46 if (cs->debug & L1_DEB_HSCX) in modehscx()
47 debugl1(cs, "hscx %c mode %d ichan %d", in modehscx()
49 bcs->mode = mode; in modehscx()
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| D | saphir.c | 26 #define ISAC_DATA 0
68 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
70 return (readreg(cs->hw.saphir.ale, cs->hw.saphir.isac, offset)); in ReadISAC()
74 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
76 writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, offset, value); in WriteISAC()
80 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
82 readfifo(cs->hw.saphir.ale, cs->hw.saphir.isac, 0, data, size); in ReadISACfifo()
86 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
88 writefifo(cs->hw.saphir.ale, cs->hw.saphir.isac, 0, data, size); in WriteISACfifo()
92 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
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| D | teles3.c | 56 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
58 return (readreg(cs->hw.teles3.isac, offset)); in ReadISAC()
62 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
64 writereg(cs->hw.teles3.isac, offset, value); in WriteISAC()
68 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
70 read_fifo(cs->hw.teles3.isacfifo, data, size); in ReadISACfifo()
74 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
76 write_fifo(cs->hw.teles3.isacfifo, data, size); in WriteISACfifo()
80 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
82 return (readreg(cs->hw.teles3.hscx[hscx], offset)); in ReadHSCX()
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| D | hfcscard.c | 24 struct IsdnCardState *cs = dev_id; in hfcs_interrupt() local
28 spin_lock_irqsave(&cs->lock, flags); in hfcs_interrupt()
30 (stat = cs->BC_Read_Reg(cs, HFCD_DATA, HFCD_STAT))) { in hfcs_interrupt()
31 val = cs->BC_Read_Reg(cs, HFCD_DATA, HFCD_INT_S1); in hfcs_interrupt()
32 if (cs->debug & L1_DEB_ISAC) in hfcs_interrupt()
33 debugl1(cs, "HFCS: stat(%02x) s1(%02x)", stat, val); in hfcs_interrupt()
34 hfc2bds0_interrupt(cs, val); in hfcs_interrupt()
36 if (cs->debug & L1_DEB_ISAC) in hfcs_interrupt()
37 debugl1(cs, "HFCS: irq_no_irq stat(%02x)", stat); in hfcs_interrupt()
39 spin_unlock_irqrestore(&cs->lock, flags); in hfcs_interrupt()
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| D | hfc_sx.c | 3 * level driver for Cologne Chip Designs hfc-s+/sp based cards
25 /* IRQ-table for CCDs demo board */
33 * ISA-SLOT Signal PIN
46 0, 0, 0, 0, 0, 2, 1, 0, 0, 0, 3, 4, 5, 0, 0, 6
50 0, 0, 0, 7, 0, 1, 0, 0, 0, 2, 3, 4, 5, 0, 0, 6
62 Write_hfc(struct IsdnCardState *cs, u_char regnum, u_char val) in Write_hfc() argument
64 byteout(cs->hw.hfcsx.base + 1, regnum); in Write_hfc()
65 byteout(cs->hw.hfcsx.base, val); in Write_hfc()
69 Read_hfc(struct IsdnCardState *cs, u_char regnum) in Read_hfc() argument
73 byteout(cs->hw.hfcsx.base + 1, regnum); in Read_hfc()
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| D | niccy.c | 29 #define ISAC_PCI_DATA 0
33 #define ISAC_PNP 0
41 #define PCI_IRQ_CTRL_REG 0x38
42 #define PCI_IRQ_ENABLE 0x1f00
43 #define PCI_IRQ_DISABLE 0xff0000
44 #define PCI_IRQ_ASSERT 0x800000
78 static u_char ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
80 return readreg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, offset); in ReadISAC()
83 static void WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
85 writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, offset, value); in WriteISAC()
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| D | avm_a1.c | 21 #define AVM_A1_STAT_ISAC 0x01
22 #define AVM_A1_STAT_HSCX 0x02
23 #define AVM_A1_STAT_TIMER 0x04
56 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
58 return (readreg(cs->hw.avm.isac, offset)); in ReadISAC()
62 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
64 writereg(cs->hw.avm.isac, offset, value); in WriteISAC()
68 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
70 read_fifo(cs->hw.avm.isacfifo, data, size); in ReadISACfifo()
74 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
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| D | nj_u.c | 19 static u_char dummyrr(struct IsdnCardState *cs, int chan, u_char off) in dummyrr() argument
24 static void dummywr(struct IsdnCardState *cs, int chan, u_char off, u_char value) in dummywr() argument
31 struct IsdnCardState *cs = dev_id; in netjet_u_interrupt() local
35 spin_lock_irqsave(&cs->lock, flags); in netjet_u_interrupt()
36 if (!((sval = bytein(cs->hw.njet.base + NETJET_IRQSTAT1)) & in netjet_u_interrupt()
38 val = NETjet_ReadIC(cs, ICC_ISTA); in netjet_u_interrupt()
39 if (cs->debug & L1_DEB_ISAC) in netjet_u_interrupt()
40 debugl1(cs, "tiger: i1 %x %x", sval, val); in netjet_u_interrupt()
42 icc_interrupt(cs, val); in netjet_u_interrupt()
43 NETjet_WriteIC(cs, ICC_MASK, 0xFF); in netjet_u_interrupt()
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| D | mic.c | 29 #define MIC_RESET 0x3 /* same as DOS driver */
66 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
68 return (readreg(cs->hw.mic.adr, cs->hw.mic.isac, offset)); in ReadISAC()
72 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
74 writereg(cs->hw.mic.adr, cs->hw.mic.isac, offset, value); in WriteISAC()
78 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
80 readfifo(cs->hw.mic.adr, cs->hw.mic.isac, 0, data, size); in ReadISACfifo()
84 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
86 writefifo(cs->hw.mic.adr, cs->hw.mic.isac, 0, data, size); in WriteISACfifo()
90 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
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| D | nj_s.c | 19 static u_char dummyrr(struct IsdnCardState *cs, int chan, u_char off) in dummyrr() argument
24 static void dummywr(struct IsdnCardState *cs, int chan, u_char off, u_char value) in dummywr() argument
31 struct IsdnCardState *cs = dev_id; in netjet_s_interrupt() local
35 spin_lock_irqsave(&cs->lock, flags); in netjet_s_interrupt()
36 s1val = bytein(cs->hw.njet.base + NETJET_IRQSTAT1); in netjet_s_interrupt()
38 val = NETjet_ReadIC(cs, ISAC_ISTA); in netjet_s_interrupt()
39 if (cs->debug & L1_DEB_ISAC) in netjet_s_interrupt()
40 debugl1(cs, "tiger: i1 %x %x", s1val, val); in netjet_s_interrupt()
42 isac_interrupt(cs, val); in netjet_s_interrupt()
43 NETjet_WriteIC(cs, ISAC_MASK, 0xFF); in netjet_s_interrupt()
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| D | isurf.c | 3 * low level stuff for Siemens I-Surf/I-Talk cards
31 #define ISURF_ISAR_OFFSET 0
32 #define ISURF_ISAC_OFFSET 0x100
33 #define ISURF_IOMEM_SIZE 0x400
37 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
39 return (readb(cs->hw.isurf.isac + offset)); in ReadISAC()
43 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
45 writeb(value, cs->hw.isurf.isac + offset); mb(); in WriteISAC()
49 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
52 for (i = 0; i < size; i++) in ReadISACfifo()
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| D | s0box.c | 23 outb_p(0x1c, padr + 2); in writereg()
24 outb_p(0x14, padr + 2); in writereg()
25 outb_p((addr + off) & 0x7f, padr); in writereg()
26 outb_p(0x16, padr + 2); in writereg()
28 outb_p(0x17, padr + 2); in writereg()
29 outb_p(0x14, padr + 2); in writereg()
30 outb_p(0x1c, padr + 2); in writereg()
33 static u_char nibtab[] = { 1, 9, 5, 0xd, 3, 0xb, 7, 0xf,
34 0, 0, 0, 0, 0, 0, 0, 0,
35 0, 8, 4, 0xc, 2, 0xa, 6, 0xe };
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| D | teleint.c | 32 while (ret && --max_delay) in readreg()
36 return (0); in readreg()
50 for (i = 0; i < size; i++) { in readfifo()
52 while (ret && --max_delay) in readfifo()
71 while (ret && --max_delay) in writereg()
88 for (i = 0; i < size; i++) { in writefifo()
90 while (ret && --max_delay) in writefifo()
103 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
105 cs->hw.hfc.cip = offset; in ReadISAC()
106 return (readreg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, offset)); in ReadISAC()
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| D | jade.c | 24 JadeVersion(struct IsdnCardState *cs, char *s) in JadeVersion() argument
28 cs->BC_Write_Reg(cs, -1, 0x50, 0x19); in JadeVersion()
31 ver = cs->BC_Read_Reg(cs, -1, 0x60); in JadeVersion()
32 to--; in JadeVersion()
37 return (0); in JadeVersion()
43 ver = cs->BC_Read_Reg(cs, -1, 0x60); in JadeVersion()
50 jade_write_indirect(struct IsdnCardState *cs, u_char reg, u_char value) in jade_write_indirect() argument
56 cs->BC_Write_Reg(cs, -1, COMM_JADE + 1, value); in jade_write_indirect()
58 cs->BC_Write_Reg(cs, -1, COMM_JADE, reg); in jade_write_indirect()
63 ret = cs->BC_Read_Reg(cs, -1, COMM_JADE); in jade_write_indirect()
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| /kernel/linux/linux-4.19/drivers/isdn/gigaset/ |
| D | common.c | 37 #define VALID_MINOR 0x01
38 #define VALID_ID 0x02
41 * gigaset_dbg_buffer() - dump data in ASCII and hex for debugging
56 size_t space = sizeof outbuf - 1; in gigaset_dbg_buffer()
60 while (numin--) { in gigaset_dbg_buffer()
63 if (!space--) in gigaset_dbg_buffer()
67 if (c & 0x80) { in gigaset_dbg_buffer()
68 if (!space--) in gigaset_dbg_buffer()
71 c ^= 0x80; in gigaset_dbg_buffer()
73 if (c < 0x20 || c == 0x7f) { in gigaset_dbg_buffer()
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