| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/serial/ |
| D | rs485.txt | 3 The RTS signal is capable of automatically controlling line direction for
4 the built-in half-duplex mode.
5 The properties described hereafter shall be given to a half-duplex capable
9 - rs485-rts-delay: prop-encoded-array <a b> where:
15 - rs485-rts-active-low: drive RTS low when sending (default is high).
16 - linux,rs485-enabled-at-boot-time: empty property telling to enable the rs485
18 - rs485-rx-during-tx: empty property that enables the receiving of data even
23 compatible = "atmel,at91sam9260-usart";
26 atmel,use-dma-rx;
27 atmel,use-dma-tx;
[all …]
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| D | atmel-usart.txt | 4 - compatible: Should be "atmel,<chip>-usart" or "atmel,<chip>-dbgu"
7 For the dbgu UART, use "atmel,<chip>-dbgu", "atmel,<chip>-usart"
8 - reg: Should contain registers location and length
9 - interrupts: Should contain interrupt
10 - clock-names: tuple listing input clock names.
12 - clocks: phandles to input clocks.
15 - atmel,use-dma-rx: use of PDC or DMA for receiving data
16 - atmel,use-dma-tx: use of PDC or DMA for transmitting data
17 - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD line respectively.
20 - add dma bindings for dma transfer:
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mmc/ |
| D | mmci.txt | 11 - compatible : contains "arm,pl18x", "arm,primecell".
12 - vmmc-supply : phandle to the regulator device tree node, mentioned
16 - arm,primecell-periphid : contains the PrimeCell Peripheral ID, it overrides
18 - vqmmc-supply : phandle to the regulator device tree node, mentioned
20 - st,sig-dir-dat0 : bus signal direction pin used for DAT[0].
21 - st,sig-dir-dat2 : bus signal direction pin used for DAT[2].
22 - st,sig-dir-dat31 : bus signal direction pin used for DAT[3] and DAT[1].
23 - st,sig-dir-dat74 : bus signal direction pin used for DAT[4] to DAT[7].
24 - st,sig-dir-cmd : cmd signal direction pin used for CMD.
25 - st,sig-pin-fbclk : feedback clock signal pin used.
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | mmci.txt | 11 - compatible : contains "arm,pl18x", "arm,primecell".
12 - vmmc-supply : phandle to the regulator device tree node, mentioned
16 - arm,primecell-periphid : contains the PrimeCell Peripheral ID, it overrides
18 - resets : phandle to internal reset line.
20 - vqmmc-supply : phandle to the regulator device tree node, mentioned
23 - st,sig-dir-dat0 : bus signal direction pin used for DAT[0].
24 - st,sig-dir-dat2 : bus signal direction pin used for DAT[2].
25 - st,sig-dir-dat31 : bus signal direction pin used for DAT[3] and DAT[1].
26 - st,sig-dir-dat74 : bus signal direction pin used for DAT[4] to DAT[7].
27 - st,sig-dir-cmd : cmd signal direction pin used for CMD.
[all …]
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| /kernel/linux/linux-5.10/drivers/ata/ |
| D | pata_ali.c | 2 * pata_ali.c - ALI 15x3 PATA for new ATA layer
8 * Copyright (C) 1998-2000 Michel Aubry, Maintainer
9 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
10 * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
12 * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
22 * otherwise should do atapi DMA (For now for old we do PIO only for
42 MODULE_PARM_DESC(atapi_dma, "Enable ATAPI DMA (0=disable, 1=enable)");
54 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
55 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
59 .ident = "Toshiba Satellite S1800-814",
[all …]
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| /kernel/linux/linux-4.19/drivers/ata/ |
| D | pata_ali.c | 2 * pata_ali.c - ALI 15x3 PATA for new ATA layer
8 * Copyright (C) 1998-2000 Michel Aubry, Maintainer
9 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
10 * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
12 * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
22 * otherwise should do atapi DMA (For now for old we do PIO only for
42 MODULE_PARM_DESC(atapi_dma, "Enable ATAPI DMA (0=disable, 1=enable)");
54 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
55 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
59 .ident = "Toshiba Satellite S1800-814",
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/ |
| D | owl-dma.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/owl-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Actions Semi Owl SoCs DMA controller
10 The OWL DMA is a general-purpose direct memory access controller capable of
11 supporting 10 and 12 independent DMA channels for S700 and S900 SoCs
15 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 - $ref: "dma-controller.yaml#"
23 - actions,s900-dma
[all …]
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| D | socionext,uniphier-xdmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/socionext,uniphier-xdmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier external DMA controller
10 This describes the devicetree bindings for an external DMA engine to perform
11 memory-to-memory or peripheral-to-memory data transfer capable of supporting
15 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
18 - $ref: "dma-controller.yaml#"
22 const: socionext,uniphier-xdmac
[all …]
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| D | renesas,shdma.txt | 3 Sh-/r-mobile and R-Car systems often have multiple identical DMA controller
4 instances, capable of serving any of a common set of DMA slave devices, using
6 SHDMA DT nodes to be placed under a DMA multiplexer node. All such compatible
7 DMAC instances have the same number of channels and use the same DMA
8 descriptors. Therefore respective DMA DT bindings can also all be placed in the
12 * DMA multiplexer
15 - compatible: should be "renesas,shdma-mux"
16 - #dma-cells: should be <1>, see "dmas" property below
19 - dma-channels: number of DMA channels
20 - dma-requests: number of DMA request signals
[all …]
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| D | st,stm32-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DMA Controller bindings
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
[all …]
|
| D | mv-xor-v2.txt | 4 - compatible: one of the following values:
5 "marvell,armada-7k-xor"
6 "marvell,xor-v2"
7 - reg: Should contain registers location and length (two sets)
8 the first set is the DMA registers
10 - msi-parent: Phandle to the MSI-capable interrupt controller used for
14 - clocks: Optional reference to the clocks used by the XOR engine.
15 - clock-names: mandatory if there is a second clock, in this case the
23 compatible = "marvell,xor-v2";
26 msi-parent = <&gic_v2m0>;
[all …]
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| D | st_fdma.txt | 3 The FDMA is a general-purpose direct memory access controller capable of
4 supporting 16 independent DMA channels. It accepts up to 32 DMA requests.
10 - compatible : Should be one of
11 - st,stih407-fdma-mpe31-11, "st,slim-rproc";
12 - st,stih407-fdma-mpe31-12, "st,slim-rproc";
13 - st,stih407-fdma-mpe31-13, "st,slim-rproc";
14 - reg : Should contain an entry for each name in reg-names
15 - reg-names : Must contain "slimcore", "dmem", "peripherals", "imem" entries
16 - interrupts : Should contain one interrupt shared by all channels
17 - dma-channels : Number of channels supported by the controller
[all …]
|
| /kernel/linux/linux-4.19/Documentation/ |
| D | DMA-API-HOWTO.txt | 2 Dynamic DMA mapping Guide
9 This is a guide to device driver writers on how to use the DMA API
10 with example pseudo-code. For a concise description of the API, see
11 DMA-API.txt.
13 CPU and DMA addresses
16 There are several kinds of addresses involved in the DMA API, and it's
31 registers at an MMIO address, or if it performs DMA to read or write system
37 From a device's point of view, DMA uses the bus address space, but it may
39 supports 64-bit addresses for main memory and PCI BARs, it may use an IOMMU
40 so devices only need to use 32-bit DMA addresses.
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/dma/ |
| D | shdma.txt | 3 Sh-/r-mobile and R-Car systems often have multiple identical DMA controller
4 instances, capable of serving any of a common set of DMA slave devices, using
6 SHDMA DT nodes to be placed under a DMA multiplexer node. All such compatible
7 DMAC instances have the same number of channels and use the same DMA
8 descriptors. Therefore respective DMA DT bindings can also all be placed in the
12 * DMA multiplexer
15 - compatible: should be "renesas,shdma-mux"
16 - #dma-cells: should be <1>, see "dmas" property below
19 - dma-channels: number of DMA channels
20 - dma-requests: number of DMA request signals
[all …]
|
| D | stm32-dma.txt | 1 * STMicroelectronics STM32 DMA controller
3 The STM32 DMA is a general-purpose direct memory access controller capable of
4 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
7 - compatible: Should be "st,stm32-dma"
8 - reg: Should contain DMA registers location and length. This should include
9 all of the per-channel registers.
10 - interrupts: Should contain all of the per-channel DMA interrupts in
11 ascending order with respect to the DMA channel index.
12 - clocks: Should contain the input clock of the DMA instance.
13 - #dma-cells : Must be <4>. See DMA client paragraph for more details.
[all …]
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| D | mv-xor-v2.txt | 4 - compatible: one of the following values:
5 "marvell,armada-7k-xor"
6 "marvell,xor-v2"
7 - reg: Should contain registers location and length (two sets)
8 the first set is the DMA registers
10 - msi-parent: Phandle to the MSI-capable interrupt controller used for
14 - clocks: Optional reference to the clocks used by the XOR engine.
15 - clock-names: mandatory if there is a second clock, in this case the
23 compatible = "marvell,xor-v2";
26 msi-parent = <&gic_v2m0>;
[all …]
|
| D | st_fdma.txt | 3 The FDMA is a general-purpose direct memory access controller capable of
4 supporting 16 independent DMA channels. It accepts up to 32 DMA requests.
10 - compatible : Should be one of
11 - st,stih407-fdma-mpe31-11, "st,slim-rproc";
12 - st,stih407-fdma-mpe31-12, "st,slim-rproc";
13 - st,stih407-fdma-mpe31-13, "st,slim-rproc";
14 - reg : Should contain an entry for each name in reg-names
15 - reg-names : Must contain "slimcore", "dmem", "peripherals", "imem" entries
16 - interrupts : Should contain one interrupt shared by all channels
17 - dma-channels : Number of channels supported by the controller
[all …]
|
| /kernel/linux/linux-5.10/arch/xtensa/include/asm/ |
| D | dma.h | 2 * include/asm-xtensa/dma.h
8 * Copyright (C) 2003 - 2005 Tensilica Inc.
17 * This is only to be defined if we have PC-like DMA.
28 * The maximum virtual address to which DMA transfers
31 * NOTE: This is board (platform) specific, not processor-specific!
33 * NOTE: This assumes DMA transfers can only be performed on
36 * means the maximum possible size of this DMA area is
40 * NOTE: When the entire KSEG area is DMA capable, we subtract
48 #define MAX_DMA_ADDRESS (PAGE_OFFSET + XCHAL_KIO_SIZE - 1)
51 /* Reserve and release a DMA channel */
|
| /kernel/linux/linux-4.19/arch/xtensa/include/asm/ |
| D | dma.h | 2 * include/asm-xtensa/dma.h
8 * Copyright (C) 2003 - 2005 Tensilica Inc.
17 * This is only to be defined if we have PC-like DMA.
28 * The maximum virtual address to which DMA transfers
31 * NOTE: This is board (platform) specific, not processor-specific!
33 * NOTE: This assumes DMA transfers can only be performed on
36 * means the maximum possible size of this DMA area is
40 * NOTE: When the entire KSEG area is DMA capable, we subtract
48 #define MAX_DMA_ADDRESS (PAGE_OFFSET + XCHAL_KIO_SIZE - 1)
51 /* Reserve and release a DMA channel */
|
| /kernel/linux/linux-4.19/drivers/mmc/host/ |
| D | sdhci.h | 2 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
6 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
33 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) argument
161 #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
183 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
227 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
241 /* 4C-4F reserved for more max current */
248 /* 55-57 reserved */
253 /* 60-FB reserved */
260 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/net/ |
| D | keystone-netcp.txt | 6 switch sub-module to send and receive packets. NetCP also includes a packet
10 capable of performing IPSec operations on ingress/egress packets.
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
[all …]
|
| /kernel/linux/linux-4.19/drivers/usb/dwc2/ |
| D | core.h | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * core.h - DesignWare HS OTG Controller common declarations
5 * Copyright (C) 2004-2013 Synopsys, Inc.
16 * 3. The names of the above-listed copyright holders may not be used
50 * - no_printk: Disable tracing
51 * - pr_info: Print this info to the console
52 * - trace_printk: Print this info to trace buffer (good for verbose logging)
61 dev_name(hsotg->dev), ##__VA_ARGS__)
66 dev_name(hsotg->dev), ##__VA_ARGS__)
71 /* dwc2-hsotg declarations */
[all …]
|
| /kernel/linux/linux-5.10/include/uapi/linux/ |
| D | rio_mport_cdev.h | 1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
3 * Copyright (c) 2015-2016, Integrated Device Technology Inc.
11 * License(GPL) Version 2, or the BSD-3 Clause license below:
57 * - memory mapped (MAPPED)
58 * - packet generation from memory (TRANSFER)
83 __u32 cap_sys_size; /* Capable system sizes */
84 __u32 cap_addr_size; /* Capable addressing sizes */
85 __u32 cap_transfer_mode; /* Capable transfer modes */
91 * - incoming port-writes
92 * - incoming doorbells
[all …]
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| /kernel/linux/linux-4.19/include/uapi/linux/ |
| D | rio_mport_cdev.h | 1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
3 * Copyright (c) 2015-2016, Integrated Device Technology Inc.
11 * License(GPL) Version 2, or the BSD-3 Clause license below:
57 * - memory mapped (MAPPED)
58 * - packet generation from memory (TRANSFER)
83 __u32 cap_sys_size; /* Capable system sizes */
84 __u32 cap_addr_size; /* Capable addressing sizes */
85 __u32 cap_transfer_mode; /* Capable transfer modes */
91 * - incoming port-writes
92 * - incoming doorbells
[all …]
|
| /kernel/linux/linux-4.19/Documentation/i2c/ |
| D | DMA-considerations | 2 Linux I2C and DMA
5 Given that i2c is a low-speed bus, over which the majority of messages
6 transferred are small, it is not considered a prime user of DMA access. At this
7 time of writing, only 10% of I2C bus master drivers have DMA support
9 DMA for it will likely add more overhead than a plain PIO transfer.
11 Therefore, it is *not* mandatory that the buffer of an I2C message is DMA safe.
13 rarely used. However, it is recommended to use a DMA-safe buffer if your
14 message size is likely applicable for DMA. Most drivers have this threshold
18 I2C bus master driver is using USB as a bridge, then you need to have DMA
22 -------
[all …]
|