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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/ti/
Ddpll.txt1 Binding for Texas Instruments DPLL clock.
6 register-mapped DPLL with usually two selectable input clocks
12 for the actual DPLL clock.
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
22 "ti,omap4-dpll-clock",
23 "ti,omap4-dpll-x2-clock",
24 "ti,omap4-dpll-core-clock",
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ti/
Ddpll.txt1 Binding for Texas Instruments DPLL clock.
6 register-mapped DPLL with usually two selectable input clocks
12 for the actual DPLL clock.
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
22 "ti,omap4-dpll-clock",
23 "ti,omap4-dpll-x2-clock",
24 "ti,omap4-dpll-core-clock",
[all …]
/kernel/linux/linux-4.19/drivers/clk/ti/
Ddpll3xxx.c2 * OMAP3/4 - specific DPLL control functions
49 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
63 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
132 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
133 * @clk: pointer to a DPLL struct clk
135 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
136 * readiness before returning. Will save and restore the DPLL's
137 * autoidle state across the enable, per the CDP code. If the DPLL
138 * locked successfully, return 0; if the DPLL did not lock in the time
148 pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_lock()
[all …]
Dclkt_dpll.c2 * OMAP2/3/4 DPLL clock functions
28 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
36 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
47 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
48 * From device data manual section 4.3 "DPLL and DLL Specifications".
60 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
61 * @clk: DPLL struct clk to test
64 * Tests whether a particular divider @n will result in a valid DPLL
65 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
78 /* DPLL divider must result in a valid jitter correction val */ in _dpll_test_fint()
[all …]
Ddpll44xx.c2 * OMAP4-specific DPLL control functions
22 * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
23 * can supported when using the DPLL low-power mode. Frequencies are
82 * omap4_dpll_lpmode_recalc - compute DPLL low-power setting
83 * @dd: pointer to the dpll data structure
107 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
108 * @clk: struct clk * of the DPLL to compute the rate for
110 * Compute the output rate for the OMAP4 DPLL represented by @clk.
112 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
130 /* regm4xen adds a multiplier of 4 to DPLL calculations */ in omap4_dpll_regm4xen_recalc()
[all …]
Ddpll.c2 * OMAP DPLL clock support
147 * _register_dpll - low level registration of a DPLL clock
151 * Finalizes DPLL registration process. In case a failure (clk-ref or
215 * Initializes a DPLL x 2 clock from device tree data.
274 * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
275 * @node: device node containing the DPLL info
276 * @ops: ops for the DPLL
277 * @ddt: DPLL data template to use
279 * Initializes a DPLL clock from device tree data.
324 * Special case for OMAP2 DPLL, register order is different due to in of_ti_dpll_setup()
[all …]
/kernel/linux/linux-5.10/drivers/clk/ti/
Ddpll3xxx.c3 * OMAP3/4 - specific DPLL control functions
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
60 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
129 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
130 * @clk: pointer to a DPLL struct clk
132 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
133 * readiness before returning. Will save and restore the DPLL's
134 * autoidle state across the enable, per the CDP code. If the DPLL
135 * locked successfully, return 0; if the DPLL did not lock in the time
145 pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_lock()
[all …]
Dclkt_dpll.c3 * OMAP2/3/4 DPLL clock functions
25 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
33 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
44 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
45 * From device data manual section 4.3 "DPLL and DLL Specifications".
57 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
58 * @clk: DPLL struct clk to test
61 * Tests whether a particular divider @n will result in a valid DPLL
62 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
75 /* DPLL divider must result in a valid jitter correction val */ in _dpll_test_fint()
[all …]
Ddpll44xx.c3 * OMAP4-specific DPLL control functions
19 * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
20 * can supported when using the DPLL low-power mode. Frequencies are
79 * omap4_dpll_lpmode_recalc - compute DPLL low-power setting
80 * @dd: pointer to the dpll data structure
104 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
105 * @clk: struct clk * of the DPLL to compute the rate for
107 * Compute the output rate for the OMAP4 DPLL represented by @clk.
109 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
127 /* regm4xen adds a multiplier of 4 to DPLL calculations */ in omap4_dpll_regm4xen_recalc()
[all …]
Ddpll.c2 * OMAP DPLL clock support
153 * _register_dpll - low level registration of a DPLL clock
157 * Finalizes DPLL registration process. In case a failure (clk-ref or
221 * Initializes a DPLL x 2 clock from device tree data.
278 * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
279 * @node: device node containing the DPLL info
280 * @ops: ops for the DPLL
281 * @ddt: DPLL data template to use
283 * Initializes a DPLL clock from device tree data.
326 * Special case for OMAP2 DPLL, register order is different due to in of_ti_dpll_setup()
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/gma500/
Dpsb_intel_display.c116 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
163 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
165 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
166 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
168 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
172 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
173 dpll |= in psb_intel_crtc_mode_set()
178 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
181 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
184 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in psb_intel_crtc_mode_set()
[all …]
Dmdfld_intel_display.c275 temp = REG_READ(map->dpll); in mdfld_disable_crtc()
281 REG_WRITE(map->dpll, temp); in mdfld_disable_crtc()
282 REG_READ(map->dpll); in mdfld_disable_crtc()
288 /* gating power of DPLL */ in mdfld_disable_crtc()
289 REG_WRITE(map->dpll, temp | MDFLD_PWR_GATE_EN); in mdfld_disable_crtc()
330 /* Enable the DPLL */ in mdfld_crtc_dpms()
331 temp = REG_READ(map->dpll); in mdfld_crtc_dpms()
334 /* When ungating power of DPLL, needs to wait 0.5us in mdfld_crtc_dpms()
338 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
343 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
[all …]
Doaktrail_crtc.c251 /* Enable the DPLL */ in oaktrail_crtc_dpms()
252 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
254 REG_WRITE_WITH_AUX(map->dpll, temp, i); in oaktrail_crtc_dpms()
255 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
258 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
260 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
263 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
265 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
324 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
326 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
[all …]
Dmdfld_device.c197 pipe->dpll = PSB_RVDC32(map->dpll); in mdfld_save_display_registers()
251 u32 dpll; in mdfld_restore_display_registers() local
258 u32 dpll_val = pipe->dpll; in mdfld_restore_display_registers()
283 PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, map->dpll); in mdfld_restore_display_registers()
284 PSB_RVDC32(map->dpll); in mdfld_restore_display_registers()
289 dpll = PSB_RVDC32(map->dpll); in mdfld_restore_display_registers()
291 if (!(dpll & DPLL_VCO_ENABLE)) { in mdfld_restore_display_registers()
293 /* When ungating power of DPLL, needs to wait 0.5us in mdfld_restore_display_registers()
295 if (dpll & MDFLD_PWR_GATE_EN) { in mdfld_restore_display_registers()
296 dpll &= ~MDFLD_PWR_GATE_EN; in mdfld_restore_display_registers()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/gma500/
Dpsb_intel_display.c105 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
152 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
154 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
155 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
157 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
161 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
162 dpll |= in psb_intel_crtc_mode_set()
167 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
170 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
173 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in psb_intel_crtc_mode_set()
[all …]
Doaktrail_crtc.c241 /* Enable the DPLL */ in oaktrail_crtc_dpms()
242 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
244 REG_WRITE_WITH_AUX(map->dpll, temp, i); in oaktrail_crtc_dpms()
245 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
248 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
250 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
253 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
255 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
314 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
316 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
[all …]
Dmdfld_intel_display.c243 temp = REG_READ(map->dpll); in mdfld_disable_crtc()
249 REG_WRITE(map->dpll, temp); in mdfld_disable_crtc()
250 REG_READ(map->dpll); in mdfld_disable_crtc()
256 /* gating power of DPLL */ in mdfld_disable_crtc()
257 REG_WRITE(map->dpll, temp | MDFLD_PWR_GATE_EN); in mdfld_disable_crtc()
298 /* Enable the DPLL */ in mdfld_crtc_dpms()
299 temp = REG_READ(map->dpll); in mdfld_crtc_dpms()
302 /* When ungating power of DPLL, needs to wait 0.5us in mdfld_crtc_dpms()
306 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
311 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
[all …]
Dcdv_intel_display.c206 /* Unlike most Intel display engines, on Cedarview the DPLL registers
208 * DPLL reference clock is on in the DPLL control register, but before
209 * the DPLL is enabled in the DPLL control register.
260 DRM_DEBUG_KMS("use their DPLL for pipe A/B\n"); in cdv_dpll_set_clock_cdv()
583 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
662 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
665 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ in cdv_intel_crtc_mode_set()
666 dpll |= 3; in cdv_intel_crtc_mode_set()
668 /* dpll |= PLL_REF_INPUT_DREFCLK; */ in cdv_intel_crtc_mode_set()
679 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
[all …]
Dmdfld_device.c188 pipe->dpll = PSB_RVDC32(map->dpll); in mdfld_save_display_registers()
242 u32 dpll; in mdfld_restore_display_registers() local
249 u32 dpll_val = pipe->dpll; in mdfld_restore_display_registers()
274 PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, map->dpll); in mdfld_restore_display_registers()
275 PSB_RVDC32(map->dpll); in mdfld_restore_display_registers()
280 dpll = PSB_RVDC32(map->dpll); in mdfld_restore_display_registers()
282 if (!(dpll & DPLL_VCO_ENABLE)) { in mdfld_restore_display_registers()
284 /* When ungating power of DPLL, needs to wait 0.5us in mdfld_restore_display_registers()
286 if (dpll & MDFLD_PWR_GATE_EN) { in mdfld_restore_display_registers()
287 dpll &= ~MDFLD_PWR_GATE_EN; in mdfld_restore_display_registers()
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Dclkt2xxx_dpll.c3 * OMAP2-specific DPLL control functions
21 * _allow_idle - enable DPLL autoidle bits
22 * @clk: struct clk * of the DPLL to operate on
24 * Enable DPLL automatic idle control. The DPLL will enter low-power
26 * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
38 * _deny_idle - prevent DPLL from automatically idling
39 * @clk: struct clk * of the DPLL to operate on
41 * Disable DPLL automatic idle control. No return value.
/kernel/linux/linux-4.19/drivers/gpu/drm/i915/
Dintel_dpll_mgr.h44 * enum intel_dpll_id - possible DPLL ids
46 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.
50 * @DPLL_ID_PRIVATE: non-shared dpll in use
55 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB
59 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB
141 uint32_t dpll; member
152 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
155 * the DPLL.
188 * struct intel_shared_dpll_state - hold the DPLL atomic state
190 * This structure holds an atomic state for the DPLL, that can represent
[all …]
/kernel/linux/linux-4.19/arch/arm/mach-omap2/
Dclkt2xxx_dpll.c2 * OMAP2-specific DPLL control functions
24 * _allow_idle - enable DPLL autoidle bits
25 * @clk: struct clk * of the DPLL to operate on
27 * Enable DPLL automatic idle control. The DPLL will enter low-power
29 * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
41 * _deny_idle - prevent DPLL from automatically idling
42 * @clk: struct clk * of the DPLL to operate on
44 * Disable DPLL automatic idle control. No return value.
/kernel/linux/linux-5.10/include/linux/clk/
Dti.h34 * struct dpll_data - DPLL registers and integration data
35 * @mult_div1_reg: register containing the DPLL M and N bitfields
36 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
37 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
40 * @control_reg: register containing the DPLL mode bitfield
41 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
52 * @max_rate: maximum clock rate for the DPLL
54 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
55 * @idlest_reg: register containing the DPLL idle status bitfield
56 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.h49 * enum intel_dpll_id - possible DPLL ids
51 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.
55 * @DPLL_ID_PRIVATE: non-shared dpll in use
60 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB
64 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB
170 u32 dpll; member
181 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
184 * the DPLL.
216 * struct intel_shared_dpll_state - hold the DPLL atomic state
218 * This structure holds an atomic state for the DPLL, that can represent
[all …]
/kernel/linux/linux-4.19/include/linux/clk/
Dti.h34 * struct dpll_data - DPLL registers and integration data
35 * @mult_div1_reg: register containing the DPLL M and N bitfields
36 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
37 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
40 * @control_reg: register containing the DPLL mode bitfield
41 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
52 * @max_rate: maximum clock rate for the DPLL
54 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
55 * @idlest_reg: register containing the DPLL idle status bitfield
56 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
[all …]

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