| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | brcm,stingray-usb-phy.txt | 1 Broadcom Stingray USB PHY
4 - compatible : should be one of the listed compatibles
5 - "brcm,sr-usb-combo-phy" is combo PHY has two PHYs, one SS and one HS.
6 - "brcm,sr-usb-hs-phy" is a single HS PHY.
7 - reg: offset and length of the PHY blocks registers
8 - #phy-cells:
9 - Must be 1 for brcm,sr-usb-combo-phy as it expects one argument to indicate
10 the PHY number of two PHYs. 0 for HS PHY and 1 for SS PHY.
11 - Must be 0 for brcm,sr-usb-hs-phy.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties
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| D | qcom,usb-hs-phy.txt | 1 Qualcomm's USB HS PHY
5 - compatible:
8 Definition: Should contain "qcom,usb-hs-phy" and more specifically one of the
11 "qcom,usb-hs-phy-apq8064"
12 "qcom,usb-hs-phy-msm8916"
13 "qcom,usb-hs-phy-msm8974"
15 - #phy-cells:
20 - clocks:
22 Value type: <prop-encoded-array>
26 - clock-names:
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| D | qcom,ipq806x-usb-phy-hs.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-hs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm ipq806x usb DWC3 HS PHY CONTROLLER
10 - Ansuel Smith <ansuelsmth@gmail.com>
13 DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
14 controllers used in ipq806x. Each DWC3 PHY controller should have its
19 const: qcom,ipq806x-usb-phy-hs
21 "#phy-cells":
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| D | qcom-usb-ipq4019-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/qcom-usb-ipq4019-phy.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Qualcom IPQ40xx Dakota HS/SS USB PHY
10 - Robert Marko <robert.marko@sartura.hr>
15 - qcom,usb-ss-ipq4019-phy
16 - qcom,usb-hs-ipq4019-phy
24 reset-names:
26 - const: por_rst
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| D | nvidia,tegra20-usb-phy.txt | 1 Tegra SOC USB PHY
3 The device node for Tegra SOC USB PHY:
6 - compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy".
7 For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain
8 "nvidia,<chip>-usb-phy" plus at least one of the above, where <chip> is
10 - reg : Defines the following set of registers, in the order listed:
11 - The PHY's own register set.
13 - The register set of the PHY containing the UTMI pad control registers.
14 Present if-and-only-if phy_type == utmi.
15 - phy_type : Should be one of "utmi", "ulpi" or "hsic".
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| D | qcom,usb-snps-femto-v2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/qcom,usb-snps-femto-v2.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Qualcomm Synopsys Femto High-Speed USB PHY V2
10 - Wesley Cheng <wcheng@codeaurora.org>
13 Qualcomm High-Speed USB PHY
18 - qcom,usb-snps-hs-7nm-phy
19 - qcom,sm8150-usb-hs-phy
20 - qcom,usb-snps-femto-v2-phy
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| D | qcom,usb-hs-28nm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/qcom,usb-hs-28nm.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Qualcomm Synopsys DesignWare Core 28nm High-Speed PHY
10 - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
13 Qualcomm Low-Speed, Full-Speed, Hi-Speed 28nm USB PHY
18 - qcom,usb-hs-28nm-femtophy
23 "#phy-cells":
28 - description: rpmcc ref clock
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| D | socionext,uniphier-usb3hs-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
10 This describes the devicetree bindings for PHY interfaces built into
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-usb3-hsphy
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/phy/ |
| D | qcom,usb-hs-phy.txt | 1 Qualcomm's USB HS PHY
5 - compatible:
8 Definition: Should contain "qcom,usb-hs-phy" and more specifically one of the
11 "qcom,usb-hs-phy-apq8064"
12 "qcom,usb-hs-phy-msm8916"
13 "qcom,usb-hs-phy-msm8974"
15 - #phy-cells:
20 - clocks:
22 Value type: <prop-encoded-array>
26 - clock-names:
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| D | qcom-dwc3-usb-phy.txt | 1 Qualcomm DWC3 HS AND SS PHY CONTROLLER
2 --------------------------------------
4 DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
5 controllers. Each DWC3 PHY controller should have its own node.
8 - compatible: should contain one of the following:
9 - "qcom,dwc3-hs-usb-phy" for High Speed Synopsis PHY controller
10 - "qcom,dwc3-ss-usb-phy" for Super Speed Synopsis PHY controller
11 - reg: offset and length of the DWC3 PHY controller register set
12 - #phy-cells: must be zero
13 - clocks: a list of phandles and clock-specifier pairs, one for each entry in
[all …]
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| D | nvidia,tegra20-usb-phy.txt | 1 Tegra SOC USB PHY
3 The device node for Tegra SOC USB PHY:
6 - compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy".
7 For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain
8 "nvidia,<chip>-usb-phy" plus at least one of the above, where <chip> is
10 - reg : Defines the following set of registers, in the order listed:
11 - The PHY's own register set.
13 - The register set of the PHY containing the UTMI pad control registers.
14 Present if-and-only-if phy_type == utmi.
15 - phy_type : Should be one of "utmi", "ulpi" or "hsic".
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| D | qcom-qusb2-phy.txt | 1 Qualcomm QUSB2 phy controller
4 QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
7 - compatible: compatible list, contains
8 "qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996,
9 "qcom,sdm845-qusb2-phy" for 10nm PHY on sdm845.
11 - reg: offset and length of the PHY register set.
12 - #phy-cells: must be 0.
14 - clocks: a list of phandles and clock-specifier pairs,
15 one for each entry in clock-names.
16 - clock-names: must be "cfg_ahb" for phy config clock,
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/usb/ |
| D | dwc2.txt | 1 Platform DesignWare HS OTG USB 2.0 controller
2 -----------------------------------------------------
5 - compatible : One of:
6 - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC.
7 - hisilicon,hi6220-usb: The DWC2 USB controller instance in the hi6220 SoC.
8 - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
9 - "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc;
10 - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
11 - "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs;
12 - "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs;
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| D | qcom,dwc3.txt | 4 - compatible: Compatible list, contains
6 "qcom,msm8996-dwc3" for msm8996 SOC.
7 "qcom,sdm845-dwc3" for sdm845 SOC.
8 - reg: Offset and length of register set for QSCRATCH wrapper
9 - power-domains: specifies a phandle to PM domain provider node
10 - clocks: A list of phandle + clock-specifier pairs for the
11 clocks listed in clock-names
12 - clock-names: Should contain the following:
14 operation and >= 60MHz for HS operation
22 Not present on "qcom,msm8996-dwc3" compatible.
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| /kernel/linux/linux-5.10/drivers/phy/qualcomm/ |
| D | phy-qcom-snps-femto-v2.c | 1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/phy/phy.h>
63 "vdda-pll", "vdda33", "vdda18",
69 * struct qcom_snps_hsphy - snps hs phy attributes
71 * @phy: generic phy
72 * @base: iomapped memory space for snps hs phy
75 * @ref_clk: phy reference clock
76 * @iface_clk: phy interface clock
77 * @phy_reset: phy reset control
79 * @phy_initialized: if PHY has been initialized correctly
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Qualcomm and Atheros platforms
6 tristate "Atheros AR71XX/9XXX USB PHY driver"
12 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.
15 tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
22 tristate "Qualcomm IPQ4019 USB PHY driver"
26 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
29 tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
36 tristate "Qualcomm PCIe Gen2 PHY Driver"
40 Enable this to support the Qualcomm PCIe PHY, used with the Synopsys
[all …]
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| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_ATH79_USB) += phy-ath79-usb.o
3 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
4 obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
5 obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
6 obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
7 obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o
8 obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
9 obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
10 obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o
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| /kernel/linux/linux-5.10/drivers/phy/st/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for STMicro platforms
6 tristate "STMicroelectronics MIPHY28LP PHY driver for STiH407"
14 tristate "ST SPEAR1310-MIPHY driver"
21 tristate "ST SPEAR1340-MIPHY driver"
37 tristate "STMicroelectronics STM32 USB HS PHY Controller driver"
41 Enable this to support the High-Speed USB transceivers that are part
44 This driver controls the entire USB PHY block: the USB PHY controller
45 (USBPHYC) and the two 8-bit wide UTMI+ interfaces. First interface is
46 used by an HS USB Host controller, and the second one is shared
[all …]
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| /kernel/linux/linux-4.19/drivers/phy/st/ |
| D | Kconfig | 2 # Phy drivers for STMicro platforms
5 tristate "STMicroelectronics MIPHY28LP PHY driver for STiH407"
13 tristate "ST SPEAR1310-MIPHY driver"
20 tristate "ST SPEAR1340-MIPHY driver"
36 tristate "STMicroelectronics STM32 USB HS PHY Controller driver"
40 Enable this to support the High-Speed USB transceivers that are part
43 This driver controls the entire USB PHY block: the USB PHY controller
44 (USBPHYC) and the two 8-bit wide UTMI+ interfaces. First interface is
45 used by an HS USB Host controller, and the second one is shared
46 between an HS USB OTG controller and an HS USB Host controller,
|
| /kernel/linux/linux-5.10/include/linux/phy/ |
| D | phy-mipi-dphy.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
13 * MIPI D-PHY phy.
20 * Clock transitions and disable the Clock Lane HS-RX.
30 * send HS clock after the last associated Data Lane has
41 * Time, in UI, that the HS clock shall be driven by
43 * the transition from LP to HS mode.
53 * Lane LP-00 Line state immediately before the HS-0 Line
54 * state starting the HS transmission.
64 * Time interval, in picoseconds, during which the HS receiver
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| /kernel/linux/linux-4.19/drivers/scsi/ufs/ |
| D | ufs-qcom.c | 2 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
18 #include <linux/phy/phy.h>
19 #include <linux/phy/phy-qcom-ufs.h>
22 #include "ufshcd-pltfrm.h"
24 #include "ufs-qcom.h"
66 dev_err(hba->dev, "%s: couldn't read PA_CONNECTEDTXDATALANES %d\n", in ufs_qcom_get_connected_tx_lanes()
104 if (!host->is_lane_clks_enabled) in ufs_qcom_disable_lane_clks()
107 if (host->hba->lanes_per_direction > 1) in ufs_qcom_disable_lane_clks()
108 clk_disable_unprepare(host->tx_l1_sync_clk); in ufs_qcom_disable_lane_clks()
109 clk_disable_unprepare(host->tx_l0_sync_clk); in ufs_qcom_disable_lane_clks()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/ |
| D | imx7-mipi-csi2.txt | 5 --------------
7 This is the device node for the MIPI CSI-2 receiver core in i.MX7 SoC. It is
8 compatible with previous version of Samsung D-phy.
12 - compatible : "fsl,imx7-mipi-csi2";
13 - reg : base address and length of the register set for the device;
14 - interrupts : should contain MIPI CSIS interrupt;
15 - clocks : list of clock specifiers, see
16 Documentation/devicetree/bindings/clock/clock-bindings.txt for details;
17 - clock-names : must contain "pclk", "wrap" and "phy" entries, matching
19 - power-domains : a phandle to the power domain, see
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| /kernel/linux/linux-5.10/drivers/phy/rockchip/ |
| D | phy-rockchip-dphy-rx0.c | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 * chromeos-4.4 branch.
14 * Jacob Chen <jacob2.chen@rock-chips.com>
15 * Shunqian Zheng <zhengsq@rock-chips.com>
25 #include <linux/phy/phy.h>
26 #include <linux/phy/phy-mipi-dphy.h>
65 "dphy-ref",
66 "dphy-cfg",
111 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
163 const struct dphy_reg *reg = &priv->drv_data->regs[index]; in rk_dphy_write_grf()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/tegra/ |
| D | mipi-phy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include "mipi-phy.h"
12 * Default D-PHY timings based on MIPI D-PHY specification. Derived from the
13 * valid ranges specified in Section 6.9, Table 14, Page 40 of the D-PHY
19 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
20 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
21 timing->clkpre = 8; in mipi_dphy_timing_get_default()
22 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
23 timing->clksettle = 95; in mipi_dphy_timing_get_default()
24 timing->clktermen = 0; in mipi_dphy_timing_get_default()
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| /kernel/linux/linux-5.10/drivers/phy/ |
| D | phy-core-mipi-dphy.c | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/phy/phy.h>
13 #include <linux/phy/phy-mipi-dphy.h>
18 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived
20 * of the D-PHY specification (v2.1).
31 return -EINVAL; in phy_mipi_dphy_get_default_config()
39 cfg->clk_miss = 0; in phy_mipi_dphy_get_default_config()
40 cfg->clk_post = 60000 + 52 * ui; in phy_mipi_dphy_get_default_config()
41 cfg->clk_pre = 8000; in phy_mipi_dphy_get_default_config()
42 cfg->clk_prepare = 38000; in phy_mipi_dphy_get_default_config()
[all …]
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