1Qualcomm SuperSpeed DWC3 USB SoC controller 2 3Required properties: 4- compatible: Compatible list, contains 5 "qcom,dwc3" 6 "qcom,msm8996-dwc3" for msm8996 SOC. 7 "qcom,sdm845-dwc3" for sdm845 SOC. 8- reg: Offset and length of register set for QSCRATCH wrapper 9- power-domains: specifies a phandle to PM domain provider node 10- clocks: A list of phandle + clock-specifier pairs for the 11 clocks listed in clock-names 12- clock-names: Should contain the following: 13 "core" Master/Core clock, have to be >= 125 MHz for SS 14 operation and >= 60MHz for HS operation 15 "mock_utmi" Mock utmi clock needed for ITP/SOF generation in 16 host mode. Its frequency should be 19.2MHz. 17 "sleep" Sleep clock, used for wakeup when USB3 core goes 18 into low power mode (U3). 19 20Optional clocks: 21 "iface" System bus AXI clock. 22 Not present on "qcom,msm8996-dwc3" compatible. 23 "cfg_noc" System Config NOC clock. 24 Not present on "qcom,msm8996-dwc3" compatible. 25- assigned-clocks: Should be: 26 MOCK_UTMI_CLK 27 MASTER_CLK 28- assigned-clock-rates: Should be: 29 19.2Mhz (192000000) for MOCK_UTMI_CLK 30 >=125Mhz (125000000) for MASTER_CLK in SS mode 31 >=60Mhz (60000000) for MASTER_CLK in HS mode 32 33Optional properties: 34- resets: Phandle to reset control that resets core and wrapper. 35- interrupts: specifies interrupts from controller wrapper used 36 to wakeup from low power/susepnd state. Must contain 37 one or more entry for interrupt-names property 38- interrupt-names: Must include the following entries: 39 - "hs_phy_irq": The interrupt that is asserted when a 40 wakeup event is received on USB2 bus 41 - "ss_phy_irq": The interrupt that is asserted when a 42 wakeup event is received on USB3 bus 43 - "dm_hs_phy_irq" and "dp_hs_phy_irq": Separate 44 interrupts for any wakeup event on DM and DP lines 45- qcom,select-utmi-as-pipe-clk: if present, disable USB3 pipe_clk requirement. 46 Used when dwc3 operates without SSPHY and only 47 HS/FS/LS modes are supported. 48 49Required child node: 50A child node must exist to represent the core DWC3 IP block. The name of 51the node is not important. The content of the node is defined in dwc3.txt. 52 53Phy documentation is provided in the following places: 54Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt - USB3 QMP PHY 55Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt - USB2 QUSB2 PHY 56 57Example device nodes: 58 59 hs_phy: phy@100f8800 { 60 compatible = "qcom,qusb2-v2-phy"; 61 ... 62 }; 63 64 ss_phy: phy@100f8830 { 65 compatible = "qcom,qmp-v3-usb3-phy"; 66 ... 67 }; 68 69 usb3_0: usb30@a6f8800 { 70 compatible = "qcom,dwc3"; 71 reg = <0xa6f8800 0x400>; 72 #address-cells = <1>; 73 #size-cells = <1>; 74 ranges; 75 76 interrupts = <0 131 0>, <0 486 0>, <0 488 0>, <0 489 0>; 77 interrupt-names = "hs_phy_irq", "ss_phy_irq", 78 "dm_hs_phy_irq", "dp_hs_phy_irq"; 79 80 clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, 81 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 82 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 83 clock-names = "core", "mock_utmi", "sleep"; 84 85 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 86 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 87 assigned-clock-rates = <19200000>, <133000000>; 88 89 resets = <&gcc GCC_USB30_PRIM_BCR>; 90 reset-names = "core_reset"; 91 power-domains = <&gcc USB30_PRIM_GDSC>; 92 qcom,select-utmi-as-pipe-clk; 93 94 dwc3@10000000 { 95 compatible = "snps,dwc3"; 96 reg = <0x10000000 0xcd00>; 97 interrupts = <0 205 0x4>; 98 phys = <&hs_phy>, <&ss_phy>; 99 phy-names = "usb2-phy", "usb3-phy"; 100 dr_mode = "host"; 101 }; 102 }; 103 104